1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Pin controller and GPIO driver for Amlogic Meson SoCs
4  *
5  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6  */
7 
8 /*
9  * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
10  * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
11  * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
12  * variable number of pins.
13  *
14  * The AO bank is special because it belongs to the Always-On power
15  * domain which can't be powered off; the bank also uses a set of
16  * registers different from the other banks.
17  *
18  * For each pin controller there are 4 different register ranges that
19  * control the following properties of the pins:
20  *  1) pin muxing
21  *  2) pull enable/disable
22  *  3) pull up/down
23  *  4) GPIO direction, output value, input value
24  *
25  * In some cases the register ranges for pull enable and pull
26  * direction are the same and thus there are only 3 register ranges.
27  *
28  * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
29  * and pull direction are the same, so there are only 2 register ranges.
30  *
31  * For the pull and GPIO configuration every bank uses a contiguous
32  * set of bits in the register sets described above; the same register
33  * can be shared by more banks with different offsets.
34  *
35  * In addition to this there are some registers shared between all
36  * banks that control the IRQ functionality. This feature is not
37  * supported at the moment by the driver.
38  */
39 
40 #include <linux/device.h>
41 #include <linux/gpio/driver.h>
42 #include <linux/init.h>
43 #include <linux/io.h>
44 #include <linux/of.h>
45 #include <linux/of_address.h>
46 #include <linux/of_device.h>
47 #include <linux/pinctrl/pinconf-generic.h>
48 #include <linux/pinctrl/pinconf.h>
49 #include <linux/pinctrl/pinctrl.h>
50 #include <linux/pinctrl/pinmux.h>
51 #include <linux/platform_device.h>
52 #include <linux/regmap.h>
53 #include <linux/seq_file.h>
54 
55 #include "../core.h"
56 #include "../pinctrl-utils.h"
57 #include "pinctrl-meson.h"
58 
59 /**
60  * meson_get_bank() - find the bank containing a given pin
61  *
62  * @pc:		the pinctrl instance
63  * @pin:	the pin number
64  * @bank:	the found bank
65  *
66  * Return:	0 on success, a negative value on error
67  */
68 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
69 			  struct meson_bank **bank)
70 {
71 	int i;
72 
73 	for (i = 0; i < pc->data->num_banks; i++) {
74 		if (pin >= pc->data->banks[i].first &&
75 		    pin <= pc->data->banks[i].last) {
76 			*bank = &pc->data->banks[i];
77 			return 0;
78 		}
79 	}
80 
81 	return -EINVAL;
82 }
83 
84 /**
85  * meson_calc_reg_and_bit() - calculate register and bit for a pin
86  *
87  * @bank:	the bank containing the pin
88  * @pin:	the pin number
89  * @reg_type:	the type of register needed (pull-enable, pull, etc...)
90  * @reg:	the computed register offset
91  * @bit:	the computed bit
92  */
93 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
94 				   enum meson_reg_type reg_type,
95 				   unsigned int *reg, unsigned int *bit)
96 {
97 	struct meson_reg_desc *desc = &bank->regs[reg_type];
98 
99 	*reg = desc->reg * 4;
100 	*bit = desc->bit + pin - bank->first;
101 }
102 
103 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
104 {
105 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
106 
107 	return pc->data->num_groups;
108 }
109 
110 static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
111 					unsigned selector)
112 {
113 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
114 
115 	return pc->data->groups[selector].name;
116 }
117 
118 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
119 				const unsigned **pins, unsigned *num_pins)
120 {
121 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
122 
123 	*pins = pc->data->groups[selector].pins;
124 	*num_pins = pc->data->groups[selector].num_pins;
125 
126 	return 0;
127 }
128 
129 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
130 			       unsigned offset)
131 {
132 	seq_printf(s, " %s", dev_name(pcdev->dev));
133 }
134 
135 static const struct pinctrl_ops meson_pctrl_ops = {
136 	.get_groups_count	= meson_get_groups_count,
137 	.get_group_name		= meson_get_group_name,
138 	.get_group_pins		= meson_get_group_pins,
139 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_all,
140 	.dt_free_map		= pinctrl_utils_free_map,
141 	.pin_dbg_show		= meson_pin_dbg_show,
142 };
143 
144 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
145 {
146 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
147 
148 	return pc->data->num_funcs;
149 }
150 
151 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
152 				    unsigned selector)
153 {
154 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
155 
156 	return pc->data->funcs[selector].name;
157 }
158 
159 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
160 			 const char * const **groups,
161 			 unsigned * const num_groups)
162 {
163 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
164 
165 	*groups = pc->data->funcs[selector].groups;
166 	*num_groups = pc->data->funcs[selector].num_groups;
167 
168 	return 0;
169 }
170 
171 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
172 			     unsigned long *configs, unsigned num_configs)
173 {
174 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
175 	struct meson_bank *bank;
176 	enum pin_config_param param;
177 	unsigned int reg, bit;
178 	int i, ret;
179 
180 	ret = meson_get_bank(pc, pin, &bank);
181 	if (ret)
182 		return ret;
183 
184 	for (i = 0; i < num_configs; i++) {
185 		param = pinconf_to_config_param(configs[i]);
186 
187 		switch (param) {
188 		case PIN_CONFIG_BIAS_DISABLE:
189 			dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
190 
191 			meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg,
192 					       &bit);
193 			ret = regmap_update_bits(pc->reg_pullen, reg,
194 						 BIT(bit), 0);
195 			if (ret)
196 				return ret;
197 			break;
198 		case PIN_CONFIG_BIAS_PULL_UP:
199 			dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
200 
201 			meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
202 					       &reg, &bit);
203 			ret = regmap_update_bits(pc->reg_pullen, reg,
204 						 BIT(bit), BIT(bit));
205 			if (ret)
206 				return ret;
207 
208 			meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
209 			ret = regmap_update_bits(pc->reg_pull, reg,
210 						 BIT(bit), BIT(bit));
211 			if (ret)
212 				return ret;
213 			break;
214 		case PIN_CONFIG_BIAS_PULL_DOWN:
215 			dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
216 
217 			meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
218 					       &reg, &bit);
219 			ret = regmap_update_bits(pc->reg_pullen, reg,
220 						 BIT(bit), BIT(bit));
221 			if (ret)
222 				return ret;
223 
224 			meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
225 			ret = regmap_update_bits(pc->reg_pull, reg,
226 						 BIT(bit), 0);
227 			if (ret)
228 				return ret;
229 			break;
230 		default:
231 			return -ENOTSUPP;
232 		}
233 	}
234 
235 	return 0;
236 }
237 
238 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
239 {
240 	struct meson_bank *bank;
241 	unsigned int reg, bit, val;
242 	int ret, conf;
243 
244 	ret = meson_get_bank(pc, pin, &bank);
245 	if (ret)
246 		return ret;
247 
248 	meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
249 
250 	ret = regmap_read(pc->reg_pullen, reg, &val);
251 	if (ret)
252 		return ret;
253 
254 	if (!(val & BIT(bit))) {
255 		conf = PIN_CONFIG_BIAS_DISABLE;
256 	} else {
257 		meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
258 
259 		ret = regmap_read(pc->reg_pull, reg, &val);
260 		if (ret)
261 			return ret;
262 
263 		if (val & BIT(bit))
264 			conf = PIN_CONFIG_BIAS_PULL_UP;
265 		else
266 			conf = PIN_CONFIG_BIAS_PULL_DOWN;
267 	}
268 
269 	return conf;
270 }
271 
272 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
273 			     unsigned long *config)
274 {
275 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
276 	enum pin_config_param param = pinconf_to_config_param(*config);
277 	u16 arg;
278 
279 	switch (param) {
280 	case PIN_CONFIG_BIAS_DISABLE:
281 	case PIN_CONFIG_BIAS_PULL_DOWN:
282 	case PIN_CONFIG_BIAS_PULL_UP:
283 		if (meson_pinconf_get_pull(pc, pin) == param)
284 			arg = 1;
285 		else
286 			return -EINVAL;
287 		break;
288 	default:
289 		return -ENOTSUPP;
290 	}
291 
292 	*config = pinconf_to_config_packed(param, arg);
293 	dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
294 
295 	return 0;
296 }
297 
298 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
299 				   unsigned int num_group,
300 				   unsigned long *configs, unsigned num_configs)
301 {
302 	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
303 	struct meson_pmx_group *group = &pc->data->groups[num_group];
304 	int i;
305 
306 	dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
307 
308 	for (i = 0; i < group->num_pins; i++) {
309 		meson_pinconf_set(pcdev, group->pins[i], configs,
310 				  num_configs);
311 	}
312 
313 	return 0;
314 }
315 
316 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
317 				   unsigned int group, unsigned long *config)
318 {
319 	return -ENOTSUPP;
320 }
321 
322 static const struct pinconf_ops meson_pinconf_ops = {
323 	.pin_config_get		= meson_pinconf_get,
324 	.pin_config_set		= meson_pinconf_set,
325 	.pin_config_group_get	= meson_pinconf_group_get,
326 	.pin_config_group_set	= meson_pinconf_group_set,
327 	.is_generic		= true,
328 };
329 
330 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
331 {
332 	struct meson_pinctrl *pc = gpiochip_get_data(chip);
333 	unsigned int reg, bit;
334 	struct meson_bank *bank;
335 	int ret;
336 
337 	ret = meson_get_bank(pc, gpio, &bank);
338 	if (ret)
339 		return ret;
340 
341 	meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
342 
343 	return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
344 }
345 
346 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
347 				       int value)
348 {
349 	struct meson_pinctrl *pc = gpiochip_get_data(chip);
350 	unsigned int reg, bit;
351 	struct meson_bank *bank;
352 	int ret;
353 
354 	ret = meson_get_bank(pc, gpio, &bank);
355 	if (ret)
356 		return ret;
357 
358 	meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
359 	ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
360 	if (ret)
361 		return ret;
362 
363 	meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
364 	return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
365 				  value ? BIT(bit) : 0);
366 }
367 
368 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
369 {
370 	struct meson_pinctrl *pc = gpiochip_get_data(chip);
371 	unsigned int reg, bit;
372 	struct meson_bank *bank;
373 	int ret;
374 
375 	ret = meson_get_bank(pc, gpio, &bank);
376 	if (ret)
377 		return;
378 
379 	meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
380 	regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
381 			   value ? BIT(bit) : 0);
382 }
383 
384 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
385 {
386 	struct meson_pinctrl *pc = gpiochip_get_data(chip);
387 	unsigned int reg, bit, val;
388 	struct meson_bank *bank;
389 	int ret;
390 
391 	ret = meson_get_bank(pc, gpio, &bank);
392 	if (ret)
393 		return ret;
394 
395 	meson_calc_reg_and_bit(bank, gpio, REG_IN, &reg, &bit);
396 	regmap_read(pc->reg_gpio, reg, &val);
397 
398 	return !!(val & BIT(bit));
399 }
400 
401 static int meson_gpiolib_register(struct meson_pinctrl *pc)
402 {
403 	int ret;
404 
405 	pc->chip.label = pc->data->name;
406 	pc->chip.parent = pc->dev;
407 	pc->chip.request = gpiochip_generic_request;
408 	pc->chip.free = gpiochip_generic_free;
409 	pc->chip.direction_input = meson_gpio_direction_input;
410 	pc->chip.direction_output = meson_gpio_direction_output;
411 	pc->chip.get = meson_gpio_get;
412 	pc->chip.set = meson_gpio_set;
413 	pc->chip.base = -1;
414 	pc->chip.ngpio = pc->data->num_pins;
415 	pc->chip.can_sleep = false;
416 	pc->chip.of_node = pc->of_node;
417 	pc->chip.of_gpio_n_cells = 2;
418 
419 	ret = gpiochip_add_data(&pc->chip, pc);
420 	if (ret) {
421 		dev_err(pc->dev, "can't add gpio chip %s\n",
422 			pc->data->name);
423 		return ret;
424 	}
425 
426 	return 0;
427 }
428 
429 static struct regmap_config meson_regmap_config = {
430 	.reg_bits = 32,
431 	.val_bits = 32,
432 	.reg_stride = 4,
433 };
434 
435 static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
436 					 struct device_node *node, char *name)
437 {
438 	struct resource res;
439 	void __iomem *base;
440 	int i;
441 
442 	i = of_property_match_string(node, "reg-names", name);
443 	if (of_address_to_resource(node, i, &res))
444 		return ERR_PTR(-ENOENT);
445 
446 	base = devm_ioremap_resource(pc->dev, &res);
447 	if (IS_ERR(base))
448 		return ERR_CAST(base);
449 
450 	meson_regmap_config.max_register = resource_size(&res) - 4;
451 	meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
452 						  "%pOFn-%s", node,
453 						  name);
454 	if (!meson_regmap_config.name)
455 		return ERR_PTR(-ENOMEM);
456 
457 	return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
458 }
459 
460 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
461 				  struct device_node *node)
462 {
463 	struct device_node *np, *gpio_np = NULL;
464 
465 	for_each_child_of_node(node, np) {
466 		if (!of_find_property(np, "gpio-controller", NULL))
467 			continue;
468 		if (gpio_np) {
469 			dev_err(pc->dev, "multiple gpio nodes\n");
470 			return -EINVAL;
471 		}
472 		gpio_np = np;
473 	}
474 
475 	if (!gpio_np) {
476 		dev_err(pc->dev, "no gpio node found\n");
477 		return -EINVAL;
478 	}
479 
480 	pc->of_node = gpio_np;
481 
482 	pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
483 	if (IS_ERR(pc->reg_mux)) {
484 		dev_err(pc->dev, "mux registers not found\n");
485 		return PTR_ERR(pc->reg_mux);
486 	}
487 
488 	pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
489 	if (IS_ERR(pc->reg_gpio)) {
490 		dev_err(pc->dev, "gpio registers not found\n");
491 		return PTR_ERR(pc->reg_gpio);
492 	}
493 
494 	pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
495 	/* Use gpio region if pull one is not present */
496 	if (IS_ERR(pc->reg_pull))
497 		pc->reg_pull = pc->reg_gpio;
498 
499 	pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
500 	/* Use pull region if pull-enable one is not present */
501 	if (IS_ERR(pc->reg_pullen))
502 		pc->reg_pullen = pc->reg_pull;
503 
504 	pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
505 	if (IS_ERR(pc->reg_ds)) {
506 		dev_dbg(pc->dev, "ds registers not found - skipping\n");
507 		pc->reg_ds = NULL;
508 	}
509 
510 	return 0;
511 }
512 
513 int meson_pinctrl_probe(struct platform_device *pdev)
514 {
515 	struct device *dev = &pdev->dev;
516 	struct meson_pinctrl *pc;
517 	int ret;
518 
519 	pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
520 	if (!pc)
521 		return -ENOMEM;
522 
523 	pc->dev = dev;
524 	pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
525 
526 	ret = meson_pinctrl_parse_dt(pc, dev->of_node);
527 	if (ret)
528 		return ret;
529 
530 	pc->desc.name		= "pinctrl-meson";
531 	pc->desc.owner		= THIS_MODULE;
532 	pc->desc.pctlops	= &meson_pctrl_ops;
533 	pc->desc.pmxops		= pc->data->pmx_ops;
534 	pc->desc.confops	= &meson_pinconf_ops;
535 	pc->desc.pins		= pc->data->pins;
536 	pc->desc.npins		= pc->data->num_pins;
537 
538 	pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
539 	if (IS_ERR(pc->pcdev)) {
540 		dev_err(pc->dev, "can't register pinctrl device");
541 		return PTR_ERR(pc->pcdev);
542 	}
543 
544 	return meson_gpiolib_register(pc);
545 }
546