1 /* 2 * Pin controller and GPIO driver for Amlogic Meson SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * You should have received a copy of the GNU General Public License 11 * along with this program. If not, see <http://www.gnu.org/licenses/>. 12 */ 13 14 /* 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a 18 * variable number of pins. 19 * 20 * The AO bank is special because it belongs to the Always-On power 21 * domain which can't be powered off; the bank also uses a set of 22 * registers different from the other banks. 23 * 24 * For each pin controller there are 4 different register ranges that 25 * control the following properties of the pins: 26 * 1) pin muxing 27 * 2) pull enable/disable 28 * 3) pull up/down 29 * 4) GPIO direction, output value, input value 30 * 31 * In some cases the register ranges for pull enable and pull 32 * direction are the same and thus there are only 3 register ranges. 33 * 34 * Since Meson G12A SoC, the ao register ranges for gpio, pull enable 35 * and pull direction are the same, so there are only 2 register ranges. 36 * 37 * For the pull and GPIO configuration every bank uses a contiguous 38 * set of bits in the register sets described above; the same register 39 * can be shared by more banks with different offsets. 40 * 41 * In addition to this there are some registers shared between all 42 * banks that control the IRQ functionality. This feature is not 43 * supported at the moment by the driver. 44 */ 45 46 #include <linux/device.h> 47 #include <linux/gpio/driver.h> 48 #include <linux/init.h> 49 #include <linux/io.h> 50 #include <linux/of.h> 51 #include <linux/of_address.h> 52 #include <linux/of_device.h> 53 #include <linux/pinctrl/pinconf-generic.h> 54 #include <linux/pinctrl/pinconf.h> 55 #include <linux/pinctrl/pinctrl.h> 56 #include <linux/pinctrl/pinmux.h> 57 #include <linux/platform_device.h> 58 #include <linux/regmap.h> 59 #include <linux/seq_file.h> 60 61 #include "../core.h" 62 #include "../pinctrl-utils.h" 63 #include "pinctrl-meson.h" 64 65 /** 66 * meson_get_bank() - find the bank containing a given pin 67 * 68 * @pc: the pinctrl instance 69 * @pin: the pin number 70 * @bank: the found bank 71 * 72 * Return: 0 on success, a negative value on error 73 */ 74 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, 75 struct meson_bank **bank) 76 { 77 int i; 78 79 for (i = 0; i < pc->data->num_banks; i++) { 80 if (pin >= pc->data->banks[i].first && 81 pin <= pc->data->banks[i].last) { 82 *bank = &pc->data->banks[i]; 83 return 0; 84 } 85 } 86 87 return -EINVAL; 88 } 89 90 /** 91 * meson_calc_reg_and_bit() - calculate register and bit for a pin 92 * 93 * @bank: the bank containing the pin 94 * @pin: the pin number 95 * @reg_type: the type of register needed (pull-enable, pull, etc...) 96 * @reg: the computed register offset 97 * @bit: the computed bit 98 */ 99 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, 100 enum meson_reg_type reg_type, 101 unsigned int *reg, unsigned int *bit) 102 { 103 struct meson_reg_desc *desc = &bank->regs[reg_type]; 104 105 *reg = desc->reg * 4; 106 *bit = desc->bit + pin - bank->first; 107 } 108 109 static int meson_get_groups_count(struct pinctrl_dev *pcdev) 110 { 111 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 112 113 return pc->data->num_groups; 114 } 115 116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev, 117 unsigned selector) 118 { 119 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 120 121 return pc->data->groups[selector].name; 122 } 123 124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, 125 const unsigned **pins, unsigned *num_pins) 126 { 127 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 128 129 *pins = pc->data->groups[selector].pins; 130 *num_pins = pc->data->groups[selector].num_pins; 131 132 return 0; 133 } 134 135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, 136 unsigned offset) 137 { 138 seq_printf(s, " %s", dev_name(pcdev->dev)); 139 } 140 141 static const struct pinctrl_ops meson_pctrl_ops = { 142 .get_groups_count = meson_get_groups_count, 143 .get_group_name = meson_get_group_name, 144 .get_group_pins = meson_get_group_pins, 145 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 146 .dt_free_map = pinctrl_utils_free_map, 147 .pin_dbg_show = meson_pin_dbg_show, 148 }; 149 150 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) 151 { 152 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 153 154 return pc->data->num_funcs; 155 } 156 157 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 158 unsigned selector) 159 { 160 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 161 162 return pc->data->funcs[selector].name; 163 } 164 165 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 166 const char * const **groups, 167 unsigned * const num_groups) 168 { 169 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 170 171 *groups = pc->data->funcs[selector].groups; 172 *num_groups = pc->data->funcs[selector].num_groups; 173 174 return 0; 175 } 176 177 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 178 unsigned long *configs, unsigned num_configs) 179 { 180 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 181 struct meson_bank *bank; 182 enum pin_config_param param; 183 unsigned int reg, bit; 184 int i, ret; 185 186 ret = meson_get_bank(pc, pin, &bank); 187 if (ret) 188 return ret; 189 190 for (i = 0; i < num_configs; i++) { 191 param = pinconf_to_config_param(configs[i]); 192 193 switch (param) { 194 case PIN_CONFIG_BIAS_DISABLE: 195 dev_dbg(pc->dev, "pin %u: disable bias\n", pin); 196 197 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, 198 &bit); 199 ret = regmap_update_bits(pc->reg_pullen, reg, 200 BIT(bit), 0); 201 if (ret) 202 return ret; 203 break; 204 case PIN_CONFIG_BIAS_PULL_UP: 205 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); 206 207 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, 208 ®, &bit); 209 ret = regmap_update_bits(pc->reg_pullen, reg, 210 BIT(bit), BIT(bit)); 211 if (ret) 212 return ret; 213 214 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 215 ret = regmap_update_bits(pc->reg_pull, reg, 216 BIT(bit), BIT(bit)); 217 if (ret) 218 return ret; 219 break; 220 case PIN_CONFIG_BIAS_PULL_DOWN: 221 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); 222 223 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, 224 ®, &bit); 225 ret = regmap_update_bits(pc->reg_pullen, reg, 226 BIT(bit), BIT(bit)); 227 if (ret) 228 return ret; 229 230 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 231 ret = regmap_update_bits(pc->reg_pull, reg, 232 BIT(bit), 0); 233 if (ret) 234 return ret; 235 break; 236 default: 237 return -ENOTSUPP; 238 } 239 } 240 241 return 0; 242 } 243 244 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) 245 { 246 struct meson_bank *bank; 247 unsigned int reg, bit, val; 248 int ret, conf; 249 250 ret = meson_get_bank(pc, pin, &bank); 251 if (ret) 252 return ret; 253 254 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); 255 256 ret = regmap_read(pc->reg_pullen, reg, &val); 257 if (ret) 258 return ret; 259 260 if (!(val & BIT(bit))) { 261 conf = PIN_CONFIG_BIAS_DISABLE; 262 } else { 263 meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); 264 265 ret = regmap_read(pc->reg_pull, reg, &val); 266 if (ret) 267 return ret; 268 269 if (val & BIT(bit)) 270 conf = PIN_CONFIG_BIAS_PULL_UP; 271 else 272 conf = PIN_CONFIG_BIAS_PULL_DOWN; 273 } 274 275 return conf; 276 } 277 278 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, 279 unsigned long *config) 280 { 281 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 282 enum pin_config_param param = pinconf_to_config_param(*config); 283 u16 arg; 284 285 switch (param) { 286 case PIN_CONFIG_BIAS_DISABLE: 287 case PIN_CONFIG_BIAS_PULL_DOWN: 288 case PIN_CONFIG_BIAS_PULL_UP: 289 if (meson_pinconf_get_pull(pc, pin) == param) 290 arg = 1; 291 else 292 return -EINVAL; 293 break; 294 default: 295 return -ENOTSUPP; 296 } 297 298 *config = pinconf_to_config_packed(param, arg); 299 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); 300 301 return 0; 302 } 303 304 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, 305 unsigned int num_group, 306 unsigned long *configs, unsigned num_configs) 307 { 308 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 309 struct meson_pmx_group *group = &pc->data->groups[num_group]; 310 int i; 311 312 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); 313 314 for (i = 0; i < group->num_pins; i++) { 315 meson_pinconf_set(pcdev, group->pins[i], configs, 316 num_configs); 317 } 318 319 return 0; 320 } 321 322 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 323 unsigned int group, unsigned long *config) 324 { 325 return -ENOTSUPP; 326 } 327 328 static const struct pinconf_ops meson_pinconf_ops = { 329 .pin_config_get = meson_pinconf_get, 330 .pin_config_set = meson_pinconf_set, 331 .pin_config_group_get = meson_pinconf_group_get, 332 .pin_config_group_set = meson_pinconf_group_set, 333 .is_generic = true, 334 }; 335 336 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 337 { 338 struct meson_pinctrl *pc = gpiochip_get_data(chip); 339 unsigned int reg, bit; 340 struct meson_bank *bank; 341 int ret; 342 343 ret = meson_get_bank(pc, gpio, &bank); 344 if (ret) 345 return ret; 346 347 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 348 349 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); 350 } 351 352 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 353 int value) 354 { 355 struct meson_pinctrl *pc = gpiochip_get_data(chip); 356 unsigned int reg, bit; 357 struct meson_bank *bank; 358 int ret; 359 360 ret = meson_get_bank(pc, gpio, &bank); 361 if (ret) 362 return ret; 363 364 meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); 365 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); 366 if (ret) 367 return ret; 368 369 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 370 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 371 value ? BIT(bit) : 0); 372 } 373 374 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 375 { 376 struct meson_pinctrl *pc = gpiochip_get_data(chip); 377 unsigned int reg, bit; 378 struct meson_bank *bank; 379 int ret; 380 381 ret = meson_get_bank(pc, gpio, &bank); 382 if (ret) 383 return; 384 385 meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); 386 regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 387 value ? BIT(bit) : 0); 388 } 389 390 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 391 { 392 struct meson_pinctrl *pc = gpiochip_get_data(chip); 393 unsigned int reg, bit, val; 394 struct meson_bank *bank; 395 int ret; 396 397 ret = meson_get_bank(pc, gpio, &bank); 398 if (ret) 399 return ret; 400 401 meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); 402 regmap_read(pc->reg_gpio, reg, &val); 403 404 return !!(val & BIT(bit)); 405 } 406 407 static int meson_gpiolib_register(struct meson_pinctrl *pc) 408 { 409 int ret; 410 411 pc->chip.label = pc->data->name; 412 pc->chip.parent = pc->dev; 413 pc->chip.request = gpiochip_generic_request; 414 pc->chip.free = gpiochip_generic_free; 415 pc->chip.direction_input = meson_gpio_direction_input; 416 pc->chip.direction_output = meson_gpio_direction_output; 417 pc->chip.get = meson_gpio_get; 418 pc->chip.set = meson_gpio_set; 419 pc->chip.base = -1; 420 pc->chip.ngpio = pc->data->num_pins; 421 pc->chip.can_sleep = false; 422 pc->chip.of_node = pc->of_node; 423 pc->chip.of_gpio_n_cells = 2; 424 425 ret = gpiochip_add_data(&pc->chip, pc); 426 if (ret) { 427 dev_err(pc->dev, "can't add gpio chip %s\n", 428 pc->data->name); 429 return ret; 430 } 431 432 return 0; 433 } 434 435 static struct regmap_config meson_regmap_config = { 436 .reg_bits = 32, 437 .val_bits = 32, 438 .reg_stride = 4, 439 }; 440 441 static struct regmap *meson_map_resource(struct meson_pinctrl *pc, 442 struct device_node *node, char *name) 443 { 444 struct resource res; 445 void __iomem *base; 446 int i; 447 448 i = of_property_match_string(node, "reg-names", name); 449 if (of_address_to_resource(node, i, &res)) 450 return ERR_PTR(-ENOENT); 451 452 base = devm_ioremap_resource(pc->dev, &res); 453 if (IS_ERR(base)) 454 return ERR_CAST(base); 455 456 meson_regmap_config.max_register = resource_size(&res) - 4; 457 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, 458 "%pOFn-%s", node, 459 name); 460 if (!meson_regmap_config.name) 461 return ERR_PTR(-ENOMEM); 462 463 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); 464 } 465 466 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, 467 struct device_node *node) 468 { 469 struct device_node *np, *gpio_np = NULL; 470 471 for_each_child_of_node(node, np) { 472 if (!of_find_property(np, "gpio-controller", NULL)) 473 continue; 474 if (gpio_np) { 475 dev_err(pc->dev, "multiple gpio nodes\n"); 476 return -EINVAL; 477 } 478 gpio_np = np; 479 } 480 481 if (!gpio_np) { 482 dev_err(pc->dev, "no gpio node found\n"); 483 return -EINVAL; 484 } 485 486 pc->of_node = gpio_np; 487 488 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); 489 if (IS_ERR(pc->reg_mux)) { 490 dev_err(pc->dev, "mux registers not found\n"); 491 return PTR_ERR(pc->reg_mux); 492 } 493 494 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); 495 if (IS_ERR(pc->reg_gpio)) { 496 dev_err(pc->dev, "gpio registers not found\n"); 497 return PTR_ERR(pc->reg_gpio); 498 } 499 500 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); 501 /* Use gpio region if pull one is not present */ 502 if (IS_ERR(pc->reg_pull)) 503 pc->reg_pull = pc->reg_gpio; 504 505 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); 506 /* Use pull region if pull-enable one is not present */ 507 if (IS_ERR(pc->reg_pullen)) 508 pc->reg_pullen = pc->reg_pull; 509 510 pc->reg_ds = meson_map_resource(pc, gpio_np, "ds"); 511 if (IS_ERR(pc->reg_ds)) { 512 dev_dbg(pc->dev, "ds registers not found - skipping\n"); 513 pc->reg_ds = NULL; 514 } 515 516 return 0; 517 } 518 519 int meson_pinctrl_probe(struct platform_device *pdev) 520 { 521 struct device *dev = &pdev->dev; 522 struct meson_pinctrl *pc; 523 int ret; 524 525 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); 526 if (!pc) 527 return -ENOMEM; 528 529 pc->dev = dev; 530 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); 531 532 ret = meson_pinctrl_parse_dt(pc, dev->of_node); 533 if (ret) 534 return ret; 535 536 pc->desc.name = "pinctrl-meson"; 537 pc->desc.owner = THIS_MODULE; 538 pc->desc.pctlops = &meson_pctrl_ops; 539 pc->desc.pmxops = pc->data->pmx_ops; 540 pc->desc.confops = &meson_pinconf_ops; 541 pc->desc.pins = pc->data->pins; 542 pc->desc.npins = pc->data->num_pins; 543 544 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); 545 if (IS_ERR(pc->pcdev)) { 546 dev_err(pc->dev, "can't register pinctrl device"); 547 return PTR_ERR(pc->pcdev); 548 } 549 550 return meson_gpiolib_register(pc); 551 } 552