1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin 4 * bindings for MediaTek SoC. 5 * 6 * Copyright (C) 2018 MediaTek Inc. 7 * Author: Sean Wang <sean.wang@mediatek.com> 8 * Zhiyong Tao <zhiyong.tao@mediatek.com> 9 * Hongzhou.Yang <hongzhou.yang@mediatek.com> 10 */ 11 12 #include <linux/gpio/driver.h> 13 #include <dt-bindings/pinctrl/mt65xx.h> 14 #include "pinctrl-paris.h" 15 16 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME 17 18 /* Custom pinconf parameters */ 19 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) 20 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) 21 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) 22 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) 23 24 static const struct pinconf_generic_params mtk_custom_bindings[] = { 25 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, 26 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, 27 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, 28 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, 29 }; 30 31 #ifdef CONFIG_DEBUG_FS 32 static const struct pin_config_item mtk_conf_items[] = { 33 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), 34 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), 35 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), 36 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), 37 }; 38 #endif 39 40 static const char * const mtk_gpio_functions[] = { 41 "func0", "func1", "func2", "func3", 42 "func4", "func5", "func6", "func7", 43 "func8", "func9", "func10", "func11", 44 "func12", "func13", "func14", "func15", 45 }; 46 47 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, 48 struct pinctrl_gpio_range *range, 49 unsigned int pin) 50 { 51 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 52 const struct mtk_pin_desc *desc; 53 54 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; 55 56 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, 57 hw->soc->gpio_m); 58 } 59 60 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 61 struct pinctrl_gpio_range *range, 62 unsigned int pin, bool input) 63 { 64 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 65 const struct mtk_pin_desc *desc; 66 67 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; 68 69 /* hardware would take 0 as input direction */ 70 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); 71 } 72 73 static int mtk_pinconf_get(struct pinctrl_dev *pctldev, 74 unsigned int pin, unsigned long *config) 75 { 76 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 77 u32 param = pinconf_to_config_param(*config); 78 int val, val2, err, reg, ret = 1; 79 const struct mtk_pin_desc *desc; 80 81 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; 82 83 switch (param) { 84 case PIN_CONFIG_BIAS_DISABLE: 85 if (hw->soc->bias_disable_get) { 86 err = hw->soc->bias_disable_get(hw, desc, &ret); 87 if (err) 88 return err; 89 } else { 90 return -ENOTSUPP; 91 } 92 break; 93 case PIN_CONFIG_BIAS_PULL_UP: 94 if (hw->soc->bias_get) { 95 err = hw->soc->bias_get(hw, desc, 1, &ret); 96 if (err) 97 return err; 98 } else { 99 return -ENOTSUPP; 100 } 101 break; 102 case PIN_CONFIG_BIAS_PULL_DOWN: 103 if (hw->soc->bias_get) { 104 err = hw->soc->bias_get(hw, desc, 0, &ret); 105 if (err) 106 return err; 107 } else { 108 return -ENOTSUPP; 109 } 110 break; 111 case PIN_CONFIG_SLEW_RATE: 112 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val); 113 if (err) 114 return err; 115 116 if (!val) 117 return -EINVAL; 118 119 break; 120 case PIN_CONFIG_INPUT_ENABLE: 121 case PIN_CONFIG_OUTPUT_ENABLE: 122 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); 123 if (err) 124 return err; 125 126 /* HW takes input mode as zero; output mode as non-zero */ 127 if ((val && param == PIN_CONFIG_INPUT_ENABLE) || 128 (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) 129 return -EINVAL; 130 131 break; 132 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 133 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val); 134 if (err) 135 return err; 136 137 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2); 138 if (err) 139 return err; 140 141 if (val || !val2) 142 return -EINVAL; 143 144 break; 145 case PIN_CONFIG_DRIVE_STRENGTH: 146 if (hw->soc->drive_get) { 147 err = hw->soc->drive_get(hw, desc, &ret); 148 if (err) 149 return err; 150 } else { 151 err = -ENOTSUPP; 152 } 153 break; 154 case MTK_PIN_CONFIG_TDSEL: 155 case MTK_PIN_CONFIG_RDSEL: 156 reg = (param == MTK_PIN_CONFIG_TDSEL) ? 157 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; 158 159 err = mtk_hw_get_value(hw, desc, reg, &val); 160 if (err) 161 return err; 162 163 ret = val; 164 165 break; 166 case MTK_PIN_CONFIG_PU_ADV: 167 case MTK_PIN_CONFIG_PD_ADV: 168 if (hw->soc->adv_pull_get) { 169 bool pullup; 170 171 pullup = param == MTK_PIN_CONFIG_PU_ADV; 172 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); 173 if (err) 174 return err; 175 } else { 176 return -ENOTSUPP; 177 } 178 break; 179 default: 180 return -ENOTSUPP; 181 } 182 183 *config = pinconf_to_config_packed(param, ret); 184 185 return 0; 186 } 187 188 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 189 enum pin_config_param param, 190 enum pin_config_param arg) 191 { 192 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 193 const struct mtk_pin_desc *desc; 194 int err = 0; 195 u32 reg; 196 197 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; 198 199 switch ((u32)param) { 200 case PIN_CONFIG_BIAS_DISABLE: 201 if (hw->soc->bias_disable_set) { 202 err = hw->soc->bias_disable_set(hw, desc); 203 if (err) 204 return err; 205 } else { 206 return -ENOTSUPP; 207 } 208 break; 209 case PIN_CONFIG_BIAS_PULL_UP: 210 if (hw->soc->bias_set) { 211 err = hw->soc->bias_set(hw, desc, 1); 212 if (err) 213 return err; 214 } else { 215 return -ENOTSUPP; 216 } 217 break; 218 case PIN_CONFIG_BIAS_PULL_DOWN: 219 if (hw->soc->bias_set) { 220 err = hw->soc->bias_set(hw, desc, 0); 221 if (err) 222 return err; 223 } else { 224 return -ENOTSUPP; 225 } 226 break; 227 case PIN_CONFIG_OUTPUT_ENABLE: 228 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, 229 MTK_DISABLE); 230 if (err) 231 goto err; 232 233 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, 234 MTK_OUTPUT); 235 if (err) 236 goto err; 237 break; 238 case PIN_CONFIG_INPUT_ENABLE: 239 if (hw->soc->ies_present) { 240 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, 241 MTK_ENABLE); 242 } 243 244 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, 245 MTK_INPUT); 246 if (err) 247 goto err; 248 break; 249 case PIN_CONFIG_SLEW_RATE: 250 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, 251 arg); 252 if (err) 253 goto err; 254 255 break; 256 case PIN_CONFIG_OUTPUT: 257 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, 258 MTK_OUTPUT); 259 if (err) 260 goto err; 261 262 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, 263 arg); 264 if (err) 265 goto err; 266 break; 267 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 268 /* arg = 1: Input mode & SMT enable ; 269 * arg = 0: Output mode & SMT disable 270 */ 271 arg = arg ? 2 : 1; 272 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, 273 arg & 1); 274 if (err) 275 goto err; 276 277 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, 278 !!(arg & 2)); 279 if (err) 280 goto err; 281 break; 282 case PIN_CONFIG_DRIVE_STRENGTH: 283 if (hw->soc->drive_set) { 284 err = hw->soc->drive_set(hw, desc, arg); 285 if (err) 286 return err; 287 } else { 288 return -ENOTSUPP; 289 } 290 break; 291 case MTK_PIN_CONFIG_TDSEL: 292 case MTK_PIN_CONFIG_RDSEL: 293 reg = (param == MTK_PIN_CONFIG_TDSEL) ? 294 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; 295 296 err = mtk_hw_set_value(hw, desc, reg, arg); 297 if (err) 298 goto err; 299 break; 300 case MTK_PIN_CONFIG_PU_ADV: 301 case MTK_PIN_CONFIG_PD_ADV: 302 if (hw->soc->adv_pull_set) { 303 bool pullup; 304 305 pullup = param == MTK_PIN_CONFIG_PU_ADV; 306 err = hw->soc->adv_pull_set(hw, desc, pullup, 307 arg); 308 if (err) 309 return err; 310 } else { 311 return -ENOTSUPP; 312 } 313 break; 314 default: 315 err = -ENOTSUPP; 316 } 317 318 err: 319 return err; 320 } 321 322 static struct mtk_pinctrl_group * 323 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin) 324 { 325 int i; 326 327 for (i = 0; i < hw->soc->ngrps; i++) { 328 struct mtk_pinctrl_group *grp = hw->groups + i; 329 330 if (grp->pin == pin) 331 return grp; 332 } 333 334 return NULL; 335 } 336 337 static const struct mtk_func_desc * 338 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum) 339 { 340 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num; 341 const struct mtk_func_desc *func = pin->funcs; 342 343 while (func && func->name) { 344 if (func->muxval == fnum) 345 return func; 346 func++; 347 } 348 349 return NULL; 350 } 351 352 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num, 353 u32 fnum) 354 { 355 int i; 356 357 for (i = 0; i < hw->soc->npins; i++) { 358 const struct mtk_pin_desc *pin = hw->soc->pins + i; 359 360 if (pin->number == pin_num) { 361 const struct mtk_func_desc *func = pin->funcs; 362 363 while (func && func->name) { 364 if (func->muxval == fnum) 365 return true; 366 func++; 367 } 368 369 break; 370 } 371 } 372 373 return false; 374 } 375 376 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 377 u32 pin, u32 fnum, 378 struct mtk_pinctrl_group *grp, 379 struct pinctrl_map **map, 380 unsigned *reserved_maps, 381 unsigned *num_maps) 382 { 383 bool ret; 384 385 if (*num_maps == *reserved_maps) 386 return -ENOSPC; 387 388 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 389 (*map)[*num_maps].data.mux.group = grp->name; 390 391 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 392 if (!ret) { 393 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 394 fnum, pin); 395 return -EINVAL; 396 } 397 398 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 399 (*num_maps)++; 400 401 return 0; 402 } 403 404 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 405 struct device_node *node, 406 struct pinctrl_map **map, 407 unsigned *reserved_maps, 408 unsigned *num_maps) 409 { 410 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 411 int num_pins, num_funcs, maps_per_pin, i, err; 412 struct mtk_pinctrl_group *grp; 413 unsigned int num_configs; 414 bool has_config = false; 415 unsigned long *configs; 416 u32 pinfunc, pin, func; 417 struct property *pins; 418 unsigned reserve = 0; 419 420 pins = of_find_property(node, "pinmux", NULL); 421 if (!pins) { 422 dev_err(hw->dev, "missing pins property in node %pOFn .\n", 423 node); 424 return -EINVAL; 425 } 426 427 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 428 &num_configs); 429 if (err) 430 return err; 431 432 if (num_configs) 433 has_config = true; 434 435 num_pins = pins->length / sizeof(u32); 436 num_funcs = num_pins; 437 maps_per_pin = 0; 438 if (num_funcs) 439 maps_per_pin++; 440 if (has_config && num_pins >= 1) 441 maps_per_pin++; 442 443 if (!num_pins || !maps_per_pin) { 444 err = -EINVAL; 445 goto exit; 446 } 447 448 reserve = num_pins * maps_per_pin; 449 450 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, 451 reserve); 452 if (err < 0) 453 goto exit; 454 455 for (i = 0; i < num_pins; i++) { 456 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc); 457 if (err) 458 goto exit; 459 460 pin = MTK_GET_PIN_NO(pinfunc); 461 func = MTK_GET_PIN_FUNC(pinfunc); 462 463 if (pin >= hw->soc->npins || 464 func >= ARRAY_SIZE(mtk_gpio_functions)) { 465 dev_err(hw->dev, "invalid pins value.\n"); 466 err = -EINVAL; 467 goto exit; 468 } 469 470 grp = mtk_pctrl_find_group_by_pin(hw, pin); 471 if (!grp) { 472 dev_err(hw->dev, "unable to match pin %d to group\n", 473 pin); 474 err = -EINVAL; 475 goto exit; 476 } 477 478 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map, 479 reserved_maps, num_maps); 480 if (err < 0) 481 goto exit; 482 483 if (has_config) { 484 err = pinctrl_utils_add_map_configs(pctldev, map, 485 reserved_maps, 486 num_maps, 487 grp->name, 488 configs, 489 num_configs, 490 PIN_MAP_TYPE_CONFIGS_GROUP); 491 if (err < 0) 492 goto exit; 493 } 494 } 495 496 err = 0; 497 498 exit: 499 kfree(configs); 500 return err; 501 } 502 503 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 504 struct device_node *np_config, 505 struct pinctrl_map **map, 506 unsigned *num_maps) 507 { 508 struct device_node *np; 509 unsigned reserved_maps; 510 int ret; 511 512 *map = NULL; 513 *num_maps = 0; 514 reserved_maps = 0; 515 516 for_each_child_of_node(np_config, np) { 517 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 518 &reserved_maps, 519 num_maps); 520 if (ret < 0) { 521 pinctrl_utils_free_map(pctldev, *map, *num_maps); 522 of_node_put(np); 523 return ret; 524 } 525 } 526 527 return 0; 528 } 529 530 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 531 { 532 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 533 534 return hw->soc->ngrps; 535 } 536 537 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 538 unsigned group) 539 { 540 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 541 542 return hw->groups[group].name; 543 } 544 545 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 546 unsigned group, const unsigned **pins, 547 unsigned *num_pins) 548 { 549 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 550 551 *pins = (unsigned *)&hw->groups[group].pin; 552 *num_pins = 1; 553 554 return 0; 555 } 556 557 static const struct pinctrl_ops mtk_pctlops = { 558 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 559 .dt_free_map = pinctrl_utils_free_map, 560 .get_groups_count = mtk_pctrl_get_groups_count, 561 .get_group_name = mtk_pctrl_get_group_name, 562 .get_group_pins = mtk_pctrl_get_group_pins, 563 }; 564 565 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 566 { 567 return ARRAY_SIZE(mtk_gpio_functions); 568 } 569 570 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 571 unsigned selector) 572 { 573 return mtk_gpio_functions[selector]; 574 } 575 576 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 577 unsigned function, 578 const char * const **groups, 579 unsigned * const num_groups) 580 { 581 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 582 583 *groups = hw->grp_names; 584 *num_groups = hw->soc->ngrps; 585 586 return 0; 587 } 588 589 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 590 unsigned function, 591 unsigned group) 592 { 593 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 594 struct mtk_pinctrl_group *grp = hw->groups + group; 595 const struct mtk_func_desc *desc_func; 596 const struct mtk_pin_desc *desc; 597 bool ret; 598 599 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function); 600 if (!ret) { 601 dev_err(hw->dev, "invalid function %d on group %d .\n", 602 function, group); 603 return -EINVAL; 604 } 605 606 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function); 607 if (!desc_func) 608 return -EINVAL; 609 610 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin]; 611 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval); 612 613 return 0; 614 } 615 616 static const struct pinmux_ops mtk_pmxops = { 617 .get_functions_count = mtk_pmx_get_funcs_cnt, 618 .get_function_name = mtk_pmx_get_func_name, 619 .get_function_groups = mtk_pmx_get_func_groups, 620 .set_mux = mtk_pmx_set_mux, 621 .gpio_set_direction = mtk_pinmux_gpio_set_direction, 622 .gpio_request_enable = mtk_pinmux_gpio_request_enable, 623 }; 624 625 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, 626 unsigned long *config) 627 { 628 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 629 630 *config = hw->groups[group].config; 631 632 return 0; 633 } 634 635 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 636 unsigned long *configs, unsigned num_configs) 637 { 638 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 639 struct mtk_pinctrl_group *grp = &hw->groups[group]; 640 int i, ret; 641 642 for (i = 0; i < num_configs; i++) { 643 ret = mtk_pinconf_set(pctldev, grp->pin, 644 pinconf_to_config_param(configs[i]), 645 pinconf_to_config_argument(configs[i])); 646 if (ret < 0) 647 return ret; 648 649 grp->config = configs[i]; 650 } 651 652 return 0; 653 } 654 655 static const struct pinconf_ops mtk_confops = { 656 .pin_config_get = mtk_pinconf_get, 657 .pin_config_group_get = mtk_pconf_group_get, 658 .pin_config_group_set = mtk_pconf_group_set, 659 }; 660 661 static struct pinctrl_desc mtk_desc = { 662 .name = PINCTRL_PINCTRL_DEV, 663 .pctlops = &mtk_pctlops, 664 .pmxops = &mtk_pmxops, 665 .confops = &mtk_confops, 666 .owner = THIS_MODULE, 667 }; 668 669 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 670 { 671 struct mtk_pinctrl *hw = gpiochip_get_data(chip); 672 const struct mtk_pin_desc *desc; 673 int value, err; 674 675 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; 676 677 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value); 678 if (err) 679 return err; 680 681 return !value; 682 } 683 684 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) 685 { 686 struct mtk_pinctrl *hw = gpiochip_get_data(chip); 687 const struct mtk_pin_desc *desc; 688 int value, err; 689 690 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; 691 692 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); 693 if (err) 694 return err; 695 696 return !!value; 697 } 698 699 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 700 { 701 struct mtk_pinctrl *hw = gpiochip_get_data(chip); 702 const struct mtk_pin_desc *desc; 703 704 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; 705 706 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); 707 } 708 709 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 710 { 711 return pinctrl_gpio_direction_input(chip->base + gpio); 712 } 713 714 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 715 int value) 716 { 717 mtk_gpio_set(chip, gpio, value); 718 719 return pinctrl_gpio_direction_output(chip->base + gpio); 720 } 721 722 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 723 { 724 struct mtk_pinctrl *hw = gpiochip_get_data(chip); 725 const struct mtk_pin_desc *desc; 726 727 if (!hw->eint) 728 return -ENOTSUPP; 729 730 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; 731 732 if (desc->eint.eint_n == EINT_NA) 733 return -ENOTSUPP; 734 735 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n); 736 } 737 738 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 739 unsigned long config) 740 { 741 struct mtk_pinctrl *hw = gpiochip_get_data(chip); 742 const struct mtk_pin_desc *desc; 743 u32 debounce; 744 745 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; 746 747 if (!hw->eint || 748 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || 749 desc->eint.eint_n == EINT_NA) 750 return -ENOTSUPP; 751 752 debounce = pinconf_to_config_argument(config); 753 754 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); 755 } 756 757 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) 758 { 759 struct gpio_chip *chip = &hw->chip; 760 int ret; 761 762 chip->label = PINCTRL_PINCTRL_DEV; 763 chip->parent = hw->dev; 764 chip->request = gpiochip_generic_request; 765 chip->free = gpiochip_generic_free; 766 chip->get_direction = mtk_gpio_get_direction; 767 chip->direction_input = mtk_gpio_direction_input; 768 chip->direction_output = mtk_gpio_direction_output; 769 chip->get = mtk_gpio_get; 770 chip->set = mtk_gpio_set; 771 chip->to_irq = mtk_gpio_to_irq, 772 chip->set_config = mtk_gpio_set_config, 773 chip->base = -1; 774 chip->ngpio = hw->soc->npins; 775 chip->of_node = np; 776 chip->of_gpio_n_cells = 2; 777 778 ret = gpiochip_add_data(chip, hw); 779 if (ret < 0) 780 return ret; 781 782 return 0; 783 } 784 785 static int mtk_pctrl_build_state(struct platform_device *pdev) 786 { 787 struct mtk_pinctrl *hw = platform_get_drvdata(pdev); 788 int i; 789 790 /* Allocate groups */ 791 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps, 792 sizeof(*hw->groups), GFP_KERNEL); 793 if (!hw->groups) 794 return -ENOMEM; 795 796 /* We assume that one pin is one group, use pin name as group name. */ 797 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps, 798 sizeof(*hw->grp_names), GFP_KERNEL); 799 if (!hw->grp_names) 800 return -ENOMEM; 801 802 for (i = 0; i < hw->soc->npins; i++) { 803 const struct mtk_pin_desc *pin = hw->soc->pins + i; 804 struct mtk_pinctrl_group *group = hw->groups + i; 805 806 group->name = pin->name; 807 group->pin = pin->number; 808 809 hw->grp_names[i] = pin->name; 810 } 811 812 return 0; 813 } 814 815 int mtk_paris_pinctrl_probe(struct platform_device *pdev, 816 const struct mtk_pin_soc *soc) 817 { 818 struct pinctrl_pin_desc *pins; 819 struct mtk_pinctrl *hw; 820 struct resource *res; 821 int err, i; 822 823 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); 824 if (!hw) 825 return -ENOMEM; 826 827 platform_set_drvdata(pdev, hw); 828 hw->soc = soc; 829 hw->dev = &pdev->dev; 830 831 if (!hw->soc->nbase_names) { 832 dev_err(&pdev->dev, 833 "SoC should be assigned at least one register base\n"); 834 return -EINVAL; 835 } 836 837 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, 838 sizeof(*hw->base), GFP_KERNEL); 839 if (!hw->base) 840 return -ENOMEM; 841 842 for (i = 0; i < hw->soc->nbase_names; i++) { 843 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 844 hw->soc->base_names[i]); 845 if (!res) { 846 dev_err(&pdev->dev, "missing IO resource\n"); 847 return -ENXIO; 848 } 849 850 hw->base[i] = devm_ioremap_resource(&pdev->dev, res); 851 if (IS_ERR(hw->base[i])) 852 return PTR_ERR(hw->base[i]); 853 } 854 855 hw->nbase = hw->soc->nbase_names; 856 857 err = mtk_pctrl_build_state(pdev); 858 if (err) { 859 dev_err(&pdev->dev, "build state failed: %d\n", err); 860 return -EINVAL; 861 } 862 863 /* Copy from internal struct mtk_pin_desc to register to the core */ 864 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), 865 GFP_KERNEL); 866 if (!pins) 867 return -ENOMEM; 868 869 for (i = 0; i < hw->soc->npins; i++) { 870 pins[i].number = hw->soc->pins[i].number; 871 pins[i].name = hw->soc->pins[i].name; 872 } 873 874 /* Setup pins descriptions per SoC types */ 875 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins; 876 mtk_desc.npins = hw->soc->npins; 877 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); 878 mtk_desc.custom_params = mtk_custom_bindings; 879 #ifdef CONFIG_DEBUG_FS 880 mtk_desc.custom_conf_items = mtk_conf_items; 881 #endif 882 883 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw, 884 &hw->pctrl); 885 if (err) 886 return err; 887 888 err = pinctrl_enable(hw->pctrl); 889 if (err) 890 return err; 891 892 err = mtk_build_eint(hw, pdev); 893 if (err) 894 dev_warn(&pdev->dev, 895 "Failed to add EINT, but pinctrl still can work\n"); 896 897 /* Build gpiochip should be after pinctrl_enable is done */ 898 err = mtk_build_gpiochip(hw, pdev->dev.of_node); 899 if (err) { 900 dev_err(&pdev->dev, "Failed to add gpio_chip\n"); 901 return err; 902 } 903 904 platform_set_drvdata(pdev, hw); 905 906 return 0; 907 } 908