1 /* 2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/io.h> 17 #include <linux/gpio.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include <linux/bitops.h> 32 #include <linux/regmap.h> 33 #include <linux/mfd/syscon.h> 34 #include <linux/delay.h> 35 #include <linux/interrupt.h> 36 #include <linux/pm.h> 37 #include <dt-bindings/pinctrl/mt65xx.h> 38 39 #include "../core.h" 40 #include "../pinconf.h" 41 #include "../pinctrl-utils.h" 42 #include "pinctrl-mtk-common.h" 43 44 #define MAX_GPIO_MODE_PER_REG 5 45 #define GPIO_MODE_BITS 3 46 47 static const char * const mtk_gpio_functions[] = { 48 "func0", "func1", "func2", "func3", 49 "func4", "func5", "func6", "func7", 50 }; 51 52 /* 53 * There are two base address for pull related configuration 54 * in mt8135, and different GPIO pins use different base address. 55 * When pin number greater than type1_start and less than type1_end, 56 * should use the second base address. 57 */ 58 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, 59 unsigned long pin) 60 { 61 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) 62 return pctl->regmap2; 63 return pctl->regmap1; 64 } 65 66 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) 67 { 68 /* Different SoC has different mask and port shift. */ 69 return ((pin >> 4) & pctl->devdata->port_mask) 70 << pctl->devdata->port_shf; 71 } 72 73 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 74 struct pinctrl_gpio_range *range, unsigned offset, 75 bool input) 76 { 77 unsigned int reg_addr; 78 unsigned int bit; 79 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 80 81 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 82 bit = BIT(offset & 0xf); 83 84 if (input) 85 /* Different SoC has different alignment offset. */ 86 reg_addr = CLR_ADDR(reg_addr, pctl); 87 else 88 reg_addr = SET_ADDR(reg_addr, pctl); 89 90 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 91 return 0; 92 } 93 94 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 95 { 96 unsigned int reg_addr; 97 unsigned int bit; 98 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 99 100 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; 101 bit = BIT(offset & 0xf); 102 103 if (value) 104 reg_addr = SET_ADDR(reg_addr, pctl); 105 else 106 reg_addr = CLR_ADDR(reg_addr, pctl); 107 108 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 109 } 110 111 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 112 int value, enum pin_config_param arg) 113 { 114 unsigned int reg_addr, offset; 115 unsigned int bit; 116 117 /** 118 * Due to some soc are not support ies/smt config, add this special 119 * control to handle it. 120 */ 121 if (!pctl->devdata->spec_ies_smt_set && 122 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && 123 arg == PIN_CONFIG_INPUT_ENABLE) 124 return -EINVAL; 125 126 if (!pctl->devdata->spec_ies_smt_set && 127 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && 128 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 129 return -EINVAL; 130 131 /* 132 * Due to some pins are irregular, their input enable and smt 133 * control register are discontinuous, so we need this special handle. 134 */ 135 if (pctl->devdata->spec_ies_smt_set) { 136 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 137 pin, pctl->devdata->port_align, value, arg); 138 } 139 140 bit = BIT(pin & 0xf); 141 142 if (arg == PIN_CONFIG_INPUT_ENABLE) 143 offset = pctl->devdata->ies_offset; 144 else 145 offset = pctl->devdata->smt_offset; 146 147 if (value) 148 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 149 else 150 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 151 152 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 153 return 0; 154 } 155 156 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 157 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 158 unsigned int pin, unsigned char align, int value) 159 { 160 unsigned int i, reg_addr, bit; 161 162 for (i = 0; i < info_num; i++) { 163 if (pin >= ies_smt_infos[i].start && 164 pin <= ies_smt_infos[i].end) { 165 break; 166 } 167 } 168 169 if (i == info_num) 170 return -EINVAL; 171 172 if (value) 173 reg_addr = ies_smt_infos[i].offset + align; 174 else 175 reg_addr = ies_smt_infos[i].offset + (align << 1); 176 177 bit = BIT(ies_smt_infos[i].bit); 178 regmap_write(regmap, reg_addr, bit); 179 return 0; 180 } 181 182 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 183 struct mtk_pinctrl *pctl, unsigned long pin) { 184 int i; 185 186 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { 187 const struct mtk_pin_drv_grp *pin_drv = 188 pctl->devdata->pin_drv_grp + i; 189 if (pin == pin_drv->pin) 190 return pin_drv; 191 } 192 193 return NULL; 194 } 195 196 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, 197 unsigned int pin, unsigned char driving) 198 { 199 const struct mtk_pin_drv_grp *pin_drv; 200 unsigned int val; 201 unsigned int bits, mask, shift; 202 const struct mtk_drv_group_desc *drv_grp; 203 204 if (pin >= pctl->devdata->npins) 205 return -EINVAL; 206 207 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); 208 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) 209 return -EINVAL; 210 211 drv_grp = pctl->devdata->grp_desc + pin_drv->grp; 212 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv 213 && !(driving % drv_grp->step)) { 214 val = driving / drv_grp->step - 1; 215 bits = drv_grp->high_bit - drv_grp->low_bit + 1; 216 mask = BIT(bits) - 1; 217 shift = pin_drv->bit + drv_grp->low_bit; 218 mask <<= shift; 219 val <<= shift; 220 return regmap_update_bits(mtk_get_regmap(pctl, pin), 221 pin_drv->offset, mask, val); 222 } 223 224 return -EINVAL; 225 } 226 227 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 228 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, 229 unsigned int info_num, unsigned int pin, 230 unsigned char align, bool isup, unsigned int r1r0) 231 { 232 unsigned int i; 233 unsigned int reg_pupd, reg_set, reg_rst; 234 unsigned int bit_pupd, bit_r0, bit_r1; 235 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; 236 bool find = false; 237 238 for (i = 0; i < info_num; i++) { 239 if (pin == pupd_infos[i].pin) { 240 find = true; 241 break; 242 } 243 } 244 245 if (!find) 246 return -EINVAL; 247 248 spec_pupd_pin = pupd_infos + i; 249 reg_set = spec_pupd_pin->offset + align; 250 reg_rst = spec_pupd_pin->offset + (align << 1); 251 252 if (isup) 253 reg_pupd = reg_rst; 254 else 255 reg_pupd = reg_set; 256 257 bit_pupd = BIT(spec_pupd_pin->pupd_bit); 258 regmap_write(regmap, reg_pupd, bit_pupd); 259 260 bit_r0 = BIT(spec_pupd_pin->r0_bit); 261 bit_r1 = BIT(spec_pupd_pin->r1_bit); 262 263 switch (r1r0) { 264 case MTK_PUPD_SET_R1R0_00: 265 regmap_write(regmap, reg_rst, bit_r0); 266 regmap_write(regmap, reg_rst, bit_r1); 267 break; 268 case MTK_PUPD_SET_R1R0_01: 269 regmap_write(regmap, reg_set, bit_r0); 270 regmap_write(regmap, reg_rst, bit_r1); 271 break; 272 case MTK_PUPD_SET_R1R0_10: 273 regmap_write(regmap, reg_rst, bit_r0); 274 regmap_write(regmap, reg_set, bit_r1); 275 break; 276 case MTK_PUPD_SET_R1R0_11: 277 regmap_write(regmap, reg_set, bit_r0); 278 regmap_write(regmap, reg_set, bit_r1); 279 break; 280 default: 281 return -EINVAL; 282 } 283 284 return 0; 285 } 286 287 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 288 unsigned int pin, bool enable, bool isup, unsigned int arg) 289 { 290 unsigned int bit; 291 unsigned int reg_pullen, reg_pullsel; 292 int ret; 293 294 /* Some pins' pull setting are very different, 295 * they have separate pull up/down bit, R0 and R1 296 * resistor bit, so we need this special handle. 297 */ 298 if (pctl->devdata->spec_pull_set) { 299 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), 300 pin, pctl->devdata->port_align, isup, arg); 301 if (!ret) 302 return 0; 303 } 304 305 /* For generic pull config, default arg value should be 0 or 1. */ 306 if (arg != 0 && arg != 1) { 307 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", 308 arg, pin); 309 return -EINVAL; 310 } 311 312 bit = BIT(pin & 0xf); 313 if (enable) 314 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + 315 pctl->devdata->pullen_offset, pctl); 316 else 317 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + 318 pctl->devdata->pullen_offset, pctl); 319 320 if (isup) 321 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + 322 pctl->devdata->pullsel_offset, pctl); 323 else 324 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + 325 pctl->devdata->pullsel_offset, pctl); 326 327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); 328 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); 329 return 0; 330 } 331 332 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, 333 unsigned int pin, enum pin_config_param param, 334 enum pin_config_param arg) 335 { 336 int ret = 0; 337 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 338 339 switch (param) { 340 case PIN_CONFIG_BIAS_DISABLE: 341 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 342 break; 343 case PIN_CONFIG_BIAS_PULL_UP: 344 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 345 break; 346 case PIN_CONFIG_BIAS_PULL_DOWN: 347 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 348 break; 349 case PIN_CONFIG_INPUT_ENABLE: 350 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 351 break; 352 case PIN_CONFIG_OUTPUT: 353 mtk_gpio_set(pctl->chip, pin, arg); 354 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 355 break; 356 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 358 break; 359 case PIN_CONFIG_DRIVE_STRENGTH: 360 ret = mtk_pconf_set_driving(pctl, pin, arg); 361 break; 362 default: 363 ret = -EINVAL; 364 } 365 366 return ret; 367 } 368 369 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 370 unsigned group, 371 unsigned long *config) 372 { 373 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 374 375 *config = pctl->groups[group].config; 376 377 return 0; 378 } 379 380 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 381 unsigned long *configs, unsigned num_configs) 382 { 383 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 384 struct mtk_pinctrl_group *g = &pctl->groups[group]; 385 int i, ret; 386 387 for (i = 0; i < num_configs; i++) { 388 ret = mtk_pconf_parse_conf(pctldev, g->pin, 389 pinconf_to_config_param(configs[i]), 390 pinconf_to_config_argument(configs[i])); 391 if (ret < 0) 392 return ret; 393 394 g->config = configs[i]; 395 } 396 397 return 0; 398 } 399 400 static const struct pinconf_ops mtk_pconf_ops = { 401 .pin_config_group_get = mtk_pconf_group_get, 402 .pin_config_group_set = mtk_pconf_group_set, 403 }; 404 405 static struct mtk_pinctrl_group * 406 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) 407 { 408 int i; 409 410 for (i = 0; i < pctl->ngroups; i++) { 411 struct mtk_pinctrl_group *grp = pctl->groups + i; 412 413 if (grp->pin == pin) 414 return grp; 415 } 416 417 return NULL; 418 } 419 420 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( 421 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) 422 { 423 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; 424 const struct mtk_desc_function *func = pin->functions; 425 426 while (func && func->name) { 427 if (func->muxval == fnum) 428 return func; 429 func++; 430 } 431 432 return NULL; 433 } 434 435 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, 436 u32 pin_num, u32 fnum) 437 { 438 int i; 439 440 for (i = 0; i < pctl->devdata->npins; i++) { 441 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 442 443 if (pin->pin.number == pin_num) { 444 const struct mtk_desc_function *func = 445 pin->functions; 446 447 while (func && func->name) { 448 if (func->muxval == fnum) 449 return true; 450 func++; 451 } 452 453 break; 454 } 455 } 456 457 return false; 458 } 459 460 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 461 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, 462 struct pinctrl_map **map, unsigned *reserved_maps, 463 unsigned *num_maps) 464 { 465 bool ret; 466 467 if (*num_maps == *reserved_maps) 468 return -ENOSPC; 469 470 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 471 (*map)[*num_maps].data.mux.group = grp->name; 472 473 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 474 if (!ret) { 475 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 476 fnum, pin); 477 return -EINVAL; 478 } 479 480 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 481 (*num_maps)++; 482 483 return 0; 484 } 485 486 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 487 struct device_node *node, 488 struct pinctrl_map **map, 489 unsigned *reserved_maps, 490 unsigned *num_maps) 491 { 492 struct property *pins; 493 u32 pinfunc, pin, func; 494 int num_pins, num_funcs, maps_per_pin; 495 unsigned long *configs; 496 unsigned int num_configs; 497 bool has_config = 0; 498 int i, err; 499 unsigned reserve = 0; 500 struct mtk_pinctrl_group *grp; 501 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 502 503 pins = of_find_property(node, "pinmux", NULL); 504 if (!pins) { 505 dev_err(pctl->dev, "missing pins property in node %s .\n", 506 node->name); 507 return -EINVAL; 508 } 509 510 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 511 &num_configs); 512 if (num_configs) 513 has_config = 1; 514 515 num_pins = pins->length / sizeof(u32); 516 num_funcs = num_pins; 517 maps_per_pin = 0; 518 if (num_funcs) 519 maps_per_pin++; 520 if (has_config && num_pins >= 1) 521 maps_per_pin++; 522 523 if (!num_pins || !maps_per_pin) 524 return -EINVAL; 525 526 reserve = num_pins * maps_per_pin; 527 528 err = pinctrl_utils_reserve_map(pctldev, map, 529 reserved_maps, num_maps, reserve); 530 if (err < 0) 531 goto fail; 532 533 for (i = 0; i < num_pins; i++) { 534 err = of_property_read_u32_index(node, "pinmux", 535 i, &pinfunc); 536 if (err) 537 goto fail; 538 539 pin = MTK_GET_PIN_NO(pinfunc); 540 func = MTK_GET_PIN_FUNC(pinfunc); 541 542 if (pin >= pctl->devdata->npins || 543 func >= ARRAY_SIZE(mtk_gpio_functions)) { 544 dev_err(pctl->dev, "invalid pins value.\n"); 545 err = -EINVAL; 546 goto fail; 547 } 548 549 grp = mtk_pctrl_find_group_by_pin(pctl, pin); 550 if (!grp) { 551 dev_err(pctl->dev, "unable to match pin %d to group\n", 552 pin); 553 return -EINVAL; 554 } 555 556 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 557 reserved_maps, num_maps); 558 if (err < 0) 559 goto fail; 560 561 if (has_config) { 562 err = pinctrl_utils_add_map_configs(pctldev, map, 563 reserved_maps, num_maps, grp->name, 564 configs, num_configs, 565 PIN_MAP_TYPE_CONFIGS_GROUP); 566 if (err < 0) 567 goto fail; 568 } 569 } 570 571 return 0; 572 573 fail: 574 return err; 575 } 576 577 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 578 struct device_node *np_config, 579 struct pinctrl_map **map, unsigned *num_maps) 580 { 581 struct device_node *np; 582 unsigned reserved_maps; 583 int ret; 584 585 *map = NULL; 586 *num_maps = 0; 587 reserved_maps = 0; 588 589 for_each_child_of_node(np_config, np) { 590 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 591 &reserved_maps, num_maps); 592 if (ret < 0) { 593 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 594 return ret; 595 } 596 } 597 598 return 0; 599 } 600 601 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 602 { 603 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 604 605 return pctl->ngroups; 606 } 607 608 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 609 unsigned group) 610 { 611 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 612 613 return pctl->groups[group].name; 614 } 615 616 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 617 unsigned group, 618 const unsigned **pins, 619 unsigned *num_pins) 620 { 621 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 622 623 *pins = (unsigned *)&pctl->groups[group].pin; 624 *num_pins = 1; 625 626 return 0; 627 } 628 629 static const struct pinctrl_ops mtk_pctrl_ops = { 630 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 631 .dt_free_map = pinctrl_utils_dt_free_map, 632 .get_groups_count = mtk_pctrl_get_groups_count, 633 .get_group_name = mtk_pctrl_get_group_name, 634 .get_group_pins = mtk_pctrl_get_group_pins, 635 }; 636 637 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 638 { 639 return ARRAY_SIZE(mtk_gpio_functions); 640 } 641 642 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 643 unsigned selector) 644 { 645 return mtk_gpio_functions[selector]; 646 } 647 648 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 649 unsigned function, 650 const char * const **groups, 651 unsigned * const num_groups) 652 { 653 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 654 655 *groups = pctl->grp_names; 656 *num_groups = pctl->ngroups; 657 658 return 0; 659 } 660 661 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, 662 unsigned long pin, unsigned long mode) 663 { 664 unsigned int reg_addr; 665 unsigned char bit; 666 unsigned int val; 667 unsigned int mask = (1L << GPIO_MODE_BITS) - 1; 668 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 669 670 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) 671 + pctl->devdata->pinmux_offset; 672 673 bit = pin % MAX_GPIO_MODE_PER_REG; 674 mask <<= (GPIO_MODE_BITS * bit); 675 val = (mode << (GPIO_MODE_BITS * bit)); 676 return regmap_update_bits(mtk_get_regmap(pctl, pin), 677 reg_addr, mask, val); 678 } 679 680 static const struct mtk_desc_pin * 681 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) 682 { 683 int i; 684 const struct mtk_desc_pin *pin; 685 686 for (i = 0; i < pctl->devdata->npins; i++) { 687 pin = pctl->devdata->pins + i; 688 if (pin->eint.eintnum == eint_num) 689 return pin; 690 } 691 692 return NULL; 693 } 694 695 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 696 unsigned function, 697 unsigned group) 698 { 699 bool ret; 700 const struct mtk_desc_function *desc; 701 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 702 struct mtk_pinctrl_group *g = pctl->groups + group; 703 704 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 705 if (!ret) { 706 dev_err(pctl->dev, "invalid function %d on group %d .\n", 707 function, group); 708 return -EINVAL; 709 } 710 711 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); 712 if (!desc) 713 return -EINVAL; 714 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); 715 return 0; 716 } 717 718 static const struct pinmux_ops mtk_pmx_ops = { 719 .get_functions_count = mtk_pmx_get_funcs_cnt, 720 .get_function_name = mtk_pmx_get_func_name, 721 .get_function_groups = mtk_pmx_get_func_groups, 722 .set_mux = mtk_pmx_set_mux, 723 .gpio_set_direction = mtk_pmx_gpio_set_direction, 724 }; 725 726 static int mtk_gpio_direction_input(struct gpio_chip *chip, 727 unsigned offset) 728 { 729 return pinctrl_gpio_direction_input(chip->base + offset); 730 } 731 732 static int mtk_gpio_direction_output(struct gpio_chip *chip, 733 unsigned offset, int value) 734 { 735 mtk_gpio_set(chip, offset, value); 736 return pinctrl_gpio_direction_output(chip->base + offset); 737 } 738 739 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 740 { 741 unsigned int reg_addr; 742 unsigned int bit; 743 unsigned int read_val = 0; 744 745 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 746 747 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 748 bit = BIT(offset & 0xf); 749 regmap_read(pctl->regmap1, reg_addr, &read_val); 750 return !(read_val & bit); 751 } 752 753 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) 754 { 755 unsigned int reg_addr; 756 unsigned int bit; 757 unsigned int read_val = 0; 758 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 759 760 reg_addr = mtk_get_port(pctl, offset) + 761 pctl->devdata->din_offset; 762 763 bit = BIT(offset & 0xf); 764 regmap_read(pctl->regmap1, reg_addr, &read_val); 765 return !!(read_val & bit); 766 } 767 768 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 769 { 770 const struct mtk_desc_pin *pin; 771 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 772 int irq; 773 774 pin = pctl->devdata->pins + offset; 775 if (pin->eint.eintnum == NO_EINT_SUPPORT) 776 return -EINVAL; 777 778 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); 779 if (!irq) 780 return -EINVAL; 781 782 return irq; 783 } 784 785 static int mtk_pinctrl_irq_request_resources(struct irq_data *d) 786 { 787 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 788 const struct mtk_desc_pin *pin; 789 int ret; 790 791 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 792 793 if (!pin) { 794 dev_err(pctl->dev, "Can not find pin\n"); 795 return -EINVAL; 796 } 797 798 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); 799 if (ret) { 800 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 801 irqd_to_hwirq(d)); 802 return ret; 803 } 804 805 /* set mux to INT mode */ 806 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); 807 808 return 0; 809 } 810 811 static void mtk_pinctrl_irq_release_resources(struct irq_data *d) 812 { 813 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 814 const struct mtk_desc_pin *pin; 815 816 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 817 818 if (!pin) { 819 dev_err(pctl->dev, "Can not find pin\n"); 820 return; 821 } 822 823 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); 824 } 825 826 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, 827 unsigned int eint_num, unsigned int offset) 828 { 829 unsigned int eint_base = 0; 830 void __iomem *reg; 831 832 if (eint_num >= pctl->devdata->ap_num) 833 eint_base = pctl->devdata->ap_num; 834 835 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; 836 837 return reg; 838 } 839 840 /* 841 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not 842 * @eint_num: the EINT number to setmtk_pinctrl 843 */ 844 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, 845 unsigned int eint_num) 846 { 847 unsigned int sens; 848 unsigned int bit = BIT(eint_num % 32); 849 const struct mtk_eint_offsets *eint_offsets = 850 &pctl->devdata->eint_offsets; 851 852 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 853 eint_offsets->sens); 854 855 if (readl(reg) & bit) 856 sens = MT_LEVEL_SENSITIVE; 857 else 858 sens = MT_EDGE_SENSITIVE; 859 860 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) 861 return 1; 862 else 863 return 0; 864 } 865 866 /* 867 * mtk_eint_get_mask: To get the eint mask 868 * @eint_num: the EINT number to get 869 */ 870 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, 871 unsigned int eint_num) 872 { 873 unsigned int bit = BIT(eint_num % 32); 874 const struct mtk_eint_offsets *eint_offsets = 875 &pctl->devdata->eint_offsets; 876 877 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 878 eint_offsets->mask); 879 880 return !!(readl(reg) & bit); 881 } 882 883 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) 884 { 885 int start_level, curr_level; 886 unsigned int reg_offset; 887 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); 888 u32 mask = BIT(hwirq & 0x1f); 889 u32 port = (hwirq >> 5) & eint_offsets->port_mask; 890 void __iomem *reg = pctl->eint_reg_base + (port << 2); 891 const struct mtk_desc_pin *pin; 892 893 pin = mtk_find_pin_by_eint_num(pctl, hwirq); 894 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 895 do { 896 start_level = curr_level; 897 if (start_level) 898 reg_offset = eint_offsets->pol_clr; 899 else 900 reg_offset = eint_offsets->pol_set; 901 writel(mask, reg + reg_offset); 902 903 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 904 } while (start_level != curr_level); 905 906 return start_level; 907 } 908 909 static void mtk_eint_mask(struct irq_data *d) 910 { 911 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 912 const struct mtk_eint_offsets *eint_offsets = 913 &pctl->devdata->eint_offsets; 914 u32 mask = BIT(d->hwirq & 0x1f); 915 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 916 eint_offsets->mask_set); 917 918 writel(mask, reg); 919 } 920 921 static void mtk_eint_unmask(struct irq_data *d) 922 { 923 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 924 const struct mtk_eint_offsets *eint_offsets = 925 &pctl->devdata->eint_offsets; 926 u32 mask = BIT(d->hwirq & 0x1f); 927 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 928 eint_offsets->mask_clr); 929 930 writel(mask, reg); 931 932 if (pctl->eint_dual_edges[d->hwirq]) 933 mtk_eint_flip_edge(pctl, d->hwirq); 934 } 935 936 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, 937 unsigned debounce) 938 { 939 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 940 int eint_num, virq, eint_offset; 941 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; 942 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256}; 943 const struct mtk_desc_pin *pin; 944 struct irq_data *d; 945 946 pin = pctl->devdata->pins + offset; 947 if (pin->eint.eintnum == NO_EINT_SUPPORT) 948 return -EINVAL; 949 950 eint_num = pin->eint.eintnum; 951 virq = irq_find_mapping(pctl->domain, eint_num); 952 eint_offset = (eint_num % 4) * 8; 953 d = irq_get_irq_data(virq); 954 955 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; 956 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; 957 if (!mtk_eint_can_en_debounce(pctl, eint_num)) 958 return -ENOSYS; 959 960 dbnc = ARRAY_SIZE(dbnc_arr); 961 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) { 962 if (debounce <= dbnc_arr[i]) { 963 dbnc = i; 964 break; 965 } 966 } 967 968 if (!mtk_eint_get_mask(pctl, eint_num)) { 969 mtk_eint_mask(d); 970 unmask = 1; 971 } else { 972 unmask = 0; 973 } 974 975 clr_bit = 0xff << eint_offset; 976 writel(clr_bit, pctl->eint_reg_base + clr_offset); 977 978 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << 979 eint_offset; 980 rst = EINT_DBNC_RST_BIT << eint_offset; 981 writel(rst | bit, pctl->eint_reg_base + set_offset); 982 983 /* Delay a while (more than 2T) to wait for hw debounce counter reset 984 work correctly */ 985 udelay(1); 986 if (unmask == 1) 987 mtk_eint_unmask(d); 988 989 return 0; 990 } 991 992 static struct gpio_chip mtk_gpio_chip = { 993 .owner = THIS_MODULE, 994 .request = gpiochip_generic_request, 995 .free = gpiochip_generic_free, 996 .get_direction = mtk_gpio_get_direction, 997 .direction_input = mtk_gpio_direction_input, 998 .direction_output = mtk_gpio_direction_output, 999 .get = mtk_gpio_get, 1000 .set = mtk_gpio_set, 1001 .to_irq = mtk_gpio_to_irq, 1002 .set_debounce = mtk_gpio_set_debounce, 1003 .of_gpio_n_cells = 2, 1004 }; 1005 1006 static int mtk_eint_set_type(struct irq_data *d, 1007 unsigned int type) 1008 { 1009 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1010 const struct mtk_eint_offsets *eint_offsets = 1011 &pctl->devdata->eint_offsets; 1012 u32 mask = BIT(d->hwirq & 0x1f); 1013 void __iomem *reg; 1014 1015 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || 1016 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { 1017 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", 1018 d->irq, d->hwirq, type); 1019 return -EINVAL; 1020 } 1021 1022 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1023 pctl->eint_dual_edges[d->hwirq] = 1; 1024 else 1025 pctl->eint_dual_edges[d->hwirq] = 0; 1026 1027 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { 1028 reg = mtk_eint_get_offset(pctl, d->hwirq, 1029 eint_offsets->pol_clr); 1030 writel(mask, reg); 1031 } else { 1032 reg = mtk_eint_get_offset(pctl, d->hwirq, 1033 eint_offsets->pol_set); 1034 writel(mask, reg); 1035 } 1036 1037 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 1038 reg = mtk_eint_get_offset(pctl, d->hwirq, 1039 eint_offsets->sens_clr); 1040 writel(mask, reg); 1041 } else { 1042 reg = mtk_eint_get_offset(pctl, d->hwirq, 1043 eint_offsets->sens_set); 1044 writel(mask, reg); 1045 } 1046 1047 if (pctl->eint_dual_edges[d->hwirq]) 1048 mtk_eint_flip_edge(pctl, d->hwirq); 1049 1050 return 0; 1051 } 1052 1053 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) 1054 { 1055 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1056 int shift = d->hwirq & 0x1f; 1057 int reg = d->hwirq >> 5; 1058 1059 if (on) 1060 pctl->wake_mask[reg] |= BIT(shift); 1061 else 1062 pctl->wake_mask[reg] &= ~BIT(shift); 1063 1064 return 0; 1065 } 1066 1067 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip, 1068 void __iomem *eint_reg_base, u32 *buf) 1069 { 1070 int port; 1071 void __iomem *reg; 1072 1073 for (port = 0; port < chip->ports; port++) { 1074 reg = eint_reg_base + (port << 2); 1075 writel_relaxed(~buf[port], reg + chip->mask_set); 1076 writel_relaxed(buf[port], reg + chip->mask_clr); 1077 } 1078 } 1079 1080 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip, 1081 void __iomem *eint_reg_base, u32 *buf) 1082 { 1083 int port; 1084 void __iomem *reg; 1085 1086 for (port = 0; port < chip->ports; port++) { 1087 reg = eint_reg_base + chip->mask + (port << 2); 1088 buf[port] = ~readl_relaxed(reg); 1089 /* Mask is 0 when irq is enabled, and 1 when disabled. */ 1090 } 1091 } 1092 1093 static int mtk_eint_suspend(struct device *device) 1094 { 1095 void __iomem *reg; 1096 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 1097 const struct mtk_eint_offsets *eint_offsets = 1098 &pctl->devdata->eint_offsets; 1099 1100 reg = pctl->eint_reg_base; 1101 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask); 1102 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask); 1103 1104 return 0; 1105 } 1106 1107 static int mtk_eint_resume(struct device *device) 1108 { 1109 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 1110 const struct mtk_eint_offsets *eint_offsets = 1111 &pctl->devdata->eint_offsets; 1112 1113 mtk_eint_chip_write_mask(eint_offsets, 1114 pctl->eint_reg_base, pctl->cur_mask); 1115 1116 return 0; 1117 } 1118 1119 const struct dev_pm_ops mtk_eint_pm_ops = { 1120 .suspend = mtk_eint_suspend, 1121 .resume = mtk_eint_resume, 1122 }; 1123 1124 static void mtk_eint_ack(struct irq_data *d) 1125 { 1126 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1127 const struct mtk_eint_offsets *eint_offsets = 1128 &pctl->devdata->eint_offsets; 1129 u32 mask = BIT(d->hwirq & 0x1f); 1130 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 1131 eint_offsets->ack); 1132 1133 writel(mask, reg); 1134 } 1135 1136 static struct irq_chip mtk_pinctrl_irq_chip = { 1137 .name = "mt-eint", 1138 .irq_disable = mtk_eint_mask, 1139 .irq_mask = mtk_eint_mask, 1140 .irq_unmask = mtk_eint_unmask, 1141 .irq_ack = mtk_eint_ack, 1142 .irq_set_type = mtk_eint_set_type, 1143 .irq_set_wake = mtk_eint_irq_set_wake, 1144 .irq_request_resources = mtk_pinctrl_irq_request_resources, 1145 .irq_release_resources = mtk_pinctrl_irq_release_resources, 1146 }; 1147 1148 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) 1149 { 1150 const struct mtk_eint_offsets *eint_offsets = 1151 &pctl->devdata->eint_offsets; 1152 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; 1153 unsigned int i; 1154 1155 for (i = 0; i < pctl->devdata->ap_num; i += 32) { 1156 writel(0xffffffff, reg); 1157 reg += 4; 1158 } 1159 return 0; 1160 } 1161 1162 static inline void 1163 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) 1164 { 1165 unsigned int rst, ctrl_offset; 1166 unsigned int bit, dbnc; 1167 const struct mtk_eint_offsets *eint_offsets = 1168 &pctl->devdata->eint_offsets; 1169 1170 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; 1171 dbnc = readl(pctl->eint_reg_base + ctrl_offset); 1172 bit = EINT_DBNC_SET_EN << ((index % 4) * 8); 1173 if ((bit & dbnc) > 0) { 1174 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; 1175 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); 1176 writel(rst, pctl->eint_reg_base + ctrl_offset); 1177 } 1178 } 1179 1180 static void mtk_eint_irq_handler(struct irq_desc *desc) 1181 { 1182 struct irq_chip *chip = irq_desc_get_chip(desc); 1183 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc); 1184 unsigned int status, eint_num; 1185 int offset, index, virq; 1186 const struct mtk_eint_offsets *eint_offsets = 1187 &pctl->devdata->eint_offsets; 1188 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); 1189 int dual_edges, start_level, curr_level; 1190 const struct mtk_desc_pin *pin; 1191 1192 chained_irq_enter(chip, desc); 1193 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) { 1194 status = readl(reg); 1195 reg += 4; 1196 while (status) { 1197 offset = __ffs(status); 1198 index = eint_num + offset; 1199 virq = irq_find_mapping(pctl->domain, index); 1200 status &= ~BIT(offset); 1201 1202 dual_edges = pctl->eint_dual_edges[index]; 1203 if (dual_edges) { 1204 /* Clear soft-irq in case we raised it 1205 last time */ 1206 writel(BIT(offset), reg - eint_offsets->stat + 1207 eint_offsets->soft_clr); 1208 1209 pin = mtk_find_pin_by_eint_num(pctl, index); 1210 start_level = mtk_gpio_get(pctl->chip, 1211 pin->pin.number); 1212 } 1213 1214 generic_handle_irq(virq); 1215 1216 if (dual_edges) { 1217 curr_level = mtk_eint_flip_edge(pctl, index); 1218 1219 /* If level changed, we might lost one edge 1220 interrupt, raised it through soft-irq */ 1221 if (start_level != curr_level) 1222 writel(BIT(offset), reg - 1223 eint_offsets->stat + 1224 eint_offsets->soft_set); 1225 } 1226 1227 if (index < pctl->devdata->db_cnt) 1228 mtk_eint_debounce_process(pctl , index); 1229 } 1230 } 1231 chained_irq_exit(chip, desc); 1232 } 1233 1234 static int mtk_pctrl_build_state(struct platform_device *pdev) 1235 { 1236 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); 1237 int i; 1238 1239 pctl->ngroups = pctl->devdata->npins; 1240 1241 /* Allocate groups */ 1242 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1243 sizeof(*pctl->groups), GFP_KERNEL); 1244 if (!pctl->groups) 1245 return -ENOMEM; 1246 1247 /* We assume that one pin is one group, use pin name as group name. */ 1248 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1249 sizeof(*pctl->grp_names), GFP_KERNEL); 1250 if (!pctl->grp_names) 1251 return -ENOMEM; 1252 1253 for (i = 0; i < pctl->devdata->npins; i++) { 1254 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 1255 struct mtk_pinctrl_group *group = pctl->groups + i; 1256 1257 group->name = pin->pin.name; 1258 group->pin = pin->pin.number; 1259 1260 pctl->grp_names[i] = pin->pin.name; 1261 } 1262 1263 return 0; 1264 } 1265 1266 int mtk_pctrl_init(struct platform_device *pdev, 1267 const struct mtk_pinctrl_devdata *data, 1268 struct regmap *regmap) 1269 { 1270 struct pinctrl_pin_desc *pins; 1271 struct mtk_pinctrl *pctl; 1272 struct device_node *np = pdev->dev.of_node, *node; 1273 struct property *prop; 1274 struct resource *res; 1275 int i, ret, irq, ports_buf; 1276 1277 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1278 if (!pctl) 1279 return -ENOMEM; 1280 1281 platform_set_drvdata(pdev, pctl); 1282 1283 prop = of_find_property(np, "pins-are-numbered", NULL); 1284 if (!prop) { 1285 dev_err(&pdev->dev, "only support pins-are-numbered format\n"); 1286 return -EINVAL; 1287 } 1288 1289 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); 1290 if (node) { 1291 pctl->regmap1 = syscon_node_to_regmap(node); 1292 if (IS_ERR(pctl->regmap1)) 1293 return PTR_ERR(pctl->regmap1); 1294 } else if (regmap) { 1295 pctl->regmap1 = regmap; 1296 } else { 1297 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); 1298 return -EINVAL; 1299 } 1300 1301 /* Only 8135 has two base addr, other SoCs have only one. */ 1302 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); 1303 if (node) { 1304 pctl->regmap2 = syscon_node_to_regmap(node); 1305 if (IS_ERR(pctl->regmap2)) 1306 return PTR_ERR(pctl->regmap2); 1307 } 1308 1309 pctl->devdata = data; 1310 ret = mtk_pctrl_build_state(pdev); 1311 if (ret) { 1312 dev_err(&pdev->dev, "build state failed: %d\n", ret); 1313 return -EINVAL; 1314 } 1315 1316 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), 1317 GFP_KERNEL); 1318 if (!pins) 1319 return -ENOMEM; 1320 1321 for (i = 0; i < pctl->devdata->npins; i++) 1322 pins[i] = pctl->devdata->pins[i].pin; 1323 1324 pctl->pctl_desc.name = dev_name(&pdev->dev); 1325 pctl->pctl_desc.owner = THIS_MODULE; 1326 pctl->pctl_desc.pins = pins; 1327 pctl->pctl_desc.npins = pctl->devdata->npins; 1328 pctl->pctl_desc.confops = &mtk_pconf_ops; 1329 pctl->pctl_desc.pctlops = &mtk_pctrl_ops; 1330 pctl->pctl_desc.pmxops = &mtk_pmx_ops; 1331 pctl->dev = &pdev->dev; 1332 1333 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); 1334 if (IS_ERR(pctl->pctl_dev)) { 1335 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1336 return PTR_ERR(pctl->pctl_dev); 1337 } 1338 1339 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1340 if (!pctl->chip) { 1341 ret = -ENOMEM; 1342 goto pctrl_error; 1343 } 1344 1345 *pctl->chip = mtk_gpio_chip; 1346 pctl->chip->ngpio = pctl->devdata->npins; 1347 pctl->chip->label = dev_name(&pdev->dev); 1348 pctl->chip->dev = &pdev->dev; 1349 pctl->chip->base = -1; 1350 1351 ret = gpiochip_add(pctl->chip); 1352 if (ret) { 1353 ret = -EINVAL; 1354 goto pctrl_error; 1355 } 1356 1357 /* Register the GPIO to pin mappings. */ 1358 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1359 0, 0, pctl->devdata->npins); 1360 if (ret) { 1361 ret = -EINVAL; 1362 goto chip_error; 1363 } 1364 1365 if (!of_property_read_bool(np, "interrupt-controller")) 1366 return 0; 1367 1368 /* Get EINT register base from dts. */ 1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1370 if (!res) { 1371 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); 1372 ret = -EINVAL; 1373 goto chip_error; 1374 } 1375 1376 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); 1377 if (IS_ERR(pctl->eint_reg_base)) { 1378 ret = -EINVAL; 1379 goto chip_error; 1380 } 1381 1382 ports_buf = pctl->devdata->eint_offsets.ports; 1383 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf, 1384 sizeof(*pctl->wake_mask), GFP_KERNEL); 1385 if (!pctl->wake_mask) { 1386 ret = -ENOMEM; 1387 goto chip_error; 1388 } 1389 1390 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf, 1391 sizeof(*pctl->cur_mask), GFP_KERNEL); 1392 if (!pctl->cur_mask) { 1393 ret = -ENOMEM; 1394 goto chip_error; 1395 } 1396 1397 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, 1398 sizeof(int), GFP_KERNEL); 1399 if (!pctl->eint_dual_edges) { 1400 ret = -ENOMEM; 1401 goto chip_error; 1402 } 1403 1404 irq = irq_of_parse_and_map(np, 0); 1405 if (!irq) { 1406 dev_err(&pdev->dev, "couldn't parse and map irq\n"); 1407 ret = -EINVAL; 1408 goto chip_error; 1409 } 1410 1411 pctl->domain = irq_domain_add_linear(np, 1412 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); 1413 if (!pctl->domain) { 1414 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1415 ret = -ENOMEM; 1416 goto chip_error; 1417 } 1418 1419 mtk_eint_init(pctl); 1420 for (i = 0; i < pctl->devdata->ap_num; i++) { 1421 int virq = irq_create_mapping(pctl->domain, i); 1422 1423 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, 1424 handle_level_irq); 1425 irq_set_chip_data(virq, pctl); 1426 } 1427 1428 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); 1429 return 0; 1430 1431 chip_error: 1432 gpiochip_remove(pctl->chip); 1433 pctrl_error: 1434 pinctrl_unregister(pctl->pctl_dev); 1435 return ret; 1436 } 1437 1438 MODULE_LICENSE("GPL"); 1439 MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); 1440 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); 1441