1 /*
2  * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/io.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
31 #include <linux/regmap.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/pm.h>
36 #include <dt-bindings/pinctrl/mt65xx.h>
37 
38 #include "../core.h"
39 #include "../pinconf.h"
40 #include "../pinctrl-utils.h"
41 #include "pinctrl-mtk-common.h"
42 
43 #define MAX_GPIO_MODE_PER_REG 5
44 #define GPIO_MODE_BITS        3
45 #define GPIO_MODE_PREFIX "GPIO"
46 
47 static const char * const mtk_gpio_functions[] = {
48 	"func0", "func1", "func2", "func3",
49 	"func4", "func5", "func6", "func7",
50 	"func8", "func9", "func10", "func11",
51 	"func12", "func13", "func14", "func15",
52 };
53 
54 /*
55  * There are two base address for pull related configuration
56  * in mt8135, and different GPIO pins use different base address.
57  * When pin number greater than type1_start and less than type1_end,
58  * should use the second base address.
59  */
60 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
61 		unsigned long pin)
62 {
63 	if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
64 		return pctl->regmap2;
65 	return pctl->regmap1;
66 }
67 
68 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
69 {
70 	/* Different SoC has different mask and port shift. */
71 	return ((pin >> 4) & pctl->devdata->port_mask)
72 			<< pctl->devdata->port_shf;
73 }
74 
75 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
76 			struct pinctrl_gpio_range *range, unsigned offset,
77 			bool input)
78 {
79 	unsigned int reg_addr;
80 	unsigned int bit;
81 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
82 
83 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
84 	bit = BIT(offset & 0xf);
85 
86 	if (pctl->devdata->spec_dir_set)
87 		pctl->devdata->spec_dir_set(&reg_addr, offset);
88 
89 	if (input)
90 		/* Different SoC has different alignment offset. */
91 		reg_addr = CLR_ADDR(reg_addr, pctl);
92 	else
93 		reg_addr = SET_ADDR(reg_addr, pctl);
94 
95 	regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
96 	return 0;
97 }
98 
99 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100 {
101 	unsigned int reg_addr;
102 	unsigned int bit;
103 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
104 
105 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
106 	bit = BIT(offset & 0xf);
107 
108 	if (value)
109 		reg_addr = SET_ADDR(reg_addr, pctl);
110 	else
111 		reg_addr = CLR_ADDR(reg_addr, pctl);
112 
113 	regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
114 }
115 
116 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
117 		int value, enum pin_config_param arg)
118 {
119 	unsigned int reg_addr, offset;
120 	unsigned int bit;
121 
122 	/**
123 	 * Due to some soc are not support ies/smt config, add this special
124 	 * control to handle it.
125 	 */
126 	if (!pctl->devdata->spec_ies_smt_set &&
127 		pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
128 			arg == PIN_CONFIG_INPUT_ENABLE)
129 		return -EINVAL;
130 
131 	if (!pctl->devdata->spec_ies_smt_set &&
132 		pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
133 			arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
134 		return -EINVAL;
135 
136 	/*
137 	 * Due to some pins are irregular, their input enable and smt
138 	 * control register are discontinuous, so we need this special handle.
139 	 */
140 	if (pctl->devdata->spec_ies_smt_set) {
141 		return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
142 			pin, pctl->devdata->port_align, value, arg);
143 	}
144 
145 	bit = BIT(pin & 0xf);
146 
147 	if (arg == PIN_CONFIG_INPUT_ENABLE)
148 		offset = pctl->devdata->ies_offset;
149 	else
150 		offset = pctl->devdata->smt_offset;
151 
152 	if (value)
153 		reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
154 	else
155 		reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
156 
157 	regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
158 	return 0;
159 }
160 
161 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
162 		const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
163 		unsigned int pin, unsigned char align, int value)
164 {
165 	unsigned int i, reg_addr, bit;
166 
167 	for (i = 0; i < info_num; i++) {
168 		if (pin >= ies_smt_infos[i].start &&
169 				pin <= ies_smt_infos[i].end) {
170 			break;
171 		}
172 	}
173 
174 	if (i == info_num)
175 		return -EINVAL;
176 
177 	if (value)
178 		reg_addr = ies_smt_infos[i].offset + align;
179 	else
180 		reg_addr = ies_smt_infos[i].offset + (align << 1);
181 
182 	bit = BIT(ies_smt_infos[i].bit);
183 	regmap_write(regmap, reg_addr, bit);
184 	return 0;
185 }
186 
187 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
188 		struct mtk_pinctrl *pctl,  unsigned long pin) {
189 	int i;
190 
191 	for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
192 		const struct mtk_pin_drv_grp *pin_drv =
193 				pctl->devdata->pin_drv_grp + i;
194 		if (pin == pin_drv->pin)
195 			return pin_drv;
196 	}
197 
198 	return NULL;
199 }
200 
201 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
202 		unsigned int pin, unsigned char driving)
203 {
204 	const struct mtk_pin_drv_grp *pin_drv;
205 	unsigned int val;
206 	unsigned int bits, mask, shift;
207 	const struct mtk_drv_group_desc *drv_grp;
208 
209 	if (pin >= pctl->devdata->npins)
210 		return -EINVAL;
211 
212 	pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
213 	if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
214 		return -EINVAL;
215 
216 	drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
217 	if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
218 		&& !(driving % drv_grp->step)) {
219 		val = driving / drv_grp->step - 1;
220 		bits = drv_grp->high_bit - drv_grp->low_bit + 1;
221 		mask = BIT(bits) - 1;
222 		shift = pin_drv->bit + drv_grp->low_bit;
223 		mask <<= shift;
224 		val <<= shift;
225 		return regmap_update_bits(mtk_get_regmap(pctl, pin),
226 				pin_drv->offset, mask, val);
227 	}
228 
229 	return -EINVAL;
230 }
231 
232 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
233 		const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
234 		unsigned int info_num, unsigned int pin,
235 		unsigned char align, bool isup, unsigned int r1r0)
236 {
237 	unsigned int i;
238 	unsigned int reg_pupd, reg_set, reg_rst;
239 	unsigned int bit_pupd, bit_r0, bit_r1;
240 	const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
241 	bool find = false;
242 
243 	for (i = 0; i < info_num; i++) {
244 		if (pin == pupd_infos[i].pin) {
245 			find = true;
246 			break;
247 		}
248 	}
249 
250 	if (!find)
251 		return -EINVAL;
252 
253 	spec_pupd_pin = pupd_infos + i;
254 	reg_set = spec_pupd_pin->offset + align;
255 	reg_rst = spec_pupd_pin->offset + (align << 1);
256 
257 	if (isup)
258 		reg_pupd = reg_rst;
259 	else
260 		reg_pupd = reg_set;
261 
262 	bit_pupd = BIT(spec_pupd_pin->pupd_bit);
263 	regmap_write(regmap, reg_pupd, bit_pupd);
264 
265 	bit_r0 = BIT(spec_pupd_pin->r0_bit);
266 	bit_r1 = BIT(spec_pupd_pin->r1_bit);
267 
268 	switch (r1r0) {
269 	case MTK_PUPD_SET_R1R0_00:
270 		regmap_write(regmap, reg_rst, bit_r0);
271 		regmap_write(regmap, reg_rst, bit_r1);
272 		break;
273 	case MTK_PUPD_SET_R1R0_01:
274 		regmap_write(regmap, reg_set, bit_r0);
275 		regmap_write(regmap, reg_rst, bit_r1);
276 		break;
277 	case MTK_PUPD_SET_R1R0_10:
278 		regmap_write(regmap, reg_rst, bit_r0);
279 		regmap_write(regmap, reg_set, bit_r1);
280 		break;
281 	case MTK_PUPD_SET_R1R0_11:
282 		regmap_write(regmap, reg_set, bit_r0);
283 		regmap_write(regmap, reg_set, bit_r1);
284 		break;
285 	default:
286 		return -EINVAL;
287 	}
288 
289 	return 0;
290 }
291 
292 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
293 		unsigned int pin, bool enable, bool isup, unsigned int arg)
294 {
295 	unsigned int bit;
296 	unsigned int reg_pullen, reg_pullsel;
297 	int ret;
298 
299 	/* Some pins' pull setting are very different,
300 	 * they have separate pull up/down bit, R0 and R1
301 	 * resistor bit, so we need this special handle.
302 	 */
303 	if (pctl->devdata->spec_pull_set) {
304 		ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
305 			pin, pctl->devdata->port_align, isup, arg);
306 		if (!ret)
307 			return 0;
308 	}
309 
310 	/* For generic pull config, default arg value should be 0 or 1. */
311 	if (arg != 0 && arg != 1) {
312 		dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
313 			arg, pin);
314 		return -EINVAL;
315 	}
316 
317 	bit = BIT(pin & 0xf);
318 	if (enable)
319 		reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
320 			pctl->devdata->pullen_offset, pctl);
321 	else
322 		reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
323 			pctl->devdata->pullen_offset, pctl);
324 
325 	if (isup)
326 		reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
327 			pctl->devdata->pullsel_offset, pctl);
328 	else
329 		reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
330 			pctl->devdata->pullsel_offset, pctl);
331 
332 	regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
333 	regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
334 	return 0;
335 }
336 
337 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
338 		unsigned int pin, enum pin_config_param param,
339 		enum pin_config_param arg)
340 {
341 	int ret = 0;
342 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
343 
344 	switch (param) {
345 	case PIN_CONFIG_BIAS_DISABLE:
346 		ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
347 		break;
348 	case PIN_CONFIG_BIAS_PULL_UP:
349 		ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
350 		break;
351 	case PIN_CONFIG_BIAS_PULL_DOWN:
352 		ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
353 		break;
354 	case PIN_CONFIG_INPUT_ENABLE:
355 		mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
356 		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
357 		break;
358 	case PIN_CONFIG_OUTPUT:
359 		mtk_gpio_set(pctl->chip, pin, arg);
360 		ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
361 		break;
362 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
363 		mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
364 		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
365 		break;
366 	case PIN_CONFIG_DRIVE_STRENGTH:
367 		ret = mtk_pconf_set_driving(pctl, pin, arg);
368 		break;
369 	default:
370 		ret = -EINVAL;
371 	}
372 
373 	return ret;
374 }
375 
376 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
377 				 unsigned group,
378 				 unsigned long *config)
379 {
380 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
381 
382 	*config = pctl->groups[group].config;
383 
384 	return 0;
385 }
386 
387 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
388 				 unsigned long *configs, unsigned num_configs)
389 {
390 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
391 	struct mtk_pinctrl_group *g = &pctl->groups[group];
392 	int i, ret;
393 
394 	for (i = 0; i < num_configs; i++) {
395 		ret = mtk_pconf_parse_conf(pctldev, g->pin,
396 			pinconf_to_config_param(configs[i]),
397 			pinconf_to_config_argument(configs[i]));
398 		if (ret < 0)
399 			return ret;
400 
401 		g->config = configs[i];
402 	}
403 
404 	return 0;
405 }
406 
407 static const struct pinconf_ops mtk_pconf_ops = {
408 	.pin_config_group_get	= mtk_pconf_group_get,
409 	.pin_config_group_set	= mtk_pconf_group_set,
410 };
411 
412 static struct mtk_pinctrl_group *
413 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
414 {
415 	int i;
416 
417 	for (i = 0; i < pctl->ngroups; i++) {
418 		struct mtk_pinctrl_group *grp = pctl->groups + i;
419 
420 		if (grp->pin == pin)
421 			return grp;
422 	}
423 
424 	return NULL;
425 }
426 
427 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
428 		struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
429 {
430 	const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
431 	const struct mtk_desc_function *func = pin->functions;
432 
433 	while (func && func->name) {
434 		if (func->muxval == fnum)
435 			return func;
436 		func++;
437 	}
438 
439 	return NULL;
440 }
441 
442 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
443 		u32 pin_num, u32 fnum)
444 {
445 	int i;
446 
447 	for (i = 0; i < pctl->devdata->npins; i++) {
448 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
449 
450 		if (pin->pin.number == pin_num) {
451 			const struct mtk_desc_function *func =
452 					pin->functions;
453 
454 			while (func && func->name) {
455 				if (func->muxval == fnum)
456 					return true;
457 				func++;
458 			}
459 
460 			break;
461 		}
462 	}
463 
464 	return false;
465 }
466 
467 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
468 		u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
469 		struct pinctrl_map **map, unsigned *reserved_maps,
470 		unsigned *num_maps)
471 {
472 	bool ret;
473 
474 	if (*num_maps == *reserved_maps)
475 		return -ENOSPC;
476 
477 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
478 	(*map)[*num_maps].data.mux.group = grp->name;
479 
480 	ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
481 	if (!ret) {
482 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",
483 				fnum, pin);
484 		return -EINVAL;
485 	}
486 
487 	(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
488 	(*num_maps)++;
489 
490 	return 0;
491 }
492 
493 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
494 				      struct device_node *node,
495 				      struct pinctrl_map **map,
496 				      unsigned *reserved_maps,
497 				      unsigned *num_maps)
498 {
499 	struct property *pins;
500 	u32 pinfunc, pin, func;
501 	int num_pins, num_funcs, maps_per_pin;
502 	unsigned long *configs;
503 	unsigned int num_configs;
504 	bool has_config = 0;
505 	int i, err;
506 	unsigned reserve = 0;
507 	struct mtk_pinctrl_group *grp;
508 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
509 
510 	pins = of_find_property(node, "pinmux", NULL);
511 	if (!pins) {
512 		dev_err(pctl->dev, "missing pins property in node %s .\n",
513 				node->name);
514 		return -EINVAL;
515 	}
516 
517 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
518 		&num_configs);
519 	if (err)
520 		return err;
521 
522 	if (num_configs)
523 		has_config = 1;
524 
525 	num_pins = pins->length / sizeof(u32);
526 	num_funcs = num_pins;
527 	maps_per_pin = 0;
528 	if (num_funcs)
529 		maps_per_pin++;
530 	if (has_config && num_pins >= 1)
531 		maps_per_pin++;
532 
533 	if (!num_pins || !maps_per_pin) {
534 		err = -EINVAL;
535 		goto exit;
536 	}
537 
538 	reserve = num_pins * maps_per_pin;
539 
540 	err = pinctrl_utils_reserve_map(pctldev, map,
541 			reserved_maps, num_maps, reserve);
542 	if (err < 0)
543 		goto exit;
544 
545 	for (i = 0; i < num_pins; i++) {
546 		err = of_property_read_u32_index(node, "pinmux",
547 				i, &pinfunc);
548 		if (err)
549 			goto exit;
550 
551 		pin = MTK_GET_PIN_NO(pinfunc);
552 		func = MTK_GET_PIN_FUNC(pinfunc);
553 
554 		if (pin >= pctl->devdata->npins ||
555 				func >= ARRAY_SIZE(mtk_gpio_functions)) {
556 			dev_err(pctl->dev, "invalid pins value.\n");
557 			err = -EINVAL;
558 			goto exit;
559 		}
560 
561 		grp = mtk_pctrl_find_group_by_pin(pctl, pin);
562 		if (!grp) {
563 			dev_err(pctl->dev, "unable to match pin %d to group\n",
564 					pin);
565 			err = -EINVAL;
566 			goto exit;
567 		}
568 
569 		err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
570 				reserved_maps, num_maps);
571 		if (err < 0)
572 			goto exit;
573 
574 		if (has_config) {
575 			err = pinctrl_utils_add_map_configs(pctldev, map,
576 					reserved_maps, num_maps, grp->name,
577 					configs, num_configs,
578 					PIN_MAP_TYPE_CONFIGS_GROUP);
579 			if (err < 0)
580 				goto exit;
581 		}
582 	}
583 
584 	err = 0;
585 
586 exit:
587 	kfree(configs);
588 	return err;
589 }
590 
591 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
592 				 struct device_node *np_config,
593 				 struct pinctrl_map **map, unsigned *num_maps)
594 {
595 	struct device_node *np;
596 	unsigned reserved_maps;
597 	int ret;
598 
599 	*map = NULL;
600 	*num_maps = 0;
601 	reserved_maps = 0;
602 
603 	for_each_child_of_node(np_config, np) {
604 		ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
605 				&reserved_maps, num_maps);
606 		if (ret < 0) {
607 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
608 			of_node_put(np);
609 			return ret;
610 		}
611 	}
612 
613 	return 0;
614 }
615 
616 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
617 {
618 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
619 
620 	return pctl->ngroups;
621 }
622 
623 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
624 					      unsigned group)
625 {
626 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
627 
628 	return pctl->groups[group].name;
629 }
630 
631 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
632 				      unsigned group,
633 				      const unsigned **pins,
634 				      unsigned *num_pins)
635 {
636 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
637 
638 	*pins = (unsigned *)&pctl->groups[group].pin;
639 	*num_pins = 1;
640 
641 	return 0;
642 }
643 
644 static const struct pinctrl_ops mtk_pctrl_ops = {
645 	.dt_node_to_map		= mtk_pctrl_dt_node_to_map,
646 	.dt_free_map		= pinctrl_utils_free_map,
647 	.get_groups_count	= mtk_pctrl_get_groups_count,
648 	.get_group_name		= mtk_pctrl_get_group_name,
649 	.get_group_pins		= mtk_pctrl_get_group_pins,
650 };
651 
652 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
653 {
654 	return ARRAY_SIZE(mtk_gpio_functions);
655 }
656 
657 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
658 					   unsigned selector)
659 {
660 	return mtk_gpio_functions[selector];
661 }
662 
663 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
664 				     unsigned function,
665 				     const char * const **groups,
666 				     unsigned * const num_groups)
667 {
668 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
669 
670 	*groups = pctl->grp_names;
671 	*num_groups = pctl->ngroups;
672 
673 	return 0;
674 }
675 
676 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
677 		unsigned long pin, unsigned long mode)
678 {
679 	unsigned int reg_addr;
680 	unsigned char bit;
681 	unsigned int val;
682 	unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
683 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
684 
685 	if (pctl->devdata->spec_pinmux_set)
686 		pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
687 					pin, mode);
688 
689 	reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
690 			+ pctl->devdata->pinmux_offset;
691 
692 	mode &= mask;
693 	bit = pin % MAX_GPIO_MODE_PER_REG;
694 	mask <<= (GPIO_MODE_BITS * bit);
695 	val = (mode << (GPIO_MODE_BITS * bit));
696 	return regmap_update_bits(mtk_get_regmap(pctl, pin),
697 			reg_addr, mask, val);
698 }
699 
700 static const struct mtk_desc_pin *
701 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
702 {
703 	int i;
704 	const struct mtk_desc_pin *pin;
705 
706 	for (i = 0; i < pctl->devdata->npins; i++) {
707 		pin = pctl->devdata->pins + i;
708 		if (pin->eint.eintnum == eint_num)
709 			return pin;
710 	}
711 
712 	return NULL;
713 }
714 
715 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
716 			    unsigned function,
717 			    unsigned group)
718 {
719 	bool ret;
720 	const struct mtk_desc_function *desc;
721 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
722 	struct mtk_pinctrl_group *g = pctl->groups + group;
723 
724 	ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
725 	if (!ret) {
726 		dev_err(pctl->dev, "invalid function %d on group %d .\n",
727 				function, group);
728 		return -EINVAL;
729 	}
730 
731 	desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
732 	if (!desc)
733 		return -EINVAL;
734 	mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
735 	return 0;
736 }
737 
738 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
739 				unsigned offset)
740 {
741 	const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
742 	const struct mtk_desc_function *func = pin->functions;
743 
744 	while (func && func->name) {
745 		if (!strncmp(func->name, GPIO_MODE_PREFIX,
746 			sizeof(GPIO_MODE_PREFIX)-1))
747 			return func->muxval;
748 		func++;
749 	}
750 	return -EINVAL;
751 }
752 
753 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
754 				    struct pinctrl_gpio_range *range,
755 				    unsigned offset)
756 {
757 	int muxval;
758 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
759 
760 	muxval = mtk_pmx_find_gpio_mode(pctl, offset);
761 
762 	if (muxval < 0) {
763 		dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
764 		return -EINVAL;
765 	}
766 
767 	mtk_pmx_set_mode(pctldev, offset, muxval);
768 	mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
769 
770 	return 0;
771 }
772 
773 static const struct pinmux_ops mtk_pmx_ops = {
774 	.get_functions_count	= mtk_pmx_get_funcs_cnt,
775 	.get_function_name	= mtk_pmx_get_func_name,
776 	.get_function_groups	= mtk_pmx_get_func_groups,
777 	.set_mux		= mtk_pmx_set_mux,
778 	.gpio_set_direction	= mtk_pmx_gpio_set_direction,
779 	.gpio_request_enable	= mtk_pmx_gpio_request_enable,
780 };
781 
782 static int mtk_gpio_direction_input(struct gpio_chip *chip,
783 					unsigned offset)
784 {
785 	return pinctrl_gpio_direction_input(chip->base + offset);
786 }
787 
788 static int mtk_gpio_direction_output(struct gpio_chip *chip,
789 					unsigned offset, int value)
790 {
791 	mtk_gpio_set(chip, offset, value);
792 	return pinctrl_gpio_direction_output(chip->base + offset);
793 }
794 
795 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
796 {
797 	unsigned int reg_addr;
798 	unsigned int bit;
799 	unsigned int read_val = 0;
800 
801 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
802 
803 	reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
804 	bit = BIT(offset & 0xf);
805 
806 	if (pctl->devdata->spec_dir_set)
807 		pctl->devdata->spec_dir_set(&reg_addr, offset);
808 
809 	regmap_read(pctl->regmap1, reg_addr, &read_val);
810 	return !(read_val & bit);
811 }
812 
813 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
814 {
815 	unsigned int reg_addr;
816 	unsigned int bit;
817 	unsigned int read_val = 0;
818 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
819 
820 	reg_addr = mtk_get_port(pctl, offset) +
821 		pctl->devdata->din_offset;
822 
823 	bit = BIT(offset & 0xf);
824 	regmap_read(pctl->regmap1, reg_addr, &read_val);
825 	return !!(read_val & bit);
826 }
827 
828 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
829 {
830 	const struct mtk_desc_pin *pin;
831 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
832 	int irq;
833 
834 	pin = pctl->devdata->pins + offset;
835 	if (pin->eint.eintnum == NO_EINT_SUPPORT)
836 		return -EINVAL;
837 
838 	irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
839 	if (!irq)
840 		return -EINVAL;
841 
842 	return irq;
843 }
844 
845 static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
846 {
847 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
848 	const struct mtk_desc_pin *pin;
849 	int ret;
850 
851 	pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
852 
853 	if (!pin) {
854 		dev_err(pctl->dev, "Can not find pin\n");
855 		return -EINVAL;
856 	}
857 
858 	ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
859 	if (ret) {
860 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
861 			irqd_to_hwirq(d));
862 		return ret;
863 	}
864 
865 	/* set mux to INT mode */
866 	mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
867 	/* set gpio direction to input */
868 	mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
869 	/* set input-enable */
870 	mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
871 
872 	return 0;
873 }
874 
875 static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
876 {
877 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
878 	const struct mtk_desc_pin *pin;
879 
880 	pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
881 
882 	if (!pin) {
883 		dev_err(pctl->dev, "Can not find pin\n");
884 		return;
885 	}
886 
887 	gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
888 }
889 
890 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
891 	unsigned int eint_num, unsigned int offset)
892 {
893 	unsigned int eint_base = 0;
894 	void __iomem *reg;
895 
896 	if (eint_num >= pctl->devdata->ap_num)
897 		eint_base = pctl->devdata->ap_num;
898 
899 	reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
900 
901 	return reg;
902 }
903 
904 /*
905  * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
906  * @eint_num: the EINT number to setmtk_pinctrl
907  */
908 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
909 	unsigned int eint_num)
910 {
911 	unsigned int sens;
912 	unsigned int bit = BIT(eint_num % 32);
913 	const struct mtk_eint_offsets *eint_offsets =
914 		&pctl->devdata->eint_offsets;
915 
916 	void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
917 			eint_offsets->sens);
918 
919 	if (readl(reg) & bit)
920 		sens = MT_LEVEL_SENSITIVE;
921 	else
922 		sens = MT_EDGE_SENSITIVE;
923 
924 	if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
925 		return 1;
926 	else
927 		return 0;
928 }
929 
930 /*
931  * mtk_eint_get_mask: To get the eint mask
932  * @eint_num: the EINT number to get
933  */
934 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
935 	unsigned int eint_num)
936 {
937 	unsigned int bit = BIT(eint_num % 32);
938 	const struct mtk_eint_offsets *eint_offsets =
939 		&pctl->devdata->eint_offsets;
940 
941 	void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
942 			eint_offsets->mask);
943 
944 	return !!(readl(reg) & bit);
945 }
946 
947 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
948 {
949 	int start_level, curr_level;
950 	unsigned int reg_offset;
951 	const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
952 	u32 mask = BIT(hwirq & 0x1f);
953 	u32 port = (hwirq >> 5) & eint_offsets->port_mask;
954 	void __iomem *reg = pctl->eint_reg_base + (port << 2);
955 	const struct mtk_desc_pin *pin;
956 
957 	pin = mtk_find_pin_by_eint_num(pctl, hwirq);
958 	curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
959 	do {
960 		start_level = curr_level;
961 		if (start_level)
962 			reg_offset = eint_offsets->pol_clr;
963 		else
964 			reg_offset = eint_offsets->pol_set;
965 		writel(mask, reg + reg_offset);
966 
967 		curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
968 	} while (start_level != curr_level);
969 
970 	return start_level;
971 }
972 
973 static void mtk_eint_mask(struct irq_data *d)
974 {
975 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
976 	const struct mtk_eint_offsets *eint_offsets =
977 			&pctl->devdata->eint_offsets;
978 	u32 mask = BIT(d->hwirq & 0x1f);
979 	void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
980 			eint_offsets->mask_set);
981 
982 	writel(mask, reg);
983 }
984 
985 static void mtk_eint_unmask(struct irq_data *d)
986 {
987 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
988 	const struct mtk_eint_offsets *eint_offsets =
989 		&pctl->devdata->eint_offsets;
990 	u32 mask = BIT(d->hwirq & 0x1f);
991 	void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
992 			eint_offsets->mask_clr);
993 
994 	writel(mask, reg);
995 
996 	if (pctl->eint_dual_edges[d->hwirq])
997 		mtk_eint_flip_edge(pctl, d->hwirq);
998 }
999 
1000 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
1001 	unsigned debounce)
1002 {
1003 	struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
1004 	int eint_num, virq, eint_offset;
1005 	unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
1006 	static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
1007 						128000, 256000};
1008 	const struct mtk_desc_pin *pin;
1009 	struct irq_data *d;
1010 
1011 	pin = pctl->devdata->pins + offset;
1012 	if (pin->eint.eintnum == NO_EINT_SUPPORT)
1013 		return -EINVAL;
1014 
1015 	eint_num = pin->eint.eintnum;
1016 	virq = irq_find_mapping(pctl->domain, eint_num);
1017 	eint_offset = (eint_num % 4) * 8;
1018 	d = irq_get_irq_data(virq);
1019 
1020 	set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
1021 	clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
1022 	if (!mtk_eint_can_en_debounce(pctl, eint_num))
1023 		return -ENOSYS;
1024 
1025 	dbnc = ARRAY_SIZE(debounce_time);
1026 	for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
1027 		if (debounce <= debounce_time[i]) {
1028 			dbnc = i;
1029 			break;
1030 		}
1031 	}
1032 
1033 	if (!mtk_eint_get_mask(pctl, eint_num)) {
1034 		mtk_eint_mask(d);
1035 		unmask = 1;
1036 	} else {
1037 		unmask = 0;
1038 	}
1039 
1040 	clr_bit = 0xff << eint_offset;
1041 	writel(clr_bit, pctl->eint_reg_base + clr_offset);
1042 
1043 	bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
1044 		eint_offset;
1045 	rst = EINT_DBNC_RST_BIT << eint_offset;
1046 	writel(rst | bit, pctl->eint_reg_base + set_offset);
1047 
1048 	/* Delay a while (more than 2T) to wait for hw debounce counter reset
1049 	work correctly */
1050 	udelay(1);
1051 	if (unmask == 1)
1052 		mtk_eint_unmask(d);
1053 
1054 	return 0;
1055 }
1056 
1057 static const struct gpio_chip mtk_gpio_chip = {
1058 	.owner			= THIS_MODULE,
1059 	.request		= gpiochip_generic_request,
1060 	.free			= gpiochip_generic_free,
1061 	.get_direction		= mtk_gpio_get_direction,
1062 	.direction_input	= mtk_gpio_direction_input,
1063 	.direction_output	= mtk_gpio_direction_output,
1064 	.get			= mtk_gpio_get,
1065 	.set			= mtk_gpio_set,
1066 	.to_irq			= mtk_gpio_to_irq,
1067 	.set_debounce		= mtk_gpio_set_debounce,
1068 	.of_gpio_n_cells	= 2,
1069 };
1070 
1071 static int mtk_eint_set_type(struct irq_data *d,
1072 				      unsigned int type)
1073 {
1074 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1075 	const struct mtk_eint_offsets *eint_offsets =
1076 		&pctl->devdata->eint_offsets;
1077 	u32 mask = BIT(d->hwirq & 0x1f);
1078 	void __iomem *reg;
1079 
1080 	if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
1081 		((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1082 		dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1083 			d->irq, d->hwirq, type);
1084 		return -EINVAL;
1085 	}
1086 
1087 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1088 		pctl->eint_dual_edges[d->hwirq] = 1;
1089 	else
1090 		pctl->eint_dual_edges[d->hwirq] = 0;
1091 
1092 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1093 		reg = mtk_eint_get_offset(pctl, d->hwirq,
1094 			eint_offsets->pol_clr);
1095 		writel(mask, reg);
1096 	} else {
1097 		reg = mtk_eint_get_offset(pctl, d->hwirq,
1098 			eint_offsets->pol_set);
1099 		writel(mask, reg);
1100 	}
1101 
1102 	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1103 		reg = mtk_eint_get_offset(pctl, d->hwirq,
1104 			eint_offsets->sens_clr);
1105 		writel(mask, reg);
1106 	} else {
1107 		reg = mtk_eint_get_offset(pctl, d->hwirq,
1108 			eint_offsets->sens_set);
1109 		writel(mask, reg);
1110 	}
1111 
1112 	if (pctl->eint_dual_edges[d->hwirq])
1113 		mtk_eint_flip_edge(pctl, d->hwirq);
1114 
1115 	return 0;
1116 }
1117 
1118 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1119 {
1120 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1121 	int shift = d->hwirq & 0x1f;
1122 	int reg = d->hwirq >> 5;
1123 
1124 	if (on)
1125 		pctl->wake_mask[reg] |= BIT(shift);
1126 	else
1127 		pctl->wake_mask[reg] &= ~BIT(shift);
1128 
1129 	return 0;
1130 }
1131 
1132 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1133 		void __iomem *eint_reg_base, u32 *buf)
1134 {
1135 	int port;
1136 	void __iomem *reg;
1137 
1138 	for (port = 0; port < chip->ports; port++) {
1139 		reg = eint_reg_base + (port << 2);
1140 		writel_relaxed(~buf[port], reg + chip->mask_set);
1141 		writel_relaxed(buf[port], reg + chip->mask_clr);
1142 	}
1143 }
1144 
1145 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1146 		void __iomem *eint_reg_base, u32 *buf)
1147 {
1148 	int port;
1149 	void __iomem *reg;
1150 
1151 	for (port = 0; port < chip->ports; port++) {
1152 		reg = eint_reg_base + chip->mask + (port << 2);
1153 		buf[port] = ~readl_relaxed(reg);
1154 		/* Mask is 0 when irq is enabled, and 1 when disabled. */
1155 	}
1156 }
1157 
1158 static int mtk_eint_suspend(struct device *device)
1159 {
1160 	void __iomem *reg;
1161 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1162 	const struct mtk_eint_offsets *eint_offsets =
1163 			&pctl->devdata->eint_offsets;
1164 
1165 	reg = pctl->eint_reg_base;
1166 	mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1167 	mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1168 
1169 	return 0;
1170 }
1171 
1172 static int mtk_eint_resume(struct device *device)
1173 {
1174 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1175 	const struct mtk_eint_offsets *eint_offsets =
1176 			&pctl->devdata->eint_offsets;
1177 
1178 	mtk_eint_chip_write_mask(eint_offsets,
1179 			pctl->eint_reg_base, pctl->cur_mask);
1180 
1181 	return 0;
1182 }
1183 
1184 const struct dev_pm_ops mtk_eint_pm_ops = {
1185 	.suspend_noirq = mtk_eint_suspend,
1186 	.resume_noirq = mtk_eint_resume,
1187 };
1188 
1189 static void mtk_eint_ack(struct irq_data *d)
1190 {
1191 	struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1192 	const struct mtk_eint_offsets *eint_offsets =
1193 		&pctl->devdata->eint_offsets;
1194 	u32 mask = BIT(d->hwirq & 0x1f);
1195 	void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1196 			eint_offsets->ack);
1197 
1198 	writel(mask, reg);
1199 }
1200 
1201 static struct irq_chip mtk_pinctrl_irq_chip = {
1202 	.name = "mt-eint",
1203 	.irq_disable = mtk_eint_mask,
1204 	.irq_mask = mtk_eint_mask,
1205 	.irq_unmask = mtk_eint_unmask,
1206 	.irq_ack = mtk_eint_ack,
1207 	.irq_set_type = mtk_eint_set_type,
1208 	.irq_set_wake = mtk_eint_irq_set_wake,
1209 	.irq_request_resources = mtk_pinctrl_irq_request_resources,
1210 	.irq_release_resources = mtk_pinctrl_irq_release_resources,
1211 };
1212 
1213 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1214 {
1215 	const struct mtk_eint_offsets *eint_offsets =
1216 		&pctl->devdata->eint_offsets;
1217 	void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1218 	unsigned int i;
1219 
1220 	for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1221 		writel(0xffffffff, reg);
1222 		reg += 4;
1223 	}
1224 	return 0;
1225 }
1226 
1227 static inline void
1228 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1229 {
1230 	unsigned int rst, ctrl_offset;
1231 	unsigned int bit, dbnc;
1232 	const struct mtk_eint_offsets *eint_offsets =
1233 		&pctl->devdata->eint_offsets;
1234 
1235 	ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1236 	dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1237 	bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1238 	if ((bit & dbnc) > 0) {
1239 		ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1240 		rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1241 		writel(rst, pctl->eint_reg_base + ctrl_offset);
1242 	}
1243 }
1244 
1245 static void mtk_eint_irq_handler(struct irq_desc *desc)
1246 {
1247 	struct irq_chip *chip = irq_desc_get_chip(desc);
1248 	struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
1249 	unsigned int status, eint_num;
1250 	int offset, index, virq;
1251 	const struct mtk_eint_offsets *eint_offsets =
1252 		&pctl->devdata->eint_offsets;
1253 	void __iomem *reg =  mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1254 	int dual_edges, start_level, curr_level;
1255 	const struct mtk_desc_pin *pin;
1256 
1257 	chained_irq_enter(chip, desc);
1258 	for (eint_num = 0;
1259 	     eint_num < pctl->devdata->ap_num;
1260 	     eint_num += 32, reg += 4) {
1261 		status = readl(reg);
1262 		while (status) {
1263 			offset = __ffs(status);
1264 			index = eint_num + offset;
1265 			virq = irq_find_mapping(pctl->domain, index);
1266 			status &= ~BIT(offset);
1267 
1268 			dual_edges = pctl->eint_dual_edges[index];
1269 			if (dual_edges) {
1270 				/* Clear soft-irq in case we raised it
1271 				   last time */
1272 				writel(BIT(offset), reg - eint_offsets->stat +
1273 					eint_offsets->soft_clr);
1274 
1275 				pin = mtk_find_pin_by_eint_num(pctl, index);
1276 				start_level = mtk_gpio_get(pctl->chip,
1277 							   pin->pin.number);
1278 			}
1279 
1280 			generic_handle_irq(virq);
1281 
1282 			if (dual_edges) {
1283 				curr_level = mtk_eint_flip_edge(pctl, index);
1284 
1285 				/* If level changed, we might lost one edge
1286 				   interrupt, raised it through soft-irq */
1287 				if (start_level != curr_level)
1288 					writel(BIT(offset), reg -
1289 						eint_offsets->stat +
1290 						eint_offsets->soft_set);
1291 			}
1292 
1293 			if (index < pctl->devdata->db_cnt)
1294 				mtk_eint_debounce_process(pctl , index);
1295 		}
1296 	}
1297 	chained_irq_exit(chip, desc);
1298 }
1299 
1300 static int mtk_pctrl_build_state(struct platform_device *pdev)
1301 {
1302 	struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1303 	int i;
1304 
1305 	pctl->ngroups = pctl->devdata->npins;
1306 
1307 	/* Allocate groups */
1308 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1309 				    sizeof(*pctl->groups), GFP_KERNEL);
1310 	if (!pctl->groups)
1311 		return -ENOMEM;
1312 
1313 	/* We assume that one pin is one group, use pin name as group name. */
1314 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1315 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1316 	if (!pctl->grp_names)
1317 		return -ENOMEM;
1318 
1319 	for (i = 0; i < pctl->devdata->npins; i++) {
1320 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1321 		struct mtk_pinctrl_group *group = pctl->groups + i;
1322 
1323 		group->name = pin->pin.name;
1324 		group->pin = pin->pin.number;
1325 
1326 		pctl->grp_names[i] = pin->pin.name;
1327 	}
1328 
1329 	return 0;
1330 }
1331 
1332 int mtk_pctrl_init(struct platform_device *pdev,
1333 		const struct mtk_pinctrl_devdata *data,
1334 		struct regmap *regmap)
1335 {
1336 	struct pinctrl_pin_desc *pins;
1337 	struct mtk_pinctrl *pctl;
1338 	struct device_node *np = pdev->dev.of_node, *node;
1339 	struct property *prop;
1340 	struct resource *res;
1341 	int i, ret, irq, ports_buf;
1342 
1343 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1344 	if (!pctl)
1345 		return -ENOMEM;
1346 
1347 	platform_set_drvdata(pdev, pctl);
1348 
1349 	prop = of_find_property(np, "pins-are-numbered", NULL);
1350 	if (!prop) {
1351 		dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1352 		return -EINVAL;
1353 	}
1354 
1355 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1356 	if (node) {
1357 		pctl->regmap1 = syscon_node_to_regmap(node);
1358 		if (IS_ERR(pctl->regmap1))
1359 			return PTR_ERR(pctl->regmap1);
1360 	} else if (regmap) {
1361 		pctl->regmap1  = regmap;
1362 	} else {
1363 		dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1364 		return -EINVAL;
1365 	}
1366 
1367 	/* Only 8135 has two base addr, other SoCs have only one. */
1368 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1369 	if (node) {
1370 		pctl->regmap2 = syscon_node_to_regmap(node);
1371 		if (IS_ERR(pctl->regmap2))
1372 			return PTR_ERR(pctl->regmap2);
1373 	}
1374 
1375 	pctl->devdata = data;
1376 	ret = mtk_pctrl_build_state(pdev);
1377 	if (ret) {
1378 		dev_err(&pdev->dev, "build state failed: %d\n", ret);
1379 		return -EINVAL;
1380 	}
1381 
1382 	pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1383 			    GFP_KERNEL);
1384 	if (!pins)
1385 		return -ENOMEM;
1386 
1387 	for (i = 0; i < pctl->devdata->npins; i++)
1388 		pins[i] = pctl->devdata->pins[i].pin;
1389 
1390 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1391 	pctl->pctl_desc.owner = THIS_MODULE;
1392 	pctl->pctl_desc.pins = pins;
1393 	pctl->pctl_desc.npins = pctl->devdata->npins;
1394 	pctl->pctl_desc.confops = &mtk_pconf_ops;
1395 	pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1396 	pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1397 	pctl->dev = &pdev->dev;
1398 
1399 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1400 					       pctl);
1401 	if (IS_ERR(pctl->pctl_dev)) {
1402 		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1403 		return PTR_ERR(pctl->pctl_dev);
1404 	}
1405 
1406 	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1407 	if (!pctl->chip)
1408 		return -ENOMEM;
1409 
1410 	*pctl->chip = mtk_gpio_chip;
1411 	pctl->chip->ngpio = pctl->devdata->npins;
1412 	pctl->chip->label = dev_name(&pdev->dev);
1413 	pctl->chip->parent = &pdev->dev;
1414 	pctl->chip->base = -1;
1415 
1416 	ret = gpiochip_add_data(pctl->chip, pctl);
1417 	if (ret)
1418 		return -EINVAL;
1419 
1420 	/* Register the GPIO to pin mappings. */
1421 	ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1422 			0, 0, pctl->devdata->npins);
1423 	if (ret) {
1424 		ret = -EINVAL;
1425 		goto chip_error;
1426 	}
1427 
1428 	if (!of_property_read_bool(np, "interrupt-controller"))
1429 		return 0;
1430 
1431 	/* Get EINT register base from dts. */
1432 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433 	if (!res) {
1434 		dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1435 		ret = -EINVAL;
1436 		goto chip_error;
1437 	}
1438 
1439 	pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1440 	if (IS_ERR(pctl->eint_reg_base)) {
1441 		ret = -EINVAL;
1442 		goto chip_error;
1443 	}
1444 
1445 	ports_buf = pctl->devdata->eint_offsets.ports;
1446 	pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1447 					sizeof(*pctl->wake_mask), GFP_KERNEL);
1448 	if (!pctl->wake_mask) {
1449 		ret = -ENOMEM;
1450 		goto chip_error;
1451 	}
1452 
1453 	pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1454 					sizeof(*pctl->cur_mask), GFP_KERNEL);
1455 	if (!pctl->cur_mask) {
1456 		ret = -ENOMEM;
1457 		goto chip_error;
1458 	}
1459 
1460 	pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1461 					     sizeof(int), GFP_KERNEL);
1462 	if (!pctl->eint_dual_edges) {
1463 		ret = -ENOMEM;
1464 		goto chip_error;
1465 	}
1466 
1467 	irq = irq_of_parse_and_map(np, 0);
1468 	if (!irq) {
1469 		dev_err(&pdev->dev, "couldn't parse and map irq\n");
1470 		ret = -EINVAL;
1471 		goto chip_error;
1472 	}
1473 
1474 	pctl->domain = irq_domain_add_linear(np,
1475 		pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1476 	if (!pctl->domain) {
1477 		dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1478 		ret = -ENOMEM;
1479 		goto chip_error;
1480 	}
1481 
1482 	mtk_eint_init(pctl);
1483 	for (i = 0; i < pctl->devdata->ap_num; i++) {
1484 		int virq = irq_create_mapping(pctl->domain, i);
1485 
1486 		irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1487 			handle_level_irq);
1488 		irq_set_chip_data(virq, pctl);
1489 	}
1490 
1491 	irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1492 	return 0;
1493 
1494 chip_error:
1495 	gpiochip_remove(pctl->chip);
1496 	return ret;
1497 }
1498