1 /* 2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include <linux/bitops.h> 32 #include <linux/regmap.h> 33 #include <linux/mfd/syscon.h> 34 #include <linux/delay.h> 35 #include <linux/interrupt.h> 36 #include <linux/pm.h> 37 #include <dt-bindings/pinctrl/mt65xx.h> 38 39 #include "../core.h" 40 #include "../pinconf.h" 41 #include "../pinctrl-utils.h" 42 #include "pinctrl-mtk-common.h" 43 44 #define MAX_GPIO_MODE_PER_REG 5 45 #define GPIO_MODE_BITS 3 46 #define GPIO_MODE_PREFIX "GPIO" 47 48 static const char * const mtk_gpio_functions[] = { 49 "func0", "func1", "func2", "func3", 50 "func4", "func5", "func6", "func7", 51 "func8", "func9", "func10", "func11", 52 "func12", "func13", "func14", "func15", 53 }; 54 55 /* 56 * There are two base address for pull related configuration 57 * in mt8135, and different GPIO pins use different base address. 58 * When pin number greater than type1_start and less than type1_end, 59 * should use the second base address. 60 */ 61 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, 62 unsigned long pin) 63 { 64 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) 65 return pctl->regmap2; 66 return pctl->regmap1; 67 } 68 69 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) 70 { 71 /* Different SoC has different mask and port shift. */ 72 return ((pin >> 4) & pctl->devdata->port_mask) 73 << pctl->devdata->port_shf; 74 } 75 76 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 77 struct pinctrl_gpio_range *range, unsigned offset, 78 bool input) 79 { 80 unsigned int reg_addr; 81 unsigned int bit; 82 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 83 84 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 85 bit = BIT(offset & 0xf); 86 87 if (pctl->devdata->spec_dir_set) 88 pctl->devdata->spec_dir_set(®_addr, offset); 89 90 if (input) 91 /* Different SoC has different alignment offset. */ 92 reg_addr = CLR_ADDR(reg_addr, pctl); 93 else 94 reg_addr = SET_ADDR(reg_addr, pctl); 95 96 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 97 return 0; 98 } 99 100 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 101 { 102 unsigned int reg_addr; 103 unsigned int bit; 104 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 105 106 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; 107 bit = BIT(offset & 0xf); 108 109 if (value) 110 reg_addr = SET_ADDR(reg_addr, pctl); 111 else 112 reg_addr = CLR_ADDR(reg_addr, pctl); 113 114 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 115 } 116 117 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 118 int value, enum pin_config_param arg) 119 { 120 unsigned int reg_addr, offset; 121 unsigned int bit; 122 123 /** 124 * Due to some soc are not support ies/smt config, add this special 125 * control to handle it. 126 */ 127 if (!pctl->devdata->spec_ies_smt_set && 128 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && 129 arg == PIN_CONFIG_INPUT_ENABLE) 130 return -EINVAL; 131 132 if (!pctl->devdata->spec_ies_smt_set && 133 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && 134 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 135 return -EINVAL; 136 137 /* 138 * Due to some pins are irregular, their input enable and smt 139 * control register are discontinuous, so we need this special handle. 140 */ 141 if (pctl->devdata->spec_ies_smt_set) { 142 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 143 pin, pctl->devdata->port_align, value, arg); 144 } 145 146 bit = BIT(pin & 0xf); 147 148 if (arg == PIN_CONFIG_INPUT_ENABLE) 149 offset = pctl->devdata->ies_offset; 150 else 151 offset = pctl->devdata->smt_offset; 152 153 if (value) 154 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 155 else 156 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 157 158 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 159 return 0; 160 } 161 162 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 163 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 164 unsigned int pin, unsigned char align, int value) 165 { 166 unsigned int i, reg_addr, bit; 167 168 for (i = 0; i < info_num; i++) { 169 if (pin >= ies_smt_infos[i].start && 170 pin <= ies_smt_infos[i].end) { 171 break; 172 } 173 } 174 175 if (i == info_num) 176 return -EINVAL; 177 178 if (value) 179 reg_addr = ies_smt_infos[i].offset + align; 180 else 181 reg_addr = ies_smt_infos[i].offset + (align << 1); 182 183 bit = BIT(ies_smt_infos[i].bit); 184 regmap_write(regmap, reg_addr, bit); 185 return 0; 186 } 187 188 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 189 struct mtk_pinctrl *pctl, unsigned long pin) { 190 int i; 191 192 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { 193 const struct mtk_pin_drv_grp *pin_drv = 194 pctl->devdata->pin_drv_grp + i; 195 if (pin == pin_drv->pin) 196 return pin_drv; 197 } 198 199 return NULL; 200 } 201 202 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, 203 unsigned int pin, unsigned char driving) 204 { 205 const struct mtk_pin_drv_grp *pin_drv; 206 unsigned int val; 207 unsigned int bits, mask, shift; 208 const struct mtk_drv_group_desc *drv_grp; 209 210 if (pin >= pctl->devdata->npins) 211 return -EINVAL; 212 213 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); 214 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) 215 return -EINVAL; 216 217 drv_grp = pctl->devdata->grp_desc + pin_drv->grp; 218 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv 219 && !(driving % drv_grp->step)) { 220 val = driving / drv_grp->step - 1; 221 bits = drv_grp->high_bit - drv_grp->low_bit + 1; 222 mask = BIT(bits) - 1; 223 shift = pin_drv->bit + drv_grp->low_bit; 224 mask <<= shift; 225 val <<= shift; 226 return regmap_update_bits(mtk_get_regmap(pctl, pin), 227 pin_drv->offset, mask, val); 228 } 229 230 return -EINVAL; 231 } 232 233 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 234 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, 235 unsigned int info_num, unsigned int pin, 236 unsigned char align, bool isup, unsigned int r1r0) 237 { 238 unsigned int i; 239 unsigned int reg_pupd, reg_set, reg_rst; 240 unsigned int bit_pupd, bit_r0, bit_r1; 241 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; 242 bool find = false; 243 244 for (i = 0; i < info_num; i++) { 245 if (pin == pupd_infos[i].pin) { 246 find = true; 247 break; 248 } 249 } 250 251 if (!find) 252 return -EINVAL; 253 254 spec_pupd_pin = pupd_infos + i; 255 reg_set = spec_pupd_pin->offset + align; 256 reg_rst = spec_pupd_pin->offset + (align << 1); 257 258 if (isup) 259 reg_pupd = reg_rst; 260 else 261 reg_pupd = reg_set; 262 263 bit_pupd = BIT(spec_pupd_pin->pupd_bit); 264 regmap_write(regmap, reg_pupd, bit_pupd); 265 266 bit_r0 = BIT(spec_pupd_pin->r0_bit); 267 bit_r1 = BIT(spec_pupd_pin->r1_bit); 268 269 switch (r1r0) { 270 case MTK_PUPD_SET_R1R0_00: 271 regmap_write(regmap, reg_rst, bit_r0); 272 regmap_write(regmap, reg_rst, bit_r1); 273 break; 274 case MTK_PUPD_SET_R1R0_01: 275 regmap_write(regmap, reg_set, bit_r0); 276 regmap_write(regmap, reg_rst, bit_r1); 277 break; 278 case MTK_PUPD_SET_R1R0_10: 279 regmap_write(regmap, reg_rst, bit_r0); 280 regmap_write(regmap, reg_set, bit_r1); 281 break; 282 case MTK_PUPD_SET_R1R0_11: 283 regmap_write(regmap, reg_set, bit_r0); 284 regmap_write(regmap, reg_set, bit_r1); 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 return 0; 291 } 292 293 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 294 unsigned int pin, bool enable, bool isup, unsigned int arg) 295 { 296 unsigned int bit; 297 unsigned int reg_pullen, reg_pullsel; 298 int ret; 299 300 /* Some pins' pull setting are very different, 301 * they have separate pull up/down bit, R0 and R1 302 * resistor bit, so we need this special handle. 303 */ 304 if (pctl->devdata->spec_pull_set) { 305 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), 306 pin, pctl->devdata->port_align, isup, arg); 307 if (!ret) 308 return 0; 309 } 310 311 /* For generic pull config, default arg value should be 0 or 1. */ 312 if (arg != 0 && arg != 1) { 313 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", 314 arg, pin); 315 return -EINVAL; 316 } 317 318 bit = BIT(pin & 0xf); 319 if (enable) 320 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + 321 pctl->devdata->pullen_offset, pctl); 322 else 323 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + 324 pctl->devdata->pullen_offset, pctl); 325 326 if (isup) 327 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + 328 pctl->devdata->pullsel_offset, pctl); 329 else 330 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + 331 pctl->devdata->pullsel_offset, pctl); 332 333 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); 334 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); 335 return 0; 336 } 337 338 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, 339 unsigned int pin, enum pin_config_param param, 340 enum pin_config_param arg) 341 { 342 int ret = 0; 343 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 344 345 switch (param) { 346 case PIN_CONFIG_BIAS_DISABLE: 347 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 348 break; 349 case PIN_CONFIG_BIAS_PULL_UP: 350 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 351 break; 352 case PIN_CONFIG_BIAS_PULL_DOWN: 353 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 354 break; 355 case PIN_CONFIG_INPUT_ENABLE: 356 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 358 break; 359 case PIN_CONFIG_OUTPUT: 360 mtk_gpio_set(pctl->chip, pin, arg); 361 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 362 break; 363 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 364 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); 365 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 366 break; 367 case PIN_CONFIG_DRIVE_STRENGTH: 368 ret = mtk_pconf_set_driving(pctl, pin, arg); 369 break; 370 default: 371 ret = -EINVAL; 372 } 373 374 return ret; 375 } 376 377 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 378 unsigned group, 379 unsigned long *config) 380 { 381 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 382 383 *config = pctl->groups[group].config; 384 385 return 0; 386 } 387 388 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 389 unsigned long *configs, unsigned num_configs) 390 { 391 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 392 struct mtk_pinctrl_group *g = &pctl->groups[group]; 393 int i, ret; 394 395 for (i = 0; i < num_configs; i++) { 396 ret = mtk_pconf_parse_conf(pctldev, g->pin, 397 pinconf_to_config_param(configs[i]), 398 pinconf_to_config_argument(configs[i])); 399 if (ret < 0) 400 return ret; 401 402 g->config = configs[i]; 403 } 404 405 return 0; 406 } 407 408 static const struct pinconf_ops mtk_pconf_ops = { 409 .pin_config_group_get = mtk_pconf_group_get, 410 .pin_config_group_set = mtk_pconf_group_set, 411 }; 412 413 static struct mtk_pinctrl_group * 414 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) 415 { 416 int i; 417 418 for (i = 0; i < pctl->ngroups; i++) { 419 struct mtk_pinctrl_group *grp = pctl->groups + i; 420 421 if (grp->pin == pin) 422 return grp; 423 } 424 425 return NULL; 426 } 427 428 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( 429 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) 430 { 431 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; 432 const struct mtk_desc_function *func = pin->functions; 433 434 while (func && func->name) { 435 if (func->muxval == fnum) 436 return func; 437 func++; 438 } 439 440 return NULL; 441 } 442 443 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, 444 u32 pin_num, u32 fnum) 445 { 446 int i; 447 448 for (i = 0; i < pctl->devdata->npins; i++) { 449 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 450 451 if (pin->pin.number == pin_num) { 452 const struct mtk_desc_function *func = 453 pin->functions; 454 455 while (func && func->name) { 456 if (func->muxval == fnum) 457 return true; 458 func++; 459 } 460 461 break; 462 } 463 } 464 465 return false; 466 } 467 468 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 469 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, 470 struct pinctrl_map **map, unsigned *reserved_maps, 471 unsigned *num_maps) 472 { 473 bool ret; 474 475 if (*num_maps == *reserved_maps) 476 return -ENOSPC; 477 478 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 479 (*map)[*num_maps].data.mux.group = grp->name; 480 481 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 482 if (!ret) { 483 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 484 fnum, pin); 485 return -EINVAL; 486 } 487 488 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 489 (*num_maps)++; 490 491 return 0; 492 } 493 494 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 495 struct device_node *node, 496 struct pinctrl_map **map, 497 unsigned *reserved_maps, 498 unsigned *num_maps) 499 { 500 struct property *pins; 501 u32 pinfunc, pin, func; 502 int num_pins, num_funcs, maps_per_pin; 503 unsigned long *configs; 504 unsigned int num_configs; 505 bool has_config = 0; 506 int i, err; 507 unsigned reserve = 0; 508 struct mtk_pinctrl_group *grp; 509 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 510 511 pins = of_find_property(node, "pinmux", NULL); 512 if (!pins) { 513 dev_err(pctl->dev, "missing pins property in node %s .\n", 514 node->name); 515 return -EINVAL; 516 } 517 518 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 519 &num_configs); 520 if (err) 521 return err; 522 523 if (num_configs) 524 has_config = 1; 525 526 num_pins = pins->length / sizeof(u32); 527 num_funcs = num_pins; 528 maps_per_pin = 0; 529 if (num_funcs) 530 maps_per_pin++; 531 if (has_config && num_pins >= 1) 532 maps_per_pin++; 533 534 if (!num_pins || !maps_per_pin) { 535 err = -EINVAL; 536 goto exit; 537 } 538 539 reserve = num_pins * maps_per_pin; 540 541 err = pinctrl_utils_reserve_map(pctldev, map, 542 reserved_maps, num_maps, reserve); 543 if (err < 0) 544 goto exit; 545 546 for (i = 0; i < num_pins; i++) { 547 err = of_property_read_u32_index(node, "pinmux", 548 i, &pinfunc); 549 if (err) 550 goto exit; 551 552 pin = MTK_GET_PIN_NO(pinfunc); 553 func = MTK_GET_PIN_FUNC(pinfunc); 554 555 if (pin >= pctl->devdata->npins || 556 func >= ARRAY_SIZE(mtk_gpio_functions)) { 557 dev_err(pctl->dev, "invalid pins value.\n"); 558 err = -EINVAL; 559 goto exit; 560 } 561 562 grp = mtk_pctrl_find_group_by_pin(pctl, pin); 563 if (!grp) { 564 dev_err(pctl->dev, "unable to match pin %d to group\n", 565 pin); 566 err = -EINVAL; 567 goto exit; 568 } 569 570 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 571 reserved_maps, num_maps); 572 if (err < 0) 573 goto exit; 574 575 if (has_config) { 576 err = pinctrl_utils_add_map_configs(pctldev, map, 577 reserved_maps, num_maps, grp->name, 578 configs, num_configs, 579 PIN_MAP_TYPE_CONFIGS_GROUP); 580 if (err < 0) 581 goto exit; 582 } 583 } 584 585 err = 0; 586 587 exit: 588 kfree(configs); 589 return err; 590 } 591 592 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 593 struct device_node *np_config, 594 struct pinctrl_map **map, unsigned *num_maps) 595 { 596 struct device_node *np; 597 unsigned reserved_maps; 598 int ret; 599 600 *map = NULL; 601 *num_maps = 0; 602 reserved_maps = 0; 603 604 for_each_child_of_node(np_config, np) { 605 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 606 &reserved_maps, num_maps); 607 if (ret < 0) { 608 pinctrl_utils_free_map(pctldev, *map, *num_maps); 609 of_node_put(np); 610 return ret; 611 } 612 } 613 614 return 0; 615 } 616 617 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 618 { 619 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 620 621 return pctl->ngroups; 622 } 623 624 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 625 unsigned group) 626 { 627 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 628 629 return pctl->groups[group].name; 630 } 631 632 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 633 unsigned group, 634 const unsigned **pins, 635 unsigned *num_pins) 636 { 637 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 638 639 *pins = (unsigned *)&pctl->groups[group].pin; 640 *num_pins = 1; 641 642 return 0; 643 } 644 645 static const struct pinctrl_ops mtk_pctrl_ops = { 646 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 647 .dt_free_map = pinctrl_utils_free_map, 648 .get_groups_count = mtk_pctrl_get_groups_count, 649 .get_group_name = mtk_pctrl_get_group_name, 650 .get_group_pins = mtk_pctrl_get_group_pins, 651 }; 652 653 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 654 { 655 return ARRAY_SIZE(mtk_gpio_functions); 656 } 657 658 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 659 unsigned selector) 660 { 661 return mtk_gpio_functions[selector]; 662 } 663 664 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 665 unsigned function, 666 const char * const **groups, 667 unsigned * const num_groups) 668 { 669 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 670 671 *groups = pctl->grp_names; 672 *num_groups = pctl->ngroups; 673 674 return 0; 675 } 676 677 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, 678 unsigned long pin, unsigned long mode) 679 { 680 unsigned int reg_addr; 681 unsigned char bit; 682 unsigned int val; 683 unsigned int mask = (1L << GPIO_MODE_BITS) - 1; 684 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 685 686 if (pctl->devdata->spec_pinmux_set) 687 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), 688 pin, mode); 689 690 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) 691 + pctl->devdata->pinmux_offset; 692 693 mode &= mask; 694 bit = pin % MAX_GPIO_MODE_PER_REG; 695 mask <<= (GPIO_MODE_BITS * bit); 696 val = (mode << (GPIO_MODE_BITS * bit)); 697 return regmap_update_bits(mtk_get_regmap(pctl, pin), 698 reg_addr, mask, val); 699 } 700 701 static const struct mtk_desc_pin * 702 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) 703 { 704 int i; 705 const struct mtk_desc_pin *pin; 706 707 for (i = 0; i < pctl->devdata->npins; i++) { 708 pin = pctl->devdata->pins + i; 709 if (pin->eint.eintnum == eint_num) 710 return pin; 711 } 712 713 return NULL; 714 } 715 716 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 717 unsigned function, 718 unsigned group) 719 { 720 bool ret; 721 const struct mtk_desc_function *desc; 722 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 723 struct mtk_pinctrl_group *g = pctl->groups + group; 724 725 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 726 if (!ret) { 727 dev_err(pctl->dev, "invalid function %d on group %d .\n", 728 function, group); 729 return -EINVAL; 730 } 731 732 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); 733 if (!desc) 734 return -EINVAL; 735 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); 736 return 0; 737 } 738 739 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl, 740 unsigned offset) 741 { 742 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset; 743 const struct mtk_desc_function *func = pin->functions; 744 745 while (func && func->name) { 746 if (!strncmp(func->name, GPIO_MODE_PREFIX, 747 sizeof(GPIO_MODE_PREFIX)-1)) 748 return func->muxval; 749 func++; 750 } 751 return -EINVAL; 752 } 753 754 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 755 struct pinctrl_gpio_range *range, 756 unsigned offset) 757 { 758 int muxval; 759 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 760 761 muxval = mtk_pmx_find_gpio_mode(pctl, offset); 762 763 if (muxval < 0) { 764 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset); 765 return -EINVAL; 766 } 767 768 mtk_pmx_set_mode(pctldev, offset, muxval); 769 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE); 770 771 return 0; 772 } 773 774 static const struct pinmux_ops mtk_pmx_ops = { 775 .get_functions_count = mtk_pmx_get_funcs_cnt, 776 .get_function_name = mtk_pmx_get_func_name, 777 .get_function_groups = mtk_pmx_get_func_groups, 778 .set_mux = mtk_pmx_set_mux, 779 .gpio_set_direction = mtk_pmx_gpio_set_direction, 780 .gpio_request_enable = mtk_pmx_gpio_request_enable, 781 }; 782 783 static int mtk_gpio_direction_input(struct gpio_chip *chip, 784 unsigned offset) 785 { 786 return pinctrl_gpio_direction_input(chip->base + offset); 787 } 788 789 static int mtk_gpio_direction_output(struct gpio_chip *chip, 790 unsigned offset, int value) 791 { 792 mtk_gpio_set(chip, offset, value); 793 return pinctrl_gpio_direction_output(chip->base + offset); 794 } 795 796 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 797 { 798 unsigned int reg_addr; 799 unsigned int bit; 800 unsigned int read_val = 0; 801 802 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 803 804 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 805 bit = BIT(offset & 0xf); 806 807 if (pctl->devdata->spec_dir_set) 808 pctl->devdata->spec_dir_set(®_addr, offset); 809 810 regmap_read(pctl->regmap1, reg_addr, &read_val); 811 return !(read_val & bit); 812 } 813 814 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) 815 { 816 unsigned int reg_addr; 817 unsigned int bit; 818 unsigned int read_val = 0; 819 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 820 821 reg_addr = mtk_get_port(pctl, offset) + 822 pctl->devdata->din_offset; 823 824 bit = BIT(offset & 0xf); 825 regmap_read(pctl->regmap1, reg_addr, &read_val); 826 return !!(read_val & bit); 827 } 828 829 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 830 { 831 const struct mtk_desc_pin *pin; 832 struct mtk_pinctrl *pctl = gpiochip_get_data(chip); 833 int irq; 834 835 pin = pctl->devdata->pins + offset; 836 if (pin->eint.eintnum == NO_EINT_SUPPORT) 837 return -EINVAL; 838 839 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); 840 if (!irq) 841 return -EINVAL; 842 843 return irq; 844 } 845 846 static int mtk_pinctrl_irq_request_resources(struct irq_data *d) 847 { 848 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 849 const struct mtk_desc_pin *pin; 850 int ret; 851 852 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 853 854 if (!pin) { 855 dev_err(pctl->dev, "Can not find pin\n"); 856 return -EINVAL; 857 } 858 859 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); 860 if (ret) { 861 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 862 irqd_to_hwirq(d)); 863 return ret; 864 } 865 866 /* set mux to INT mode */ 867 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); 868 /* set gpio direction to input */ 869 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true); 870 /* set input-enable */ 871 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE); 872 873 return 0; 874 } 875 876 static void mtk_pinctrl_irq_release_resources(struct irq_data *d) 877 { 878 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 879 const struct mtk_desc_pin *pin; 880 881 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 882 883 if (!pin) { 884 dev_err(pctl->dev, "Can not find pin\n"); 885 return; 886 } 887 888 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); 889 } 890 891 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, 892 unsigned int eint_num, unsigned int offset) 893 { 894 unsigned int eint_base = 0; 895 void __iomem *reg; 896 897 if (eint_num >= pctl->devdata->ap_num) 898 eint_base = pctl->devdata->ap_num; 899 900 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; 901 902 return reg; 903 } 904 905 /* 906 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not 907 * @eint_num: the EINT number to setmtk_pinctrl 908 */ 909 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, 910 unsigned int eint_num) 911 { 912 unsigned int sens; 913 unsigned int bit = BIT(eint_num % 32); 914 const struct mtk_eint_offsets *eint_offsets = 915 &pctl->devdata->eint_offsets; 916 917 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 918 eint_offsets->sens); 919 920 if (readl(reg) & bit) 921 sens = MT_LEVEL_SENSITIVE; 922 else 923 sens = MT_EDGE_SENSITIVE; 924 925 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) 926 return 1; 927 else 928 return 0; 929 } 930 931 /* 932 * mtk_eint_get_mask: To get the eint mask 933 * @eint_num: the EINT number to get 934 */ 935 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, 936 unsigned int eint_num) 937 { 938 unsigned int bit = BIT(eint_num % 32); 939 const struct mtk_eint_offsets *eint_offsets = 940 &pctl->devdata->eint_offsets; 941 942 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 943 eint_offsets->mask); 944 945 return !!(readl(reg) & bit); 946 } 947 948 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) 949 { 950 int start_level, curr_level; 951 unsigned int reg_offset; 952 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); 953 u32 mask = BIT(hwirq & 0x1f); 954 u32 port = (hwirq >> 5) & eint_offsets->port_mask; 955 void __iomem *reg = pctl->eint_reg_base + (port << 2); 956 const struct mtk_desc_pin *pin; 957 958 pin = mtk_find_pin_by_eint_num(pctl, hwirq); 959 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 960 do { 961 start_level = curr_level; 962 if (start_level) 963 reg_offset = eint_offsets->pol_clr; 964 else 965 reg_offset = eint_offsets->pol_set; 966 writel(mask, reg + reg_offset); 967 968 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 969 } while (start_level != curr_level); 970 971 return start_level; 972 } 973 974 static void mtk_eint_mask(struct irq_data *d) 975 { 976 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 977 const struct mtk_eint_offsets *eint_offsets = 978 &pctl->devdata->eint_offsets; 979 u32 mask = BIT(d->hwirq & 0x1f); 980 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 981 eint_offsets->mask_set); 982 983 writel(mask, reg); 984 } 985 986 static void mtk_eint_unmask(struct irq_data *d) 987 { 988 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 989 const struct mtk_eint_offsets *eint_offsets = 990 &pctl->devdata->eint_offsets; 991 u32 mask = BIT(d->hwirq & 0x1f); 992 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 993 eint_offsets->mask_clr); 994 995 writel(mask, reg); 996 997 if (pctl->eint_dual_edges[d->hwirq]) 998 mtk_eint_flip_edge(pctl, d->hwirq); 999 } 1000 1001 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, 1002 unsigned debounce) 1003 { 1004 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent); 1005 int eint_num, virq, eint_offset; 1006 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; 1007 static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000, 1008 128000, 256000}; 1009 const struct mtk_desc_pin *pin; 1010 struct irq_data *d; 1011 1012 pin = pctl->devdata->pins + offset; 1013 if (pin->eint.eintnum == NO_EINT_SUPPORT) 1014 return -EINVAL; 1015 1016 eint_num = pin->eint.eintnum; 1017 virq = irq_find_mapping(pctl->domain, eint_num); 1018 eint_offset = (eint_num % 4) * 8; 1019 d = irq_get_irq_data(virq); 1020 1021 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; 1022 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; 1023 if (!mtk_eint_can_en_debounce(pctl, eint_num)) 1024 return -ENOSYS; 1025 1026 dbnc = ARRAY_SIZE(debounce_time); 1027 for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { 1028 if (debounce <= debounce_time[i]) { 1029 dbnc = i; 1030 break; 1031 } 1032 } 1033 1034 if (!mtk_eint_get_mask(pctl, eint_num)) { 1035 mtk_eint_mask(d); 1036 unmask = 1; 1037 } else { 1038 unmask = 0; 1039 } 1040 1041 clr_bit = 0xff << eint_offset; 1042 writel(clr_bit, pctl->eint_reg_base + clr_offset); 1043 1044 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << 1045 eint_offset; 1046 rst = EINT_DBNC_RST_BIT << eint_offset; 1047 writel(rst | bit, pctl->eint_reg_base + set_offset); 1048 1049 /* Delay a while (more than 2T) to wait for hw debounce counter reset 1050 work correctly */ 1051 udelay(1); 1052 if (unmask == 1) 1053 mtk_eint_unmask(d); 1054 1055 return 0; 1056 } 1057 1058 static struct gpio_chip mtk_gpio_chip = { 1059 .owner = THIS_MODULE, 1060 .request = gpiochip_generic_request, 1061 .free = gpiochip_generic_free, 1062 .get_direction = mtk_gpio_get_direction, 1063 .direction_input = mtk_gpio_direction_input, 1064 .direction_output = mtk_gpio_direction_output, 1065 .get = mtk_gpio_get, 1066 .set = mtk_gpio_set, 1067 .to_irq = mtk_gpio_to_irq, 1068 .set_debounce = mtk_gpio_set_debounce, 1069 .of_gpio_n_cells = 2, 1070 }; 1071 1072 static int mtk_eint_set_type(struct irq_data *d, 1073 unsigned int type) 1074 { 1075 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1076 const struct mtk_eint_offsets *eint_offsets = 1077 &pctl->devdata->eint_offsets; 1078 u32 mask = BIT(d->hwirq & 0x1f); 1079 void __iomem *reg; 1080 1081 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || 1082 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { 1083 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", 1084 d->irq, d->hwirq, type); 1085 return -EINVAL; 1086 } 1087 1088 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1089 pctl->eint_dual_edges[d->hwirq] = 1; 1090 else 1091 pctl->eint_dual_edges[d->hwirq] = 0; 1092 1093 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { 1094 reg = mtk_eint_get_offset(pctl, d->hwirq, 1095 eint_offsets->pol_clr); 1096 writel(mask, reg); 1097 } else { 1098 reg = mtk_eint_get_offset(pctl, d->hwirq, 1099 eint_offsets->pol_set); 1100 writel(mask, reg); 1101 } 1102 1103 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 1104 reg = mtk_eint_get_offset(pctl, d->hwirq, 1105 eint_offsets->sens_clr); 1106 writel(mask, reg); 1107 } else { 1108 reg = mtk_eint_get_offset(pctl, d->hwirq, 1109 eint_offsets->sens_set); 1110 writel(mask, reg); 1111 } 1112 1113 if (pctl->eint_dual_edges[d->hwirq]) 1114 mtk_eint_flip_edge(pctl, d->hwirq); 1115 1116 return 0; 1117 } 1118 1119 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) 1120 { 1121 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1122 int shift = d->hwirq & 0x1f; 1123 int reg = d->hwirq >> 5; 1124 1125 if (on) 1126 pctl->wake_mask[reg] |= BIT(shift); 1127 else 1128 pctl->wake_mask[reg] &= ~BIT(shift); 1129 1130 return 0; 1131 } 1132 1133 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip, 1134 void __iomem *eint_reg_base, u32 *buf) 1135 { 1136 int port; 1137 void __iomem *reg; 1138 1139 for (port = 0; port < chip->ports; port++) { 1140 reg = eint_reg_base + (port << 2); 1141 writel_relaxed(~buf[port], reg + chip->mask_set); 1142 writel_relaxed(buf[port], reg + chip->mask_clr); 1143 } 1144 } 1145 1146 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip, 1147 void __iomem *eint_reg_base, u32 *buf) 1148 { 1149 int port; 1150 void __iomem *reg; 1151 1152 for (port = 0; port < chip->ports; port++) { 1153 reg = eint_reg_base + chip->mask + (port << 2); 1154 buf[port] = ~readl_relaxed(reg); 1155 /* Mask is 0 when irq is enabled, and 1 when disabled. */ 1156 } 1157 } 1158 1159 static int mtk_eint_suspend(struct device *device) 1160 { 1161 void __iomem *reg; 1162 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 1163 const struct mtk_eint_offsets *eint_offsets = 1164 &pctl->devdata->eint_offsets; 1165 1166 reg = pctl->eint_reg_base; 1167 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask); 1168 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask); 1169 1170 return 0; 1171 } 1172 1173 static int mtk_eint_resume(struct device *device) 1174 { 1175 struct mtk_pinctrl *pctl = dev_get_drvdata(device); 1176 const struct mtk_eint_offsets *eint_offsets = 1177 &pctl->devdata->eint_offsets; 1178 1179 mtk_eint_chip_write_mask(eint_offsets, 1180 pctl->eint_reg_base, pctl->cur_mask); 1181 1182 return 0; 1183 } 1184 1185 const struct dev_pm_ops mtk_eint_pm_ops = { 1186 .suspend = mtk_eint_suspend, 1187 .resume = mtk_eint_resume, 1188 }; 1189 1190 static void mtk_eint_ack(struct irq_data *d) 1191 { 1192 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1193 const struct mtk_eint_offsets *eint_offsets = 1194 &pctl->devdata->eint_offsets; 1195 u32 mask = BIT(d->hwirq & 0x1f); 1196 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 1197 eint_offsets->ack); 1198 1199 writel(mask, reg); 1200 } 1201 1202 static struct irq_chip mtk_pinctrl_irq_chip = { 1203 .name = "mt-eint", 1204 .irq_disable = mtk_eint_mask, 1205 .irq_mask = mtk_eint_mask, 1206 .irq_unmask = mtk_eint_unmask, 1207 .irq_ack = mtk_eint_ack, 1208 .irq_set_type = mtk_eint_set_type, 1209 .irq_set_wake = mtk_eint_irq_set_wake, 1210 .irq_request_resources = mtk_pinctrl_irq_request_resources, 1211 .irq_release_resources = mtk_pinctrl_irq_release_resources, 1212 }; 1213 1214 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) 1215 { 1216 const struct mtk_eint_offsets *eint_offsets = 1217 &pctl->devdata->eint_offsets; 1218 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; 1219 unsigned int i; 1220 1221 for (i = 0; i < pctl->devdata->ap_num; i += 32) { 1222 writel(0xffffffff, reg); 1223 reg += 4; 1224 } 1225 return 0; 1226 } 1227 1228 static inline void 1229 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) 1230 { 1231 unsigned int rst, ctrl_offset; 1232 unsigned int bit, dbnc; 1233 const struct mtk_eint_offsets *eint_offsets = 1234 &pctl->devdata->eint_offsets; 1235 1236 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; 1237 dbnc = readl(pctl->eint_reg_base + ctrl_offset); 1238 bit = EINT_DBNC_SET_EN << ((index % 4) * 8); 1239 if ((bit & dbnc) > 0) { 1240 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; 1241 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); 1242 writel(rst, pctl->eint_reg_base + ctrl_offset); 1243 } 1244 } 1245 1246 static void mtk_eint_irq_handler(struct irq_desc *desc) 1247 { 1248 struct irq_chip *chip = irq_desc_get_chip(desc); 1249 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc); 1250 unsigned int status, eint_num; 1251 int offset, index, virq; 1252 const struct mtk_eint_offsets *eint_offsets = 1253 &pctl->devdata->eint_offsets; 1254 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); 1255 int dual_edges, start_level, curr_level; 1256 const struct mtk_desc_pin *pin; 1257 1258 chained_irq_enter(chip, desc); 1259 for (eint_num = 0; 1260 eint_num < pctl->devdata->ap_num; 1261 eint_num += 32, reg += 4) { 1262 status = readl(reg); 1263 while (status) { 1264 offset = __ffs(status); 1265 index = eint_num + offset; 1266 virq = irq_find_mapping(pctl->domain, index); 1267 status &= ~BIT(offset); 1268 1269 dual_edges = pctl->eint_dual_edges[index]; 1270 if (dual_edges) { 1271 /* Clear soft-irq in case we raised it 1272 last time */ 1273 writel(BIT(offset), reg - eint_offsets->stat + 1274 eint_offsets->soft_clr); 1275 1276 pin = mtk_find_pin_by_eint_num(pctl, index); 1277 start_level = mtk_gpio_get(pctl->chip, 1278 pin->pin.number); 1279 } 1280 1281 generic_handle_irq(virq); 1282 1283 if (dual_edges) { 1284 curr_level = mtk_eint_flip_edge(pctl, index); 1285 1286 /* If level changed, we might lost one edge 1287 interrupt, raised it through soft-irq */ 1288 if (start_level != curr_level) 1289 writel(BIT(offset), reg - 1290 eint_offsets->stat + 1291 eint_offsets->soft_set); 1292 } 1293 1294 if (index < pctl->devdata->db_cnt) 1295 mtk_eint_debounce_process(pctl , index); 1296 } 1297 } 1298 chained_irq_exit(chip, desc); 1299 } 1300 1301 static int mtk_pctrl_build_state(struct platform_device *pdev) 1302 { 1303 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); 1304 int i; 1305 1306 pctl->ngroups = pctl->devdata->npins; 1307 1308 /* Allocate groups */ 1309 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1310 sizeof(*pctl->groups), GFP_KERNEL); 1311 if (!pctl->groups) 1312 return -ENOMEM; 1313 1314 /* We assume that one pin is one group, use pin name as group name. */ 1315 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1316 sizeof(*pctl->grp_names), GFP_KERNEL); 1317 if (!pctl->grp_names) 1318 return -ENOMEM; 1319 1320 for (i = 0; i < pctl->devdata->npins; i++) { 1321 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 1322 struct mtk_pinctrl_group *group = pctl->groups + i; 1323 1324 group->name = pin->pin.name; 1325 group->pin = pin->pin.number; 1326 1327 pctl->grp_names[i] = pin->pin.name; 1328 } 1329 1330 return 0; 1331 } 1332 1333 int mtk_pctrl_init(struct platform_device *pdev, 1334 const struct mtk_pinctrl_devdata *data, 1335 struct regmap *regmap) 1336 { 1337 struct pinctrl_pin_desc *pins; 1338 struct mtk_pinctrl *pctl; 1339 struct device_node *np = pdev->dev.of_node, *node; 1340 struct property *prop; 1341 struct resource *res; 1342 int i, ret, irq, ports_buf; 1343 1344 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1345 if (!pctl) 1346 return -ENOMEM; 1347 1348 platform_set_drvdata(pdev, pctl); 1349 1350 prop = of_find_property(np, "pins-are-numbered", NULL); 1351 if (!prop) { 1352 dev_err(&pdev->dev, "only support pins-are-numbered format\n"); 1353 return -EINVAL; 1354 } 1355 1356 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); 1357 if (node) { 1358 pctl->regmap1 = syscon_node_to_regmap(node); 1359 if (IS_ERR(pctl->regmap1)) 1360 return PTR_ERR(pctl->regmap1); 1361 } else if (regmap) { 1362 pctl->regmap1 = regmap; 1363 } else { 1364 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); 1365 return -EINVAL; 1366 } 1367 1368 /* Only 8135 has two base addr, other SoCs have only one. */ 1369 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); 1370 if (node) { 1371 pctl->regmap2 = syscon_node_to_regmap(node); 1372 if (IS_ERR(pctl->regmap2)) 1373 return PTR_ERR(pctl->regmap2); 1374 } 1375 1376 pctl->devdata = data; 1377 ret = mtk_pctrl_build_state(pdev); 1378 if (ret) { 1379 dev_err(&pdev->dev, "build state failed: %d\n", ret); 1380 return -EINVAL; 1381 } 1382 1383 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), 1384 GFP_KERNEL); 1385 if (!pins) 1386 return -ENOMEM; 1387 1388 for (i = 0; i < pctl->devdata->npins; i++) 1389 pins[i] = pctl->devdata->pins[i].pin; 1390 1391 pctl->pctl_desc.name = dev_name(&pdev->dev); 1392 pctl->pctl_desc.owner = THIS_MODULE; 1393 pctl->pctl_desc.pins = pins; 1394 pctl->pctl_desc.npins = pctl->devdata->npins; 1395 pctl->pctl_desc.confops = &mtk_pconf_ops; 1396 pctl->pctl_desc.pctlops = &mtk_pctrl_ops; 1397 pctl->pctl_desc.pmxops = &mtk_pmx_ops; 1398 pctl->dev = &pdev->dev; 1399 1400 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1401 pctl); 1402 if (IS_ERR(pctl->pctl_dev)) { 1403 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1404 return PTR_ERR(pctl->pctl_dev); 1405 } 1406 1407 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1408 if (!pctl->chip) 1409 return -ENOMEM; 1410 1411 *pctl->chip = mtk_gpio_chip; 1412 pctl->chip->ngpio = pctl->devdata->npins; 1413 pctl->chip->label = dev_name(&pdev->dev); 1414 pctl->chip->parent = &pdev->dev; 1415 pctl->chip->base = -1; 1416 1417 ret = gpiochip_add_data(pctl->chip, pctl); 1418 if (ret) 1419 return -EINVAL; 1420 1421 /* Register the GPIO to pin mappings. */ 1422 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1423 0, 0, pctl->devdata->npins); 1424 if (ret) { 1425 ret = -EINVAL; 1426 goto chip_error; 1427 } 1428 1429 if (!of_property_read_bool(np, "interrupt-controller")) 1430 return 0; 1431 1432 /* Get EINT register base from dts. */ 1433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1434 if (!res) { 1435 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); 1436 ret = -EINVAL; 1437 goto chip_error; 1438 } 1439 1440 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); 1441 if (IS_ERR(pctl->eint_reg_base)) { 1442 ret = -EINVAL; 1443 goto chip_error; 1444 } 1445 1446 ports_buf = pctl->devdata->eint_offsets.ports; 1447 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf, 1448 sizeof(*pctl->wake_mask), GFP_KERNEL); 1449 if (!pctl->wake_mask) { 1450 ret = -ENOMEM; 1451 goto chip_error; 1452 } 1453 1454 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf, 1455 sizeof(*pctl->cur_mask), GFP_KERNEL); 1456 if (!pctl->cur_mask) { 1457 ret = -ENOMEM; 1458 goto chip_error; 1459 } 1460 1461 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, 1462 sizeof(int), GFP_KERNEL); 1463 if (!pctl->eint_dual_edges) { 1464 ret = -ENOMEM; 1465 goto chip_error; 1466 } 1467 1468 irq = irq_of_parse_and_map(np, 0); 1469 if (!irq) { 1470 dev_err(&pdev->dev, "couldn't parse and map irq\n"); 1471 ret = -EINVAL; 1472 goto chip_error; 1473 } 1474 1475 pctl->domain = irq_domain_add_linear(np, 1476 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); 1477 if (!pctl->domain) { 1478 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1479 ret = -ENOMEM; 1480 goto chip_error; 1481 } 1482 1483 mtk_eint_init(pctl); 1484 for (i = 0; i < pctl->devdata->ap_num; i++) { 1485 int virq = irq_create_mapping(pctl->domain, i); 1486 1487 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, 1488 handle_level_irq); 1489 irq_set_chip_data(virq, pctl); 1490 } 1491 1492 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); 1493 return 0; 1494 1495 chip_error: 1496 gpiochip_remove(pctl->chip); 1497 return ret; 1498 } 1499 1500 MODULE_LICENSE("GPL"); 1501 MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); 1502 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); 1503