1 /* 2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/io.h> 17 #include <linux/gpio.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include <linux/bitops.h> 32 #include <linux/regmap.h> 33 #include <linux/mfd/syscon.h> 34 #include <linux/delay.h> 35 #include <linux/interrupt.h> 36 #include <dt-bindings/pinctrl/mt65xx.h> 37 38 #include "../core.h" 39 #include "../pinconf.h" 40 #include "../pinctrl-utils.h" 41 #include "pinctrl-mtk-common.h" 42 43 #define MAX_GPIO_MODE_PER_REG 5 44 #define GPIO_MODE_BITS 3 45 46 static const char * const mtk_gpio_functions[] = { 47 "func0", "func1", "func2", "func3", 48 "func4", "func5", "func6", "func7", 49 }; 50 51 /* 52 * There are two base address for pull related configuration 53 * in mt8135, and different GPIO pins use different base address. 54 * When pin number greater than type1_start and less than type1_end, 55 * should use the second base address. 56 */ 57 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, 58 unsigned long pin) 59 { 60 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) 61 return pctl->regmap2; 62 return pctl->regmap1; 63 } 64 65 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) 66 { 67 /* Different SoC has different mask and port shift. */ 68 return ((pin >> 4) & pctl->devdata->port_mask) 69 << pctl->devdata->port_shf; 70 } 71 72 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 73 struct pinctrl_gpio_range *range, unsigned offset, 74 bool input) 75 { 76 unsigned int reg_addr; 77 unsigned int bit; 78 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 79 80 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 81 bit = BIT(offset & 0xf); 82 83 if (input) 84 /* Different SoC has different alignment offset. */ 85 reg_addr = CLR_ADDR(reg_addr, pctl); 86 else 87 reg_addr = SET_ADDR(reg_addr, pctl); 88 89 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 90 return 0; 91 } 92 93 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 94 { 95 unsigned int reg_addr; 96 unsigned int bit; 97 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 98 99 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; 100 bit = BIT(offset & 0xf); 101 102 if (value) 103 reg_addr = SET_ADDR(reg_addr, pctl); 104 else 105 reg_addr = CLR_ADDR(reg_addr, pctl); 106 107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 108 } 109 110 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 111 int value, enum pin_config_param arg) 112 { 113 unsigned int reg_addr, offset; 114 unsigned int bit; 115 116 /** 117 * Due to some soc are not support ies/smt config, add this special 118 * control to handle it. 119 */ 120 if (!pctl->devdata->spec_ies_smt_set && 121 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && 122 arg == PIN_CONFIG_INPUT_ENABLE) 123 return -EINVAL; 124 125 if (!pctl->devdata->spec_ies_smt_set && 126 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && 127 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 128 return -EINVAL; 129 130 /* 131 * Due to some pins are irregular, their input enable and smt 132 * control register are discontinuous, so we need this special handle. 133 */ 134 if (pctl->devdata->spec_ies_smt_set) { 135 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 136 pin, pctl->devdata->port_align, value, arg); 137 } 138 139 bit = BIT(pin & 0xf); 140 141 if (arg == PIN_CONFIG_INPUT_ENABLE) 142 offset = pctl->devdata->ies_offset; 143 else 144 offset = pctl->devdata->smt_offset; 145 146 if (value) 147 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 148 else 149 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 150 151 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 152 return 0; 153 } 154 155 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 156 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 157 unsigned int pin, unsigned char align, int value) 158 { 159 unsigned int i, reg_addr, bit; 160 161 for (i = 0; i < info_num; i++) { 162 if (pin >= ies_smt_infos[i].start && 163 pin <= ies_smt_infos[i].end) { 164 break; 165 } 166 } 167 168 if (i == info_num) 169 return -EINVAL; 170 171 if (value) 172 reg_addr = ies_smt_infos[i].offset + align; 173 else 174 reg_addr = ies_smt_infos[i].offset + (align << 1); 175 176 bit = BIT(ies_smt_infos[i].bit); 177 regmap_write(regmap, reg_addr, bit); 178 return 0; 179 } 180 181 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 182 struct mtk_pinctrl *pctl, unsigned long pin) { 183 int i; 184 185 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { 186 const struct mtk_pin_drv_grp *pin_drv = 187 pctl->devdata->pin_drv_grp + i; 188 if (pin == pin_drv->pin) 189 return pin_drv; 190 } 191 192 return NULL; 193 } 194 195 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, 196 unsigned int pin, unsigned char driving) 197 { 198 const struct mtk_pin_drv_grp *pin_drv; 199 unsigned int val; 200 unsigned int bits, mask, shift; 201 const struct mtk_drv_group_desc *drv_grp; 202 203 if (pin >= pctl->devdata->npins) 204 return -EINVAL; 205 206 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); 207 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) 208 return -EINVAL; 209 210 drv_grp = pctl->devdata->grp_desc + pin_drv->grp; 211 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv 212 && !(driving % drv_grp->step)) { 213 val = driving / drv_grp->step - 1; 214 bits = drv_grp->high_bit - drv_grp->low_bit + 1; 215 mask = BIT(bits) - 1; 216 shift = pin_drv->bit + drv_grp->low_bit; 217 mask <<= shift; 218 val <<= shift; 219 return regmap_update_bits(mtk_get_regmap(pctl, pin), 220 pin_drv->offset, mask, val); 221 } 222 223 return -EINVAL; 224 } 225 226 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 227 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, 228 unsigned int info_num, unsigned int pin, 229 unsigned char align, bool isup, unsigned int r1r0) 230 { 231 unsigned int i; 232 unsigned int reg_pupd, reg_set, reg_rst; 233 unsigned int bit_pupd, bit_r0, bit_r1; 234 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; 235 bool find = false; 236 237 for (i = 0; i < info_num; i++) { 238 if (pin == pupd_infos[i].pin) { 239 find = true; 240 break; 241 } 242 } 243 244 if (!find) 245 return -EINVAL; 246 247 spec_pupd_pin = pupd_infos + i; 248 reg_set = spec_pupd_pin->offset + align; 249 reg_rst = spec_pupd_pin->offset + (align << 1); 250 251 if (isup) 252 reg_pupd = reg_rst; 253 else 254 reg_pupd = reg_set; 255 256 bit_pupd = BIT(spec_pupd_pin->pupd_bit); 257 regmap_write(regmap, reg_pupd, bit_pupd); 258 259 bit_r0 = BIT(spec_pupd_pin->r0_bit); 260 bit_r1 = BIT(spec_pupd_pin->r1_bit); 261 262 switch (r1r0) { 263 case MTK_PUPD_SET_R1R0_00: 264 regmap_write(regmap, reg_rst, bit_r0); 265 regmap_write(regmap, reg_rst, bit_r1); 266 break; 267 case MTK_PUPD_SET_R1R0_01: 268 regmap_write(regmap, reg_set, bit_r0); 269 regmap_write(regmap, reg_rst, bit_r1); 270 break; 271 case MTK_PUPD_SET_R1R0_10: 272 regmap_write(regmap, reg_rst, bit_r0); 273 regmap_write(regmap, reg_set, bit_r1); 274 break; 275 case MTK_PUPD_SET_R1R0_11: 276 regmap_write(regmap, reg_set, bit_r0); 277 regmap_write(regmap, reg_set, bit_r1); 278 break; 279 default: 280 return -EINVAL; 281 } 282 283 return 0; 284 } 285 286 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 287 unsigned int pin, bool enable, bool isup, unsigned int arg) 288 { 289 unsigned int bit; 290 unsigned int reg_pullen, reg_pullsel; 291 int ret; 292 293 /* Some pins' pull setting are very different, 294 * they have separate pull up/down bit, R0 and R1 295 * resistor bit, so we need this special handle. 296 */ 297 if (pctl->devdata->spec_pull_set) { 298 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), 299 pin, pctl->devdata->port_align, isup, arg); 300 if (!ret) 301 return 0; 302 } 303 304 /* For generic pull config, default arg value should be 0 or 1. */ 305 if (arg != 0 && arg != 1) { 306 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", 307 arg, pin); 308 return -EINVAL; 309 } 310 311 bit = BIT(pin & 0xf); 312 if (enable) 313 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + 314 pctl->devdata->pullen_offset, pctl); 315 else 316 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + 317 pctl->devdata->pullen_offset, pctl); 318 319 if (isup) 320 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + 321 pctl->devdata->pullsel_offset, pctl); 322 else 323 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + 324 pctl->devdata->pullsel_offset, pctl); 325 326 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); 327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); 328 return 0; 329 } 330 331 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, 332 unsigned int pin, enum pin_config_param param, 333 enum pin_config_param arg) 334 { 335 int ret = 0; 336 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 337 338 switch (param) { 339 case PIN_CONFIG_BIAS_DISABLE: 340 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 341 break; 342 case PIN_CONFIG_BIAS_PULL_UP: 343 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 344 break; 345 case PIN_CONFIG_BIAS_PULL_DOWN: 346 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 347 break; 348 case PIN_CONFIG_INPUT_ENABLE: 349 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 350 break; 351 case PIN_CONFIG_OUTPUT: 352 mtk_gpio_set(pctl->chip, pin, arg); 353 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 354 break; 355 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 356 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); 357 break; 358 case PIN_CONFIG_DRIVE_STRENGTH: 359 ret = mtk_pconf_set_driving(pctl, pin, arg); 360 break; 361 default: 362 ret = -EINVAL; 363 } 364 365 return ret; 366 } 367 368 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 369 unsigned group, 370 unsigned long *config) 371 { 372 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 373 374 *config = pctl->groups[group].config; 375 376 return 0; 377 } 378 379 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 380 unsigned long *configs, unsigned num_configs) 381 { 382 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 383 struct mtk_pinctrl_group *g = &pctl->groups[group]; 384 int i, ret; 385 386 for (i = 0; i < num_configs; i++) { 387 ret = mtk_pconf_parse_conf(pctldev, g->pin, 388 pinconf_to_config_param(configs[i]), 389 pinconf_to_config_argument(configs[i])); 390 if (ret < 0) 391 return ret; 392 393 g->config = configs[i]; 394 } 395 396 return 0; 397 } 398 399 static const struct pinconf_ops mtk_pconf_ops = { 400 .pin_config_group_get = mtk_pconf_group_get, 401 .pin_config_group_set = mtk_pconf_group_set, 402 }; 403 404 static struct mtk_pinctrl_group * 405 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) 406 { 407 int i; 408 409 for (i = 0; i < pctl->ngroups; i++) { 410 struct mtk_pinctrl_group *grp = pctl->groups + i; 411 412 if (grp->pin == pin) 413 return grp; 414 } 415 416 return NULL; 417 } 418 419 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( 420 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) 421 { 422 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; 423 const struct mtk_desc_function *func = pin->functions; 424 425 while (func && func->name) { 426 if (func->muxval == fnum) 427 return func; 428 func++; 429 } 430 431 return NULL; 432 } 433 434 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, 435 u32 pin_num, u32 fnum) 436 { 437 int i; 438 439 for (i = 0; i < pctl->devdata->npins; i++) { 440 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 441 442 if (pin->pin.number == pin_num) { 443 const struct mtk_desc_function *func = 444 pin->functions; 445 446 while (func && func->name) { 447 if (func->muxval == fnum) 448 return true; 449 func++; 450 } 451 452 break; 453 } 454 } 455 456 return false; 457 } 458 459 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, 460 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, 461 struct pinctrl_map **map, unsigned *reserved_maps, 462 unsigned *num_maps) 463 { 464 bool ret; 465 466 if (*num_maps == *reserved_maps) 467 return -ENOSPC; 468 469 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 470 (*map)[*num_maps].data.mux.group = grp->name; 471 472 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); 473 if (!ret) { 474 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 475 fnum, pin); 476 return -EINVAL; 477 } 478 479 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; 480 (*num_maps)++; 481 482 return 0; 483 } 484 485 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 486 struct device_node *node, 487 struct pinctrl_map **map, 488 unsigned *reserved_maps, 489 unsigned *num_maps) 490 { 491 struct property *pins; 492 u32 pinfunc, pin, func; 493 int num_pins, num_funcs, maps_per_pin; 494 unsigned long *configs; 495 unsigned int num_configs; 496 bool has_config = 0; 497 int i, err; 498 unsigned reserve = 0; 499 struct mtk_pinctrl_group *grp; 500 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 501 502 pins = of_find_property(node, "pinmux", NULL); 503 if (!pins) { 504 dev_err(pctl->dev, "missing pins property in node %s .\n", 505 node->name); 506 return -EINVAL; 507 } 508 509 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 510 &num_configs); 511 if (num_configs) 512 has_config = 1; 513 514 num_pins = pins->length / sizeof(u32); 515 num_funcs = num_pins; 516 maps_per_pin = 0; 517 if (num_funcs) 518 maps_per_pin++; 519 if (has_config && num_pins >= 1) 520 maps_per_pin++; 521 522 if (!num_pins || !maps_per_pin) 523 return -EINVAL; 524 525 reserve = num_pins * maps_per_pin; 526 527 err = pinctrl_utils_reserve_map(pctldev, map, 528 reserved_maps, num_maps, reserve); 529 if (err < 0) 530 goto fail; 531 532 for (i = 0; i < num_pins; i++) { 533 err = of_property_read_u32_index(node, "pinmux", 534 i, &pinfunc); 535 if (err) 536 goto fail; 537 538 pin = MTK_GET_PIN_NO(pinfunc); 539 func = MTK_GET_PIN_FUNC(pinfunc); 540 541 if (pin >= pctl->devdata->npins || 542 func >= ARRAY_SIZE(mtk_gpio_functions)) { 543 dev_err(pctl->dev, "invalid pins value.\n"); 544 err = -EINVAL; 545 goto fail; 546 } 547 548 grp = mtk_pctrl_find_group_by_pin(pctl, pin); 549 if (!grp) { 550 dev_err(pctl->dev, "unable to match pin %d to group\n", 551 pin); 552 return -EINVAL; 553 } 554 555 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 556 reserved_maps, num_maps); 557 if (err < 0) 558 goto fail; 559 560 if (has_config) { 561 err = pinctrl_utils_add_map_configs(pctldev, map, 562 reserved_maps, num_maps, grp->name, 563 configs, num_configs, 564 PIN_MAP_TYPE_CONFIGS_GROUP); 565 if (err < 0) 566 goto fail; 567 } 568 } 569 570 return 0; 571 572 fail: 573 return err; 574 } 575 576 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 577 struct device_node *np_config, 578 struct pinctrl_map **map, unsigned *num_maps) 579 { 580 struct device_node *np; 581 unsigned reserved_maps; 582 int ret; 583 584 *map = NULL; 585 *num_maps = 0; 586 reserved_maps = 0; 587 588 for_each_child_of_node(np_config, np) { 589 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, 590 &reserved_maps, num_maps); 591 if (ret < 0) { 592 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 593 return ret; 594 } 595 } 596 597 return 0; 598 } 599 600 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 601 { 602 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 603 604 return pctl->ngroups; 605 } 606 607 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, 608 unsigned group) 609 { 610 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 611 612 return pctl->groups[group].name; 613 } 614 615 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 616 unsigned group, 617 const unsigned **pins, 618 unsigned *num_pins) 619 { 620 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 621 622 *pins = (unsigned *)&pctl->groups[group].pin; 623 *num_pins = 1; 624 625 return 0; 626 } 627 628 static const struct pinctrl_ops mtk_pctrl_ops = { 629 .dt_node_to_map = mtk_pctrl_dt_node_to_map, 630 .dt_free_map = pinctrl_utils_dt_free_map, 631 .get_groups_count = mtk_pctrl_get_groups_count, 632 .get_group_name = mtk_pctrl_get_group_name, 633 .get_group_pins = mtk_pctrl_get_group_pins, 634 }; 635 636 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 637 { 638 return ARRAY_SIZE(mtk_gpio_functions); 639 } 640 641 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, 642 unsigned selector) 643 { 644 return mtk_gpio_functions[selector]; 645 } 646 647 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 648 unsigned function, 649 const char * const **groups, 650 unsigned * const num_groups) 651 { 652 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 653 654 *groups = pctl->grp_names; 655 *num_groups = pctl->ngroups; 656 657 return 0; 658 } 659 660 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, 661 unsigned long pin, unsigned long mode) 662 { 663 unsigned int reg_addr; 664 unsigned char bit; 665 unsigned int val; 666 unsigned int mask = (1L << GPIO_MODE_BITS) - 1; 667 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 668 669 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) 670 + pctl->devdata->pinmux_offset; 671 672 bit = pin % MAX_GPIO_MODE_PER_REG; 673 mask <<= (GPIO_MODE_BITS * bit); 674 val = (mode << (GPIO_MODE_BITS * bit)); 675 return regmap_update_bits(mtk_get_regmap(pctl, pin), 676 reg_addr, mask, val); 677 } 678 679 static const struct mtk_desc_pin * 680 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) 681 { 682 int i; 683 const struct mtk_desc_pin *pin; 684 685 for (i = 0; i < pctl->devdata->npins; i++) { 686 pin = pctl->devdata->pins + i; 687 if (pin->eint.eintnum == eint_num) 688 return pin; 689 } 690 691 return NULL; 692 } 693 694 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, 695 unsigned function, 696 unsigned group) 697 { 698 bool ret; 699 const struct mtk_desc_function *desc; 700 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 701 struct mtk_pinctrl_group *g = pctl->groups + group; 702 703 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 704 if (!ret) { 705 dev_err(pctl->dev, "invaild function %d on group %d .\n", 706 function, group); 707 return -EINVAL; 708 } 709 710 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); 711 if (!desc) 712 return -EINVAL; 713 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); 714 return 0; 715 } 716 717 static const struct pinmux_ops mtk_pmx_ops = { 718 .get_functions_count = mtk_pmx_get_funcs_cnt, 719 .get_function_name = mtk_pmx_get_func_name, 720 .get_function_groups = mtk_pmx_get_func_groups, 721 .set_mux = mtk_pmx_set_mux, 722 .gpio_set_direction = mtk_pmx_gpio_set_direction, 723 }; 724 725 static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset) 726 { 727 return pinctrl_request_gpio(chip->base + offset); 728 } 729 730 static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset) 731 { 732 pinctrl_free_gpio(chip->base + offset); 733 } 734 735 static int mtk_gpio_direction_input(struct gpio_chip *chip, 736 unsigned offset) 737 { 738 return pinctrl_gpio_direction_input(chip->base + offset); 739 } 740 741 static int mtk_gpio_direction_output(struct gpio_chip *chip, 742 unsigned offset, int value) 743 { 744 mtk_gpio_set(chip, offset, value); 745 return pinctrl_gpio_direction_output(chip->base + offset); 746 } 747 748 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 749 { 750 unsigned int reg_addr; 751 unsigned int bit; 752 unsigned int read_val = 0; 753 754 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 755 756 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; 757 bit = BIT(offset & 0xf); 758 regmap_read(pctl->regmap1, reg_addr, &read_val); 759 return !!(read_val & bit); 760 } 761 762 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) 763 { 764 unsigned int reg_addr; 765 unsigned int bit; 766 unsigned int read_val = 0; 767 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 768 769 if (mtk_gpio_get_direction(chip, offset)) 770 reg_addr = mtk_get_port(pctl, offset) + 771 pctl->devdata->dout_offset; 772 else 773 reg_addr = mtk_get_port(pctl, offset) + 774 pctl->devdata->din_offset; 775 776 bit = BIT(offset & 0xf); 777 regmap_read(pctl->regmap1, reg_addr, &read_val); 778 return !!(read_val & bit); 779 } 780 781 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 782 { 783 const struct mtk_desc_pin *pin; 784 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 785 int irq; 786 787 pin = pctl->devdata->pins + offset; 788 if (pin->eint.eintnum == NO_EINT_SUPPORT) 789 return -EINVAL; 790 791 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); 792 if (!irq) 793 return -EINVAL; 794 795 return irq; 796 } 797 798 static int mtk_pinctrl_irq_request_resources(struct irq_data *d) 799 { 800 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 801 const struct mtk_desc_pin *pin; 802 int ret; 803 804 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 805 806 if (!pin) { 807 dev_err(pctl->dev, "Can not find pin\n"); 808 return -EINVAL; 809 } 810 811 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); 812 if (ret) { 813 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 814 irqd_to_hwirq(d)); 815 return ret; 816 } 817 818 /* set mux to INT mode */ 819 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); 820 821 return 0; 822 } 823 824 static void mtk_pinctrl_irq_release_resources(struct irq_data *d) 825 { 826 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 827 const struct mtk_desc_pin *pin; 828 829 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); 830 831 if (!pin) { 832 dev_err(pctl->dev, "Can not find pin\n"); 833 return; 834 } 835 836 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); 837 } 838 839 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, 840 unsigned int eint_num, unsigned int offset) 841 { 842 unsigned int eint_base = 0; 843 void __iomem *reg; 844 845 if (eint_num >= pctl->devdata->ap_num) 846 eint_base = pctl->devdata->ap_num; 847 848 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; 849 850 return reg; 851 } 852 853 /* 854 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not 855 * @eint_num: the EINT number to setmtk_pinctrl 856 */ 857 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, 858 unsigned int eint_num) 859 { 860 unsigned int sens; 861 unsigned int bit = BIT(eint_num % 32); 862 const struct mtk_eint_offsets *eint_offsets = 863 &pctl->devdata->eint_offsets; 864 865 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 866 eint_offsets->sens); 867 868 if (readl(reg) & bit) 869 sens = MT_LEVEL_SENSITIVE; 870 else 871 sens = MT_EDGE_SENSITIVE; 872 873 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) 874 return 1; 875 else 876 return 0; 877 } 878 879 /* 880 * mtk_eint_get_mask: To get the eint mask 881 * @eint_num: the EINT number to get 882 */ 883 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, 884 unsigned int eint_num) 885 { 886 unsigned int bit = BIT(eint_num % 32); 887 const struct mtk_eint_offsets *eint_offsets = 888 &pctl->devdata->eint_offsets; 889 890 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, 891 eint_offsets->mask); 892 893 return !!(readl(reg) & bit); 894 } 895 896 static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) 897 { 898 int start_level, curr_level; 899 unsigned int reg_offset; 900 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); 901 u32 mask = 1 << (hwirq & 0x1f); 902 u32 port = (hwirq >> 5) & eint_offsets->port_mask; 903 void __iomem *reg = pctl->eint_reg_base + (port << 2); 904 const struct mtk_desc_pin *pin; 905 906 pin = mtk_find_pin_by_eint_num(pctl, hwirq); 907 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 908 do { 909 start_level = curr_level; 910 if (start_level) 911 reg_offset = eint_offsets->pol_clr; 912 else 913 reg_offset = eint_offsets->pol_set; 914 writel(mask, reg + reg_offset); 915 916 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); 917 } while (start_level != curr_level); 918 919 return start_level; 920 } 921 922 static void mtk_eint_mask(struct irq_data *d) 923 { 924 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 925 const struct mtk_eint_offsets *eint_offsets = 926 &pctl->devdata->eint_offsets; 927 u32 mask = BIT(d->hwirq & 0x1f); 928 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 929 eint_offsets->mask_set); 930 931 writel(mask, reg); 932 } 933 934 static void mtk_eint_unmask(struct irq_data *d) 935 { 936 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 937 const struct mtk_eint_offsets *eint_offsets = 938 &pctl->devdata->eint_offsets; 939 u32 mask = BIT(d->hwirq & 0x1f); 940 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 941 eint_offsets->mask_clr); 942 943 writel(mask, reg); 944 945 if (pctl->eint_dual_edges[d->hwirq]) 946 mtk_eint_flip_edge(pctl, d->hwirq); 947 } 948 949 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, 950 unsigned debounce) 951 { 952 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); 953 int eint_num, virq, eint_offset; 954 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; 955 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256}; 956 const struct mtk_desc_pin *pin; 957 struct irq_data *d; 958 959 pin = pctl->devdata->pins + offset; 960 if (pin->eint.eintnum == NO_EINT_SUPPORT) 961 return -EINVAL; 962 963 eint_num = pin->eint.eintnum; 964 virq = irq_find_mapping(pctl->domain, eint_num); 965 eint_offset = (eint_num % 4) * 8; 966 d = irq_get_irq_data(virq); 967 968 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; 969 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; 970 if (!mtk_eint_can_en_debounce(pctl, eint_num)) 971 return -ENOSYS; 972 973 dbnc = ARRAY_SIZE(dbnc_arr); 974 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) { 975 if (debounce <= dbnc_arr[i]) { 976 dbnc = i; 977 break; 978 } 979 } 980 981 if (!mtk_eint_get_mask(pctl, eint_num)) { 982 mtk_eint_mask(d); 983 unmask = 1; 984 } else { 985 unmask = 0; 986 } 987 988 clr_bit = 0xff << eint_offset; 989 writel(clr_bit, pctl->eint_reg_base + clr_offset); 990 991 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << 992 eint_offset; 993 rst = EINT_DBNC_RST_BIT << eint_offset; 994 writel(rst | bit, pctl->eint_reg_base + set_offset); 995 996 /* Delay a while (more than 2T) to wait for hw debounce counter reset 997 work correctly */ 998 udelay(1); 999 if (unmask == 1) 1000 mtk_eint_unmask(d); 1001 1002 return 0; 1003 } 1004 1005 static struct gpio_chip mtk_gpio_chip = { 1006 .owner = THIS_MODULE, 1007 .request = mtk_gpio_request, 1008 .free = mtk_gpio_free, 1009 .direction_input = mtk_gpio_direction_input, 1010 .direction_output = mtk_gpio_direction_output, 1011 .get = mtk_gpio_get, 1012 .set = mtk_gpio_set, 1013 .to_irq = mtk_gpio_to_irq, 1014 .set_debounce = mtk_gpio_set_debounce, 1015 .of_gpio_n_cells = 2, 1016 }; 1017 1018 static int mtk_eint_set_type(struct irq_data *d, 1019 unsigned int type) 1020 { 1021 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1022 const struct mtk_eint_offsets *eint_offsets = 1023 &pctl->devdata->eint_offsets; 1024 u32 mask = BIT(d->hwirq & 0x1f); 1025 void __iomem *reg; 1026 1027 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || 1028 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { 1029 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", 1030 d->irq, d->hwirq, type); 1031 return -EINVAL; 1032 } 1033 1034 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1035 pctl->eint_dual_edges[d->hwirq] = 1; 1036 else 1037 pctl->eint_dual_edges[d->hwirq] = 0; 1038 1039 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { 1040 reg = mtk_eint_get_offset(pctl, d->hwirq, 1041 eint_offsets->pol_clr); 1042 writel(mask, reg); 1043 } else { 1044 reg = mtk_eint_get_offset(pctl, d->hwirq, 1045 eint_offsets->pol_set); 1046 writel(mask, reg); 1047 } 1048 1049 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 1050 reg = mtk_eint_get_offset(pctl, d->hwirq, 1051 eint_offsets->sens_clr); 1052 writel(mask, reg); 1053 } else { 1054 reg = mtk_eint_get_offset(pctl, d->hwirq, 1055 eint_offsets->sens_set); 1056 writel(mask, reg); 1057 } 1058 1059 if (pctl->eint_dual_edges[d->hwirq]) 1060 mtk_eint_flip_edge(pctl, d->hwirq); 1061 1062 return 0; 1063 } 1064 1065 static void mtk_eint_ack(struct irq_data *d) 1066 { 1067 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1068 const struct mtk_eint_offsets *eint_offsets = 1069 &pctl->devdata->eint_offsets; 1070 u32 mask = BIT(d->hwirq & 0x1f); 1071 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, 1072 eint_offsets->ack); 1073 1074 writel(mask, reg); 1075 } 1076 1077 static struct irq_chip mtk_pinctrl_irq_chip = { 1078 .name = "mt-eint", 1079 .irq_mask = mtk_eint_mask, 1080 .irq_unmask = mtk_eint_unmask, 1081 .irq_ack = mtk_eint_ack, 1082 .irq_set_type = mtk_eint_set_type, 1083 .irq_request_resources = mtk_pinctrl_irq_request_resources, 1084 .irq_release_resources = mtk_pinctrl_irq_release_resources, 1085 }; 1086 1087 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) 1088 { 1089 const struct mtk_eint_offsets *eint_offsets = 1090 &pctl->devdata->eint_offsets; 1091 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; 1092 unsigned int i; 1093 1094 for (i = 0; i < pctl->devdata->ap_num; i += 32) { 1095 writel(0xffffffff, reg); 1096 reg += 4; 1097 } 1098 return 0; 1099 } 1100 1101 static inline void 1102 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) 1103 { 1104 unsigned int rst, ctrl_offset; 1105 unsigned int bit, dbnc; 1106 const struct mtk_eint_offsets *eint_offsets = 1107 &pctl->devdata->eint_offsets; 1108 1109 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; 1110 dbnc = readl(pctl->eint_reg_base + ctrl_offset); 1111 bit = EINT_DBNC_SET_EN << ((index % 4) * 8); 1112 if ((bit & dbnc) > 0) { 1113 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; 1114 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); 1115 writel(rst, pctl->eint_reg_base + ctrl_offset); 1116 } 1117 } 1118 1119 static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) 1120 { 1121 struct irq_chip *chip = irq_get_chip(irq); 1122 struct mtk_pinctrl *pctl = irq_get_handler_data(irq); 1123 unsigned int status, eint_num; 1124 int offset, index, virq; 1125 const struct mtk_eint_offsets *eint_offsets = 1126 &pctl->devdata->eint_offsets; 1127 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); 1128 int dual_edges, start_level, curr_level; 1129 const struct mtk_desc_pin *pin; 1130 1131 chained_irq_enter(chip, desc); 1132 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) { 1133 status = readl(reg); 1134 reg += 4; 1135 while (status) { 1136 offset = __ffs(status); 1137 index = eint_num + offset; 1138 virq = irq_find_mapping(pctl->domain, index); 1139 status &= ~BIT(offset); 1140 1141 dual_edges = pctl->eint_dual_edges[index]; 1142 if (dual_edges) { 1143 /* Clear soft-irq in case we raised it 1144 last time */ 1145 writel(BIT(offset), reg - eint_offsets->stat + 1146 eint_offsets->soft_clr); 1147 1148 pin = mtk_find_pin_by_eint_num(pctl, index); 1149 start_level = mtk_gpio_get(pctl->chip, 1150 pin->pin.number); 1151 } 1152 1153 generic_handle_irq(virq); 1154 1155 if (dual_edges) { 1156 curr_level = mtk_eint_flip_edge(pctl, index); 1157 1158 /* If level changed, we might lost one edge 1159 interrupt, raised it through soft-irq */ 1160 if (start_level != curr_level) 1161 writel(BIT(offset), reg - 1162 eint_offsets->stat + 1163 eint_offsets->soft_set); 1164 } 1165 1166 if (index < pctl->devdata->db_cnt) 1167 mtk_eint_debounce_process(pctl , index); 1168 } 1169 } 1170 chained_irq_exit(chip, desc); 1171 } 1172 1173 static int mtk_pctrl_build_state(struct platform_device *pdev) 1174 { 1175 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); 1176 int i; 1177 1178 pctl->ngroups = pctl->devdata->npins; 1179 1180 /* Allocate groups */ 1181 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1182 sizeof(*pctl->groups), GFP_KERNEL); 1183 if (!pctl->groups) 1184 return -ENOMEM; 1185 1186 /* We assume that one pin is one group, use pin name as group name. */ 1187 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1188 sizeof(*pctl->grp_names), GFP_KERNEL); 1189 if (!pctl->grp_names) 1190 return -ENOMEM; 1191 1192 for (i = 0; i < pctl->devdata->npins; i++) { 1193 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; 1194 struct mtk_pinctrl_group *group = pctl->groups + i; 1195 1196 group->name = pin->pin.name; 1197 group->pin = pin->pin.number; 1198 1199 pctl->grp_names[i] = pin->pin.name; 1200 } 1201 1202 return 0; 1203 } 1204 1205 static struct pinctrl_desc mtk_pctrl_desc = { 1206 .confops = &mtk_pconf_ops, 1207 .pctlops = &mtk_pctrl_ops, 1208 .pmxops = &mtk_pmx_ops, 1209 }; 1210 1211 int mtk_pctrl_init(struct platform_device *pdev, 1212 const struct mtk_pinctrl_devdata *data, 1213 struct regmap *regmap) 1214 { 1215 struct pinctrl_pin_desc *pins; 1216 struct mtk_pinctrl *pctl; 1217 struct device_node *np = pdev->dev.of_node, *node; 1218 struct property *prop; 1219 struct resource *res; 1220 int i, ret, irq; 1221 1222 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1223 if (!pctl) 1224 return -ENOMEM; 1225 1226 platform_set_drvdata(pdev, pctl); 1227 1228 prop = of_find_property(np, "pins-are-numbered", NULL); 1229 if (!prop) { 1230 dev_err(&pdev->dev, "only support pins-are-numbered format\n"); 1231 return -EINVAL; 1232 } 1233 1234 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); 1235 if (node) { 1236 pctl->regmap1 = syscon_node_to_regmap(node); 1237 if (IS_ERR(pctl->regmap1)) 1238 return PTR_ERR(pctl->regmap1); 1239 } else if (regmap) { 1240 pctl->regmap1 = regmap; 1241 } else { 1242 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); 1243 return -EINVAL; 1244 } 1245 1246 /* Only 8135 has two base addr, other SoCs have only one. */ 1247 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); 1248 if (node) { 1249 pctl->regmap2 = syscon_node_to_regmap(node); 1250 if (IS_ERR(pctl->regmap2)) 1251 return PTR_ERR(pctl->regmap2); 1252 } 1253 1254 pctl->devdata = data; 1255 ret = mtk_pctrl_build_state(pdev); 1256 if (ret) { 1257 dev_err(&pdev->dev, "build state failed: %d\n", ret); 1258 return -EINVAL; 1259 } 1260 1261 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), 1262 GFP_KERNEL); 1263 if (!pins) 1264 return -ENOMEM; 1265 1266 for (i = 0; i < pctl->devdata->npins; i++) 1267 pins[i] = pctl->devdata->pins[i].pin; 1268 mtk_pctrl_desc.name = dev_name(&pdev->dev); 1269 mtk_pctrl_desc.owner = THIS_MODULE; 1270 mtk_pctrl_desc.pins = pins; 1271 mtk_pctrl_desc.npins = pctl->devdata->npins; 1272 pctl->dev = &pdev->dev; 1273 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); 1274 if (IS_ERR(pctl->pctl_dev)) { 1275 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1276 return PTR_ERR(pctl->pctl_dev); 1277 } 1278 1279 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1280 if (!pctl->chip) { 1281 ret = -ENOMEM; 1282 goto pctrl_error; 1283 } 1284 1285 *pctl->chip = mtk_gpio_chip; 1286 pctl->chip->ngpio = pctl->devdata->npins; 1287 pctl->chip->label = dev_name(&pdev->dev); 1288 pctl->chip->dev = &pdev->dev; 1289 pctl->chip->base = -1; 1290 1291 ret = gpiochip_add(pctl->chip); 1292 if (ret) { 1293 ret = -EINVAL; 1294 goto pctrl_error; 1295 } 1296 1297 /* Register the GPIO to pin mappings. */ 1298 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1299 0, 0, pctl->devdata->npins); 1300 if (ret) { 1301 ret = -EINVAL; 1302 goto chip_error; 1303 } 1304 1305 if (!of_property_read_bool(np, "interrupt-controller")) 1306 return 0; 1307 1308 /* Get EINT register base from dts. */ 1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1310 if (!res) { 1311 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); 1312 ret = -EINVAL; 1313 goto chip_error; 1314 } 1315 1316 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); 1317 if (IS_ERR(pctl->eint_reg_base)) { 1318 ret = -EINVAL; 1319 goto chip_error; 1320 } 1321 1322 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, 1323 sizeof(int), GFP_KERNEL); 1324 if (!pctl->eint_dual_edges) { 1325 ret = -ENOMEM; 1326 goto chip_error; 1327 } 1328 1329 irq = irq_of_parse_and_map(np, 0); 1330 if (!irq) { 1331 dev_err(&pdev->dev, "couldn't parse and map irq\n"); 1332 ret = -EINVAL; 1333 goto chip_error; 1334 } 1335 1336 pctl->domain = irq_domain_add_linear(np, 1337 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); 1338 if (!pctl->domain) { 1339 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1340 ret = -ENOMEM; 1341 goto chip_error; 1342 } 1343 1344 mtk_eint_init(pctl); 1345 for (i = 0; i < pctl->devdata->ap_num; i++) { 1346 int virq = irq_create_mapping(pctl->domain, i); 1347 1348 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, 1349 handle_level_irq); 1350 irq_set_chip_data(virq, pctl); 1351 set_irq_flags(virq, IRQF_VALID); 1352 }; 1353 1354 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); 1355 set_irq_flags(irq, IRQF_VALID); 1356 return 0; 1357 1358 chip_error: 1359 gpiochip_remove(pctl->chip); 1360 pctrl_error: 1361 pinctrl_unregister(pctl->pctl_dev); 1362 return ret; 1363 } 1364 1365 MODULE_LICENSE("GPL"); 1366 MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); 1367 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); 1368