1 /*
2  * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/io.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
31 #include <linux/regmap.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/pm.h>
36 #include <dt-bindings/pinctrl/mt65xx.h>
37 
38 #include "../core.h"
39 #include "../pinconf.h"
40 #include "../pinctrl-utils.h"
41 #include "mtk-eint.h"
42 #include "pinctrl-mtk-common.h"
43 
44 #define MAX_GPIO_MODE_PER_REG 5
45 #define GPIO_MODE_BITS        3
46 #define GPIO_MODE_PREFIX "GPIO"
47 
48 static const char * const mtk_gpio_functions[] = {
49 	"func0", "func1", "func2", "func3",
50 	"func4", "func5", "func6", "func7",
51 	"func8", "func9", "func10", "func11",
52 	"func12", "func13", "func14", "func15",
53 };
54 
55 /*
56  * There are two base address for pull related configuration
57  * in mt8135, and different GPIO pins use different base address.
58  * When pin number greater than type1_start and less than type1_end,
59  * should use the second base address.
60  */
61 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
62 		unsigned long pin)
63 {
64 	if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
65 		return pctl->regmap2;
66 	return pctl->regmap1;
67 }
68 
69 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
70 {
71 	/* Different SoC has different mask and port shift. */
72 	return ((pin >> 4) & pctl->devdata->port_mask)
73 			<< pctl->devdata->port_shf;
74 }
75 
76 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
77 			struct pinctrl_gpio_range *range, unsigned offset,
78 			bool input)
79 {
80 	unsigned int reg_addr;
81 	unsigned int bit;
82 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
83 
84 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
85 	bit = BIT(offset & 0xf);
86 
87 	if (pctl->devdata->spec_dir_set)
88 		pctl->devdata->spec_dir_set(&reg_addr, offset);
89 
90 	if (input)
91 		/* Different SoC has different alignment offset. */
92 		reg_addr = CLR_ADDR(reg_addr, pctl);
93 	else
94 		reg_addr = SET_ADDR(reg_addr, pctl);
95 
96 	regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
97 	return 0;
98 }
99 
100 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
101 {
102 	unsigned int reg_addr;
103 	unsigned int bit;
104 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
105 
106 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
107 	bit = BIT(offset & 0xf);
108 
109 	if (value)
110 		reg_addr = SET_ADDR(reg_addr, pctl);
111 	else
112 		reg_addr = CLR_ADDR(reg_addr, pctl);
113 
114 	regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
115 }
116 
117 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
118 		int value, enum pin_config_param arg)
119 {
120 	unsigned int reg_addr, offset;
121 	unsigned int bit;
122 
123 	/**
124 	 * Due to some soc are not support ies/smt config, add this special
125 	 * control to handle it.
126 	 */
127 	if (!pctl->devdata->spec_ies_smt_set &&
128 		pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
129 			arg == PIN_CONFIG_INPUT_ENABLE)
130 		return -EINVAL;
131 
132 	if (!pctl->devdata->spec_ies_smt_set &&
133 		pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
134 			arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
135 		return -EINVAL;
136 
137 	/*
138 	 * Due to some pins are irregular, their input enable and smt
139 	 * control register are discontinuous, so we need this special handle.
140 	 */
141 	if (pctl->devdata->spec_ies_smt_set) {
142 		return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
143 			pin, pctl->devdata->port_align, value, arg);
144 	}
145 
146 	bit = BIT(pin & 0xf);
147 
148 	if (arg == PIN_CONFIG_INPUT_ENABLE)
149 		offset = pctl->devdata->ies_offset;
150 	else
151 		offset = pctl->devdata->smt_offset;
152 
153 	if (value)
154 		reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
155 	else
156 		reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
157 
158 	regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
159 	return 0;
160 }
161 
162 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
163 		const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
164 		unsigned int pin, unsigned char align, int value)
165 {
166 	unsigned int i, reg_addr, bit;
167 
168 	for (i = 0; i < info_num; i++) {
169 		if (pin >= ies_smt_infos[i].start &&
170 				pin <= ies_smt_infos[i].end) {
171 			break;
172 		}
173 	}
174 
175 	if (i == info_num)
176 		return -EINVAL;
177 
178 	if (value)
179 		reg_addr = ies_smt_infos[i].offset + align;
180 	else
181 		reg_addr = ies_smt_infos[i].offset + (align << 1);
182 
183 	bit = BIT(ies_smt_infos[i].bit);
184 	regmap_write(regmap, reg_addr, bit);
185 	return 0;
186 }
187 
188 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
189 		struct mtk_pinctrl *pctl,  unsigned long pin) {
190 	int i;
191 
192 	for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
193 		const struct mtk_pin_drv_grp *pin_drv =
194 				pctl->devdata->pin_drv_grp + i;
195 		if (pin == pin_drv->pin)
196 			return pin_drv;
197 	}
198 
199 	return NULL;
200 }
201 
202 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
203 		unsigned int pin, unsigned char driving)
204 {
205 	const struct mtk_pin_drv_grp *pin_drv;
206 	unsigned int val;
207 	unsigned int bits, mask, shift;
208 	const struct mtk_drv_group_desc *drv_grp;
209 
210 	if (pin >= pctl->devdata->npins)
211 		return -EINVAL;
212 
213 	pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
214 	if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
215 		return -EINVAL;
216 
217 	drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
218 	if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
219 		&& !(driving % drv_grp->step)) {
220 		val = driving / drv_grp->step - 1;
221 		bits = drv_grp->high_bit - drv_grp->low_bit + 1;
222 		mask = BIT(bits) - 1;
223 		shift = pin_drv->bit + drv_grp->low_bit;
224 		mask <<= shift;
225 		val <<= shift;
226 		return regmap_update_bits(mtk_get_regmap(pctl, pin),
227 				pin_drv->offset, mask, val);
228 	}
229 
230 	return -EINVAL;
231 }
232 
233 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
234 		const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
235 		unsigned int info_num, unsigned int pin,
236 		unsigned char align, bool isup, unsigned int r1r0)
237 {
238 	unsigned int i;
239 	unsigned int reg_pupd, reg_set, reg_rst;
240 	unsigned int bit_pupd, bit_r0, bit_r1;
241 	const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
242 	bool find = false;
243 
244 	for (i = 0; i < info_num; i++) {
245 		if (pin == pupd_infos[i].pin) {
246 			find = true;
247 			break;
248 		}
249 	}
250 
251 	if (!find)
252 		return -EINVAL;
253 
254 	spec_pupd_pin = pupd_infos + i;
255 	reg_set = spec_pupd_pin->offset + align;
256 	reg_rst = spec_pupd_pin->offset + (align << 1);
257 
258 	if (isup)
259 		reg_pupd = reg_rst;
260 	else
261 		reg_pupd = reg_set;
262 
263 	bit_pupd = BIT(spec_pupd_pin->pupd_bit);
264 	regmap_write(regmap, reg_pupd, bit_pupd);
265 
266 	bit_r0 = BIT(spec_pupd_pin->r0_bit);
267 	bit_r1 = BIT(spec_pupd_pin->r1_bit);
268 
269 	switch (r1r0) {
270 	case MTK_PUPD_SET_R1R0_00:
271 		regmap_write(regmap, reg_rst, bit_r0);
272 		regmap_write(regmap, reg_rst, bit_r1);
273 		break;
274 	case MTK_PUPD_SET_R1R0_01:
275 		regmap_write(regmap, reg_set, bit_r0);
276 		regmap_write(regmap, reg_rst, bit_r1);
277 		break;
278 	case MTK_PUPD_SET_R1R0_10:
279 		regmap_write(regmap, reg_rst, bit_r0);
280 		regmap_write(regmap, reg_set, bit_r1);
281 		break;
282 	case MTK_PUPD_SET_R1R0_11:
283 		regmap_write(regmap, reg_set, bit_r0);
284 		regmap_write(regmap, reg_set, bit_r1);
285 		break;
286 	default:
287 		return -EINVAL;
288 	}
289 
290 	return 0;
291 }
292 
293 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
294 		unsigned int pin, bool enable, bool isup, unsigned int arg)
295 {
296 	unsigned int bit;
297 	unsigned int reg_pullen, reg_pullsel, r1r0;
298 	int ret;
299 
300 	/* Some pins' pull setting are very different,
301 	 * they have separate pull up/down bit, R0 and R1
302 	 * resistor bit, so we need this special handle.
303 	 */
304 	if (pctl->devdata->spec_pull_set) {
305 		/* For special pins, bias-disable is set by R1R0,
306 		 * the parameter should be "MTK_PUPD_SET_R1R0_00".
307 		 */
308 		r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
309 		ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
310 			pin, pctl->devdata->port_align, isup, r1r0);
311 		if (!ret)
312 			return 0;
313 	}
314 
315 	/* For generic pull config, default arg value should be 0 or 1. */
316 	if (arg != 0 && arg != 1) {
317 		dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
318 			arg, pin);
319 		return -EINVAL;
320 	}
321 
322 	bit = BIT(pin & 0xf);
323 	if (enable)
324 		reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
325 			pctl->devdata->pullen_offset, pctl);
326 	else
327 		reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
328 			pctl->devdata->pullen_offset, pctl);
329 
330 	if (isup)
331 		reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
332 			pctl->devdata->pullsel_offset, pctl);
333 	else
334 		reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
335 			pctl->devdata->pullsel_offset, pctl);
336 
337 	regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
338 	regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
339 	return 0;
340 }
341 
342 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
343 		unsigned int pin, enum pin_config_param param,
344 		enum pin_config_param arg)
345 {
346 	int ret = 0;
347 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
348 
349 	switch (param) {
350 	case PIN_CONFIG_BIAS_DISABLE:
351 		ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
352 		break;
353 	case PIN_CONFIG_BIAS_PULL_UP:
354 		ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
355 		break;
356 	case PIN_CONFIG_BIAS_PULL_DOWN:
357 		ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
358 		break;
359 	case PIN_CONFIG_INPUT_ENABLE:
360 		mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
361 		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
362 		break;
363 	case PIN_CONFIG_OUTPUT:
364 		mtk_gpio_set(pctl->chip, pin, arg);
365 		ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
366 		break;
367 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
368 		mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
369 		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
370 		break;
371 	case PIN_CONFIG_DRIVE_STRENGTH:
372 		ret = mtk_pconf_set_driving(pctl, pin, arg);
373 		break;
374 	default:
375 		ret = -EINVAL;
376 	}
377 
378 	return ret;
379 }
380 
381 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
382 				 unsigned group,
383 				 unsigned long *config)
384 {
385 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
386 
387 	*config = pctl->groups[group].config;
388 
389 	return 0;
390 }
391 
392 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
393 				 unsigned long *configs, unsigned num_configs)
394 {
395 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
396 	struct mtk_pinctrl_group *g = &pctl->groups[group];
397 	int i, ret;
398 
399 	for (i = 0; i < num_configs; i++) {
400 		ret = mtk_pconf_parse_conf(pctldev, g->pin,
401 			pinconf_to_config_param(configs[i]),
402 			pinconf_to_config_argument(configs[i]));
403 		if (ret < 0)
404 			return ret;
405 
406 		g->config = configs[i];
407 	}
408 
409 	return 0;
410 }
411 
412 static const struct pinconf_ops mtk_pconf_ops = {
413 	.pin_config_group_get	= mtk_pconf_group_get,
414 	.pin_config_group_set	= mtk_pconf_group_set,
415 };
416 
417 static struct mtk_pinctrl_group *
418 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
419 {
420 	int i;
421 
422 	for (i = 0; i < pctl->ngroups; i++) {
423 		struct mtk_pinctrl_group *grp = pctl->groups + i;
424 
425 		if (grp->pin == pin)
426 			return grp;
427 	}
428 
429 	return NULL;
430 }
431 
432 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
433 		struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
434 {
435 	const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
436 	const struct mtk_desc_function *func = pin->functions;
437 
438 	while (func && func->name) {
439 		if (func->muxval == fnum)
440 			return func;
441 		func++;
442 	}
443 
444 	return NULL;
445 }
446 
447 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
448 		u32 pin_num, u32 fnum)
449 {
450 	int i;
451 
452 	for (i = 0; i < pctl->devdata->npins; i++) {
453 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
454 
455 		if (pin->pin.number == pin_num) {
456 			const struct mtk_desc_function *func =
457 					pin->functions;
458 
459 			while (func && func->name) {
460 				if (func->muxval == fnum)
461 					return true;
462 				func++;
463 			}
464 
465 			break;
466 		}
467 	}
468 
469 	return false;
470 }
471 
472 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
473 		u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
474 		struct pinctrl_map **map, unsigned *reserved_maps,
475 		unsigned *num_maps)
476 {
477 	bool ret;
478 
479 	if (*num_maps == *reserved_maps)
480 		return -ENOSPC;
481 
482 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
483 	(*map)[*num_maps].data.mux.group = grp->name;
484 
485 	ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
486 	if (!ret) {
487 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",
488 				fnum, pin);
489 		return -EINVAL;
490 	}
491 
492 	(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
493 	(*num_maps)++;
494 
495 	return 0;
496 }
497 
498 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
499 				      struct device_node *node,
500 				      struct pinctrl_map **map,
501 				      unsigned *reserved_maps,
502 				      unsigned *num_maps)
503 {
504 	struct property *pins;
505 	u32 pinfunc, pin, func;
506 	int num_pins, num_funcs, maps_per_pin;
507 	unsigned long *configs;
508 	unsigned int num_configs;
509 	bool has_config = false;
510 	int i, err;
511 	unsigned reserve = 0;
512 	struct mtk_pinctrl_group *grp;
513 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
514 
515 	pins = of_find_property(node, "pinmux", NULL);
516 	if (!pins) {
517 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
518 				node);
519 		return -EINVAL;
520 	}
521 
522 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
523 		&num_configs);
524 	if (err)
525 		return err;
526 
527 	if (num_configs)
528 		has_config = true;
529 
530 	num_pins = pins->length / sizeof(u32);
531 	num_funcs = num_pins;
532 	maps_per_pin = 0;
533 	if (num_funcs)
534 		maps_per_pin++;
535 	if (has_config && num_pins >= 1)
536 		maps_per_pin++;
537 
538 	if (!num_pins || !maps_per_pin) {
539 		err = -EINVAL;
540 		goto exit;
541 	}
542 
543 	reserve = num_pins * maps_per_pin;
544 
545 	err = pinctrl_utils_reserve_map(pctldev, map,
546 			reserved_maps, num_maps, reserve);
547 	if (err < 0)
548 		goto exit;
549 
550 	for (i = 0; i < num_pins; i++) {
551 		err = of_property_read_u32_index(node, "pinmux",
552 				i, &pinfunc);
553 		if (err)
554 			goto exit;
555 
556 		pin = MTK_GET_PIN_NO(pinfunc);
557 		func = MTK_GET_PIN_FUNC(pinfunc);
558 
559 		if (pin >= pctl->devdata->npins ||
560 				func >= ARRAY_SIZE(mtk_gpio_functions)) {
561 			dev_err(pctl->dev, "invalid pins value.\n");
562 			err = -EINVAL;
563 			goto exit;
564 		}
565 
566 		grp = mtk_pctrl_find_group_by_pin(pctl, pin);
567 		if (!grp) {
568 			dev_err(pctl->dev, "unable to match pin %d to group\n",
569 					pin);
570 			err = -EINVAL;
571 			goto exit;
572 		}
573 
574 		err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
575 				reserved_maps, num_maps);
576 		if (err < 0)
577 			goto exit;
578 
579 		if (has_config) {
580 			err = pinctrl_utils_add_map_configs(pctldev, map,
581 					reserved_maps, num_maps, grp->name,
582 					configs, num_configs,
583 					PIN_MAP_TYPE_CONFIGS_GROUP);
584 			if (err < 0)
585 				goto exit;
586 		}
587 	}
588 
589 	err = 0;
590 
591 exit:
592 	kfree(configs);
593 	return err;
594 }
595 
596 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
597 				 struct device_node *np_config,
598 				 struct pinctrl_map **map, unsigned *num_maps)
599 {
600 	struct device_node *np;
601 	unsigned reserved_maps;
602 	int ret;
603 
604 	*map = NULL;
605 	*num_maps = 0;
606 	reserved_maps = 0;
607 
608 	for_each_child_of_node(np_config, np) {
609 		ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
610 				&reserved_maps, num_maps);
611 		if (ret < 0) {
612 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
613 			of_node_put(np);
614 			return ret;
615 		}
616 	}
617 
618 	return 0;
619 }
620 
621 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
622 {
623 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
624 
625 	return pctl->ngroups;
626 }
627 
628 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
629 					      unsigned group)
630 {
631 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
632 
633 	return pctl->groups[group].name;
634 }
635 
636 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
637 				      unsigned group,
638 				      const unsigned **pins,
639 				      unsigned *num_pins)
640 {
641 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
642 
643 	*pins = (unsigned *)&pctl->groups[group].pin;
644 	*num_pins = 1;
645 
646 	return 0;
647 }
648 
649 static const struct pinctrl_ops mtk_pctrl_ops = {
650 	.dt_node_to_map		= mtk_pctrl_dt_node_to_map,
651 	.dt_free_map		= pinctrl_utils_free_map,
652 	.get_groups_count	= mtk_pctrl_get_groups_count,
653 	.get_group_name		= mtk_pctrl_get_group_name,
654 	.get_group_pins		= mtk_pctrl_get_group_pins,
655 };
656 
657 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
658 {
659 	return ARRAY_SIZE(mtk_gpio_functions);
660 }
661 
662 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
663 					   unsigned selector)
664 {
665 	return mtk_gpio_functions[selector];
666 }
667 
668 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
669 				     unsigned function,
670 				     const char * const **groups,
671 				     unsigned * const num_groups)
672 {
673 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
674 
675 	*groups = pctl->grp_names;
676 	*num_groups = pctl->ngroups;
677 
678 	return 0;
679 }
680 
681 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
682 		unsigned long pin, unsigned long mode)
683 {
684 	unsigned int reg_addr;
685 	unsigned char bit;
686 	unsigned int val;
687 	unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
688 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
689 
690 	if (pctl->devdata->spec_pinmux_set)
691 		pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
692 					pin, mode);
693 
694 	reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
695 			+ pctl->devdata->pinmux_offset;
696 
697 	mode &= mask;
698 	bit = pin % MAX_GPIO_MODE_PER_REG;
699 	mask <<= (GPIO_MODE_BITS * bit);
700 	val = (mode << (GPIO_MODE_BITS * bit));
701 	return regmap_update_bits(mtk_get_regmap(pctl, pin),
702 			reg_addr, mask, val);
703 }
704 
705 static const struct mtk_desc_pin *
706 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
707 {
708 	int i;
709 	const struct mtk_desc_pin *pin;
710 
711 	for (i = 0; i < pctl->devdata->npins; i++) {
712 		pin = pctl->devdata->pins + i;
713 		if (pin->eint.eintnum == eint_num)
714 			return pin;
715 	}
716 
717 	return NULL;
718 }
719 
720 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
721 			    unsigned function,
722 			    unsigned group)
723 {
724 	bool ret;
725 	const struct mtk_desc_function *desc;
726 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
727 	struct mtk_pinctrl_group *g = pctl->groups + group;
728 
729 	ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
730 	if (!ret) {
731 		dev_err(pctl->dev, "invalid function %d on group %d .\n",
732 				function, group);
733 		return -EINVAL;
734 	}
735 
736 	desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
737 	if (!desc)
738 		return -EINVAL;
739 	mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
740 	return 0;
741 }
742 
743 static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
744 				unsigned offset)
745 {
746 	const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
747 	const struct mtk_desc_function *func = pin->functions;
748 
749 	while (func && func->name) {
750 		if (!strncmp(func->name, GPIO_MODE_PREFIX,
751 			sizeof(GPIO_MODE_PREFIX)-1))
752 			return func->muxval;
753 		func++;
754 	}
755 	return -EINVAL;
756 }
757 
758 static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
759 				    struct pinctrl_gpio_range *range,
760 				    unsigned offset)
761 {
762 	int muxval;
763 	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
764 
765 	muxval = mtk_pmx_find_gpio_mode(pctl, offset);
766 
767 	if (muxval < 0) {
768 		dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
769 		return -EINVAL;
770 	}
771 
772 	mtk_pmx_set_mode(pctldev, offset, muxval);
773 	mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
774 
775 	return 0;
776 }
777 
778 static const struct pinmux_ops mtk_pmx_ops = {
779 	.get_functions_count	= mtk_pmx_get_funcs_cnt,
780 	.get_function_name	= mtk_pmx_get_func_name,
781 	.get_function_groups	= mtk_pmx_get_func_groups,
782 	.set_mux		= mtk_pmx_set_mux,
783 	.gpio_set_direction	= mtk_pmx_gpio_set_direction,
784 	.gpio_request_enable	= mtk_pmx_gpio_request_enable,
785 };
786 
787 static int mtk_gpio_direction_input(struct gpio_chip *chip,
788 					unsigned offset)
789 {
790 	return pinctrl_gpio_direction_input(chip->base + offset);
791 }
792 
793 static int mtk_gpio_direction_output(struct gpio_chip *chip,
794 					unsigned offset, int value)
795 {
796 	mtk_gpio_set(chip, offset, value);
797 	return pinctrl_gpio_direction_output(chip->base + offset);
798 }
799 
800 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
801 {
802 	unsigned int reg_addr;
803 	unsigned int bit;
804 	unsigned int read_val = 0;
805 
806 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
807 
808 	reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
809 	bit = BIT(offset & 0xf);
810 
811 	if (pctl->devdata->spec_dir_set)
812 		pctl->devdata->spec_dir_set(&reg_addr, offset);
813 
814 	regmap_read(pctl->regmap1, reg_addr, &read_val);
815 	return !(read_val & bit);
816 }
817 
818 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
819 {
820 	unsigned int reg_addr;
821 	unsigned int bit;
822 	unsigned int read_val = 0;
823 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
824 
825 	reg_addr = mtk_get_port(pctl, offset) +
826 		pctl->devdata->din_offset;
827 
828 	bit = BIT(offset & 0xf);
829 	regmap_read(pctl->regmap1, reg_addr, &read_val);
830 	return !!(read_val & bit);
831 }
832 
833 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
834 {
835 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
836 	const struct mtk_desc_pin *pin;
837 	unsigned long eint_n;
838 
839 	pin = pctl->devdata->pins + offset;
840 	if (pin->eint.eintnum == NO_EINT_SUPPORT)
841 		return -EINVAL;
842 
843 	eint_n = pin->eint.eintnum;
844 
845 	return mtk_eint_find_irq(pctl->eint, eint_n);
846 }
847 
848 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
849 			       unsigned long config)
850 {
851 	struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
852 	const struct mtk_desc_pin *pin;
853 	unsigned long eint_n;
854 	u32 debounce;
855 
856 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
857 		return -ENOTSUPP;
858 
859 	pin = pctl->devdata->pins + offset;
860 	if (pin->eint.eintnum == NO_EINT_SUPPORT)
861 		return -EINVAL;
862 
863 	debounce = pinconf_to_config_argument(config);
864 	eint_n = pin->eint.eintnum;
865 
866 	return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
867 }
868 
869 static const struct gpio_chip mtk_gpio_chip = {
870 	.owner			= THIS_MODULE,
871 	.request		= gpiochip_generic_request,
872 	.free			= gpiochip_generic_free,
873 	.get_direction		= mtk_gpio_get_direction,
874 	.direction_input	= mtk_gpio_direction_input,
875 	.direction_output	= mtk_gpio_direction_output,
876 	.get			= mtk_gpio_get,
877 	.set			= mtk_gpio_set,
878 	.to_irq			= mtk_gpio_to_irq,
879 	.set_config		= mtk_gpio_set_config,
880 	.of_gpio_n_cells	= 2,
881 };
882 
883 static int mtk_eint_suspend(struct device *device)
884 {
885 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
886 
887 	return mtk_eint_do_suspend(pctl->eint);
888 }
889 
890 static int mtk_eint_resume(struct device *device)
891 {
892 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
893 
894 	return mtk_eint_do_resume(pctl->eint);
895 }
896 
897 const struct dev_pm_ops mtk_eint_pm_ops = {
898 	.suspend_noirq = mtk_eint_suspend,
899 	.resume_noirq = mtk_eint_resume,
900 };
901 
902 static int mtk_pctrl_build_state(struct platform_device *pdev)
903 {
904 	struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
905 	int i;
906 
907 	pctl->ngroups = pctl->devdata->npins;
908 
909 	/* Allocate groups */
910 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
911 				    sizeof(*pctl->groups), GFP_KERNEL);
912 	if (!pctl->groups)
913 		return -ENOMEM;
914 
915 	/* We assume that one pin is one group, use pin name as group name. */
916 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
917 				       sizeof(*pctl->grp_names), GFP_KERNEL);
918 	if (!pctl->grp_names)
919 		return -ENOMEM;
920 
921 	for (i = 0; i < pctl->devdata->npins; i++) {
922 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
923 		struct mtk_pinctrl_group *group = pctl->groups + i;
924 
925 		group->name = pin->pin.name;
926 		group->pin = pin->pin.number;
927 
928 		pctl->grp_names[i] = pin->pin.name;
929 	}
930 
931 	return 0;
932 }
933 
934 static int
935 mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
936 		  struct gpio_chip **gpio_chip)
937 {
938 	struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
939 	const struct mtk_desc_pin *pin;
940 
941 	pin = mtk_find_pin_by_eint_num(pctl, eint_n);
942 	if (!pin)
943 		return -EINVAL;
944 
945 	*gpio_chip = pctl->chip;
946 	*gpio_n = pin->pin.number;
947 
948 	return 0;
949 }
950 
951 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
952 {
953 	struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
954 	const struct mtk_desc_pin *pin;
955 
956 	pin = mtk_find_pin_by_eint_num(pctl, eint_n);
957 	if (!pin)
958 		return -EINVAL;
959 
960 	return mtk_gpio_get(pctl->chip, pin->pin.number);
961 }
962 
963 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
964 {
965 	struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
966 	const struct mtk_desc_pin *pin;
967 
968 	pin = mtk_find_pin_by_eint_num(pctl, eint_n);
969 	if (!pin)
970 		return -EINVAL;
971 
972 	/* set mux to INT mode */
973 	mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
974 	/* set gpio direction to input */
975 	mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
976 				   true);
977 	/* set input-enable */
978 	mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
979 			      PIN_CONFIG_INPUT_ENABLE);
980 
981 	return 0;
982 }
983 
984 static const struct mtk_eint_xt mtk_eint_xt = {
985 	.get_gpio_n = mtk_xt_get_gpio_n,
986 	.get_gpio_state = mtk_xt_get_gpio_state,
987 	.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
988 };
989 
990 static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
991 {
992 	struct device_node *np = pdev->dev.of_node;
993 	struct resource *res;
994 
995 	if (!of_property_read_bool(np, "interrupt-controller"))
996 		return -ENODEV;
997 
998 	pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
999 	if (!pctl->eint)
1000 		return -ENOMEM;
1001 
1002 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1003 	pctl->eint->base = devm_ioremap_resource(&pdev->dev, res);
1004 	if (IS_ERR(pctl->eint->base))
1005 		return PTR_ERR(pctl->eint->base);
1006 
1007 	pctl->eint->irq = irq_of_parse_and_map(np, 0);
1008 	if (!pctl->eint->irq)
1009 		return -EINVAL;
1010 
1011 	pctl->eint->dev = &pdev->dev;
1012 	/*
1013 	 * If pctl->eint->regs == NULL, it would fall back into using a generic
1014 	 * register map in mtk_eint_do_init calls.
1015 	 */
1016 	pctl->eint->regs = pctl->devdata->eint_regs;
1017 	pctl->eint->hw = &pctl->devdata->eint_hw;
1018 	pctl->eint->pctl = pctl;
1019 	pctl->eint->gpio_xlate = &mtk_eint_xt;
1020 
1021 	return mtk_eint_do_init(pctl->eint);
1022 }
1023 
1024 int mtk_pctrl_init(struct platform_device *pdev,
1025 		const struct mtk_pinctrl_devdata *data,
1026 		struct regmap *regmap)
1027 {
1028 	struct pinctrl_pin_desc *pins;
1029 	struct mtk_pinctrl *pctl;
1030 	struct device_node *np = pdev->dev.of_node, *node;
1031 	struct property *prop;
1032 	int ret, i;
1033 
1034 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1035 	if (!pctl)
1036 		return -ENOMEM;
1037 
1038 	platform_set_drvdata(pdev, pctl);
1039 
1040 	prop = of_find_property(np, "pins-are-numbered", NULL);
1041 	if (!prop) {
1042 		dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1043 		return -EINVAL;
1044 	}
1045 
1046 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1047 	if (node) {
1048 		pctl->regmap1 = syscon_node_to_regmap(node);
1049 		if (IS_ERR(pctl->regmap1))
1050 			return PTR_ERR(pctl->regmap1);
1051 	} else if (regmap) {
1052 		pctl->regmap1  = regmap;
1053 	} else {
1054 		dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1055 		return -EINVAL;
1056 	}
1057 
1058 	/* Only 8135 has two base addr, other SoCs have only one. */
1059 	node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1060 	if (node) {
1061 		pctl->regmap2 = syscon_node_to_regmap(node);
1062 		if (IS_ERR(pctl->regmap2))
1063 			return PTR_ERR(pctl->regmap2);
1064 	}
1065 
1066 	pctl->devdata = data;
1067 	ret = mtk_pctrl_build_state(pdev);
1068 	if (ret) {
1069 		dev_err(&pdev->dev, "build state failed: %d\n", ret);
1070 		return -EINVAL;
1071 	}
1072 
1073 	pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1074 			    GFP_KERNEL);
1075 	if (!pins)
1076 		return -ENOMEM;
1077 
1078 	for (i = 0; i < pctl->devdata->npins; i++)
1079 		pins[i] = pctl->devdata->pins[i].pin;
1080 
1081 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1082 	pctl->pctl_desc.owner = THIS_MODULE;
1083 	pctl->pctl_desc.pins = pins;
1084 	pctl->pctl_desc.npins = pctl->devdata->npins;
1085 	pctl->pctl_desc.confops = &mtk_pconf_ops;
1086 	pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1087 	pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1088 	pctl->dev = &pdev->dev;
1089 
1090 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1091 					       pctl);
1092 	if (IS_ERR(pctl->pctl_dev)) {
1093 		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1094 		return PTR_ERR(pctl->pctl_dev);
1095 	}
1096 
1097 	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1098 	if (!pctl->chip)
1099 		return -ENOMEM;
1100 
1101 	*pctl->chip = mtk_gpio_chip;
1102 	pctl->chip->ngpio = pctl->devdata->npins;
1103 	pctl->chip->label = dev_name(&pdev->dev);
1104 	pctl->chip->parent = &pdev->dev;
1105 	pctl->chip->base = -1;
1106 
1107 	ret = gpiochip_add_data(pctl->chip, pctl);
1108 	if (ret)
1109 		return -EINVAL;
1110 
1111 	/* Register the GPIO to pin mappings. */
1112 	ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1113 			0, 0, pctl->devdata->npins);
1114 	if (ret) {
1115 		ret = -EINVAL;
1116 		goto chip_error;
1117 	}
1118 
1119 	ret = mtk_eint_init(pctl, pdev);
1120 	if (ret)
1121 		goto chip_error;
1122 
1123 	return 0;
1124 
1125 chip_error:
1126 	gpiochip_remove(pctl->chip);
1127 	return ret;
1128 }
1129