1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * 5 * Author: Sean Wang <sean.wang@mediatek.com> 6 * 7 */ 8 9 #include <dt-bindings/pinctrl/mt65xx.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/platform_device.h> 14 #include <linux/io.h> 15 #include <linux/of_irq.h> 16 17 #include "mtk-eint.h" 18 #include "pinctrl-mtk-common-v2.h" 19 20 /** 21 * struct mtk_drive_desc - the structure that holds the information 22 * of the driving current 23 * @min: the minimum current of this group 24 * @max: the maximum current of this group 25 * @step: the step current of this group 26 * @scal: the weight factor 27 * 28 * formula: output = ((input) / step - 1) * scal 29 */ 30 struct mtk_drive_desc { 31 u8 min; 32 u8 max; 33 u8 step; 34 u8 scal; 35 }; 36 37 /* The groups of drive strength */ 38 static const struct mtk_drive_desc mtk_drive[] = { 39 [DRV_GRP0] = { 4, 16, 4, 1 }, 40 [DRV_GRP1] = { 4, 16, 4, 2 }, 41 [DRV_GRP2] = { 2, 8, 2, 1 }, 42 [DRV_GRP3] = { 2, 8, 2, 2 }, 43 [DRV_GRP4] = { 2, 16, 2, 1 }, 44 }; 45 46 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) 47 { 48 writel_relaxed(val, pctl->base[i] + reg); 49 } 50 51 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) 52 { 53 return readl_relaxed(pctl->base[i] + reg); 54 } 55 56 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) 57 { 58 u32 val; 59 60 val = mtk_r32(pctl, i, reg); 61 val &= ~mask; 62 val |= set; 63 mtk_w32(pctl, i, reg, val); 64 } 65 66 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, 67 const struct mtk_pin_desc *desc, 68 int field, struct mtk_pin_field *pfd) 69 { 70 const struct mtk_pin_field_calc *c; 71 const struct mtk_pin_reg_calc *rc; 72 int start = 0, end, check; 73 bool found = false; 74 u32 bits; 75 76 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { 77 rc = &hw->soc->reg_cal[field]; 78 } else { 79 dev_dbg(hw->dev, 80 "Not support field %d for this soc\n", field); 81 return -ENOTSUPP; 82 } 83 84 end = rc->nranges - 1; 85 86 while (start <= end) { 87 check = (start + end) >> 1; 88 if (desc->number >= rc->range[check].s_pin 89 && desc->number <= rc->range[check].e_pin) { 90 found = true; 91 break; 92 } else if (start == end) 93 break; 94 else if (desc->number < rc->range[check].s_pin) 95 end = check - 1; 96 else 97 start = check + 1; 98 } 99 100 if (!found) { 101 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", 102 field, desc->number, desc->name); 103 return -ENOTSUPP; 104 } 105 106 c = rc->range + check; 107 108 if (c->i_base > hw->nbase - 1) { 109 dev_err(hw->dev, 110 "Invalid base for field %d for pin = %d (%s)\n", 111 field, desc->number, desc->name); 112 return -EINVAL; 113 } 114 115 /* Calculated bits as the overall offset the pin is located at, 116 * if c->fixed is held, that determines the all the pins in the 117 * range use the same field with the s_pin. 118 */ 119 bits = c->fixed ? c->s_bit : c->s_bit + 120 (desc->number - c->s_pin) * (c->x_bits); 121 122 /* Fill pfd from bits. For example 32-bit register applied is assumed 123 * when c->sz_reg is equal to 32. 124 */ 125 pfd->index = c->i_base; 126 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); 127 pfd->bitpos = bits % c->sz_reg; 128 pfd->mask = (1 << c->x_bits) - 1; 129 130 /* pfd->next is used for indicating that bit wrapping-around happens 131 * which requires the manipulation for bit 0 starting in the next 132 * register to form the complete field read/write. 133 */ 134 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; 135 136 return 0; 137 } 138 139 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, 140 const struct mtk_pin_desc *desc, 141 int field, struct mtk_pin_field *pfd) 142 { 143 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { 144 dev_err(hw->dev, "Invalid Field %d\n", field); 145 return -EINVAL; 146 } 147 148 return mtk_hw_pin_field_lookup(hw, desc, field, pfd); 149 } 150 151 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) 152 { 153 *l = 32 - pf->bitpos; 154 *h = get_count_order(pf->mask) - *l; 155 } 156 157 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, 158 struct mtk_pin_field *pf, int value) 159 { 160 int nbits_l, nbits_h; 161 162 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 163 164 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, 165 (value & pf->mask) << pf->bitpos); 166 167 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, 168 (value & pf->mask) >> nbits_l); 169 } 170 171 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, 172 struct mtk_pin_field *pf, int *value) 173 { 174 int nbits_l, nbits_h, h, l; 175 176 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 177 178 l = (mtk_r32(hw, pf->index, pf->offset) 179 >> pf->bitpos) & (BIT(nbits_l) - 1); 180 h = (mtk_r32(hw, pf->index, pf->offset + pf->next)) 181 & (BIT(nbits_h) - 1); 182 183 *value = (h << nbits_l) | l; 184 } 185 186 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 187 int field, int value) 188 { 189 struct mtk_pin_field pf; 190 int err; 191 192 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 193 if (err) 194 return err; 195 196 if (value < 0 || value > pf.mask) 197 return -EINVAL; 198 199 if (!pf.next) 200 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, 201 (value & pf.mask) << pf.bitpos); 202 else 203 mtk_hw_write_cross_field(hw, &pf, value); 204 205 return 0; 206 } 207 208 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 209 int field, int *value) 210 { 211 struct mtk_pin_field pf; 212 int err; 213 214 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 215 if (err) 216 return err; 217 218 if (!pf.next) 219 *value = (mtk_r32(hw, pf.index, pf.offset) 220 >> pf.bitpos) & pf.mask; 221 else 222 mtk_hw_read_cross_field(hw, &pf, value); 223 224 return 0; 225 } 226 227 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) 228 { 229 const struct mtk_pin_desc *desc; 230 int i = 0; 231 232 desc = (const struct mtk_pin_desc *)hw->soc->pins; 233 234 while (i < hw->soc->npins) { 235 if (desc[i].eint.eint_n == eint_n) 236 return desc[i].number; 237 i++; 238 } 239 240 return EINT_NA; 241 } 242 243 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, 244 unsigned int *gpio_n, 245 struct gpio_chip **gpio_chip) 246 { 247 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 248 const struct mtk_pin_desc *desc; 249 250 desc = (const struct mtk_pin_desc *)hw->soc->pins; 251 *gpio_chip = &hw->chip; 252 253 /* Be greedy to guess first gpio_n is equal to eint_n */ 254 if (desc[eint_n].eint.eint_n == eint_n) 255 *gpio_n = eint_n; 256 else 257 *gpio_n = mtk_xt_find_eint_num(hw, eint_n); 258 259 return *gpio_n == EINT_NA ? -EINVAL : 0; 260 } 261 262 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 263 { 264 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 265 const struct mtk_pin_desc *desc; 266 struct gpio_chip *gpio_chip; 267 unsigned int gpio_n; 268 int value, err; 269 270 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 271 if (err) 272 return err; 273 274 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 275 276 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); 277 if (err) 278 return err; 279 280 return !!value; 281 } 282 283 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 284 { 285 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 286 const struct mtk_pin_desc *desc; 287 struct gpio_chip *gpio_chip; 288 unsigned int gpio_n; 289 int err; 290 291 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 292 if (err) 293 return err; 294 295 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 296 297 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, 298 desc->eint.eint_m); 299 if (err) 300 return err; 301 302 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); 303 if (err) 304 return err; 305 306 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE); 307 /* SMT is supposed to be supported by every real GPIO and doesn't 308 * support virtual GPIOs, so the extra condition err != -ENOTSUPP 309 * is just for adding EINT support to these virtual GPIOs. It should 310 * add an extra flag in the pin descriptor when more pins with 311 * distinctive characteristic come out. 312 */ 313 if (err && err != -ENOTSUPP) 314 return err; 315 316 return 0; 317 } 318 319 static const struct mtk_eint_xt mtk_eint_xt = { 320 .get_gpio_n = mtk_xt_get_gpio_n, 321 .get_gpio_state = mtk_xt_get_gpio_state, 322 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 323 }; 324 325 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) 326 { 327 struct device_node *np = pdev->dev.of_node; 328 struct resource *res; 329 330 if (!IS_ENABLED(CONFIG_EINT_MTK)) 331 return 0; 332 333 if (!of_property_read_bool(np, "interrupt-controller")) 334 return -ENODEV; 335 336 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); 337 if (!hw->eint) 338 return -ENOMEM; 339 340 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); 341 if (!res) { 342 dev_err(&pdev->dev, "Unable to get eint resource\n"); 343 return -ENODEV; 344 } 345 346 hw->eint->base = devm_ioremap_resource(&pdev->dev, res); 347 if (IS_ERR(hw->eint->base)) 348 return PTR_ERR(hw->eint->base); 349 350 hw->eint->irq = irq_of_parse_and_map(np, 0); 351 if (!hw->eint->irq) 352 return -EINVAL; 353 354 if (!hw->soc->eint_hw) 355 return -ENODEV; 356 357 hw->eint->dev = &pdev->dev; 358 hw->eint->hw = hw->soc->eint_hw; 359 hw->eint->pctl = hw; 360 hw->eint->gpio_xlate = &mtk_eint_xt; 361 362 return mtk_eint_do_init(hw->eint); 363 } 364 365 /* Revision 0 */ 366 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, 367 const struct mtk_pin_desc *desc) 368 { 369 int err; 370 371 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, 372 MTK_DISABLE); 373 if (err) 374 return err; 375 376 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 377 MTK_DISABLE); 378 if (err) 379 return err; 380 381 return 0; 382 } 383 384 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, 385 const struct mtk_pin_desc *desc, int *res) 386 { 387 int v, v2; 388 int err; 389 390 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v); 391 if (err) 392 return err; 393 394 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2); 395 if (err) 396 return err; 397 398 if (v == MTK_ENABLE || v2 == MTK_ENABLE) 399 return -EINVAL; 400 401 *res = 1; 402 403 return 0; 404 } 405 406 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, 407 const struct mtk_pin_desc *desc, bool pullup) 408 { 409 int err, arg; 410 411 arg = pullup ? 1 : 2; 412 413 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1); 414 if (err) 415 return err; 416 417 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 418 !!(arg & 2)); 419 if (err) 420 return err; 421 422 return 0; 423 } 424 425 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, 426 const struct mtk_pin_desc *desc, bool pullup, int *res) 427 { 428 int reg, err, v; 429 430 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; 431 432 err = mtk_hw_get_value(hw, desc, reg, &v); 433 if (err) 434 return err; 435 436 if (!v) 437 return -EINVAL; 438 439 *res = 1; 440 441 return 0; 442 } 443 444 /* Revision 1 */ 445 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, 446 const struct mtk_pin_desc *desc) 447 { 448 int err; 449 450 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 451 MTK_DISABLE); 452 if (err) 453 return err; 454 455 return 0; 456 } 457 458 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, 459 const struct mtk_pin_desc *desc, int *res) 460 { 461 int v, err; 462 463 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 464 if (err) 465 return err; 466 467 if (v == MTK_ENABLE) 468 return -EINVAL; 469 470 *res = 1; 471 472 return 0; 473 } 474 475 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, 476 const struct mtk_pin_desc *desc, bool pullup) 477 { 478 int err, arg; 479 480 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN; 481 482 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 483 MTK_ENABLE); 484 if (err) 485 return err; 486 487 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg); 488 if (err) 489 return err; 490 491 return 0; 492 } 493 494 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, 495 const struct mtk_pin_desc *desc, bool pullup, 496 int *res) 497 { 498 int err, v; 499 500 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 501 if (err) 502 return err; 503 504 if (v == MTK_DISABLE) 505 return -EINVAL; 506 507 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v); 508 if (err) 509 return err; 510 511 if (pullup ^ (v == MTK_PULLUP)) 512 return -EINVAL; 513 514 *res = 1; 515 516 return 0; 517 } 518 519 /* Combo for the following pull register type: 520 * 1. PU + PD 521 * 2. PULLSEL + PULLEN 522 * 3. PUPD + R0 + R1 523 */ 524 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, 525 const struct mtk_pin_desc *desc, 526 u32 pullup, u32 arg) 527 { 528 int err, pu, pd; 529 530 if (arg == MTK_DISABLE) { 531 pu = 0; 532 pd = 0; 533 } else if ((arg == MTK_ENABLE) && pullup) { 534 pu = 1; 535 pd = 0; 536 } else if ((arg == MTK_ENABLE) && !pullup) { 537 pu = 0; 538 pd = 1; 539 } else { 540 err = -EINVAL; 541 goto out; 542 } 543 544 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); 545 if (err) 546 goto out; 547 548 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); 549 550 out: 551 return err; 552 } 553 554 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, 555 const struct mtk_pin_desc *desc, 556 u32 pullup, u32 arg) 557 { 558 int err, enable; 559 560 if (arg == MTK_DISABLE) 561 enable = 0; 562 else if (arg == MTK_ENABLE) 563 enable = 1; 564 else { 565 err = -EINVAL; 566 goto out; 567 } 568 569 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 570 if (err) 571 goto out; 572 573 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 574 575 out: 576 return err; 577 } 578 579 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw, 580 const struct mtk_pin_desc *desc, 581 u32 pullup, u32 arg) 582 { 583 int err, r0, r1; 584 585 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) { 586 pullup = 0; 587 r0 = 0; 588 r1 = 0; 589 } else if (arg == MTK_PUPD_SET_R1R0_01) { 590 r0 = 1; 591 r1 = 0; 592 } else if (arg == MTK_PUPD_SET_R1R0_10) { 593 r0 = 0; 594 r1 = 1; 595 } else if (arg == MTK_PUPD_SET_R1R0_11) { 596 r0 = 1; 597 r1 = 1; 598 } else { 599 err = -EINVAL; 600 goto out; 601 } 602 603 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 604 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup); 605 if (err) 606 goto out; 607 608 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0); 609 if (err) 610 goto out; 611 612 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1); 613 614 out: 615 return err; 616 } 617 618 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, 619 const struct mtk_pin_desc *desc, 620 u32 *pullup, u32 *enable) 621 { 622 int err, pu, pd; 623 624 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); 625 if (err) 626 goto out; 627 628 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); 629 if (err) 630 goto out; 631 632 if (pu == 0 && pd == 0) { 633 *pullup = 0; 634 *enable = MTK_DISABLE; 635 } else if (pu == 1 && pd == 0) { 636 *pullup = 1; 637 *enable = MTK_ENABLE; 638 } else if (pu == 0 && pd == 1) { 639 *pullup = 0; 640 *enable = MTK_ENABLE; 641 } else 642 err = -EINVAL; 643 644 out: 645 return err; 646 } 647 648 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, 649 const struct mtk_pin_desc *desc, 650 u32 *pullup, u32 *enable) 651 { 652 int err; 653 654 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 655 if (err) 656 goto out; 657 658 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 659 660 out: 661 return err; 662 } 663 664 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw, 665 const struct mtk_pin_desc *desc, 666 u32 *pullup, u32 *enable) 667 { 668 int err, r0, r1; 669 670 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup); 671 if (err) 672 goto out; 673 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 674 *pullup = !(*pullup); 675 676 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0); 677 if (err) 678 goto out; 679 680 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1); 681 if (err) 682 goto out; 683 684 if ((r1 == 0) && (r0 == 0)) 685 *enable = MTK_PUPD_SET_R1R0_00; 686 else if ((r1 == 0) && (r0 == 1)) 687 *enable = MTK_PUPD_SET_R1R0_01; 688 else if ((r1 == 1) && (r0 == 0)) 689 *enable = MTK_PUPD_SET_R1R0_10; 690 else if ((r1 == 1) && (r0 == 1)) 691 *enable = MTK_PUPD_SET_R1R0_11; 692 else 693 err = -EINVAL; 694 695 out: 696 return err; 697 } 698 699 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, 700 const struct mtk_pin_desc *desc, 701 u32 pullup, u32 arg) 702 { 703 int err; 704 705 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); 706 if (!err) 707 goto out; 708 709 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); 710 if (!err) 711 goto out; 712 713 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); 714 715 out: 716 return err; 717 } 718 719 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, 720 const struct mtk_pin_desc *desc, 721 u32 *pullup, u32 *enable) 722 { 723 int err; 724 725 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); 726 if (!err) 727 goto out; 728 729 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); 730 if (!err) 731 goto out; 732 733 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); 734 735 out: 736 return err; 737 } 738 739 /* Revision 0 */ 740 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, 741 const struct mtk_pin_desc *desc, u32 arg) 742 { 743 const struct mtk_drive_desc *tb; 744 int err = -ENOTSUPP; 745 746 tb = &mtk_drive[desc->drv_n]; 747 /* 4mA when (e8, e4) = (0, 0) 748 * 8mA when (e8, e4) = (0, 1) 749 * 12mA when (e8, e4) = (1, 0) 750 * 16mA when (e8, e4) = (1, 1) 751 */ 752 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 753 arg = (arg / tb->step - 1) * tb->scal; 754 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4, 755 arg & 0x1); 756 if (err) 757 return err; 758 759 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8, 760 (arg & 0x2) >> 1); 761 if (err) 762 return err; 763 } 764 765 return err; 766 } 767 768 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, 769 const struct mtk_pin_desc *desc, int *val) 770 { 771 const struct mtk_drive_desc *tb; 772 int err, val1, val2; 773 774 tb = &mtk_drive[desc->drv_n]; 775 776 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1); 777 if (err) 778 return err; 779 780 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2); 781 if (err) 782 return err; 783 784 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) 785 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) 786 */ 787 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; 788 789 return 0; 790 } 791 792 /* Revision 1 */ 793 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, 794 const struct mtk_pin_desc *desc, u32 arg) 795 { 796 const struct mtk_drive_desc *tb; 797 int err = -ENOTSUPP; 798 799 tb = &mtk_drive[desc->drv_n]; 800 801 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 802 arg = (arg / tb->step - 1) * tb->scal; 803 804 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, 805 arg); 806 if (err) 807 return err; 808 } 809 810 return err; 811 } 812 813 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, 814 const struct mtk_pin_desc *desc, int *val) 815 { 816 const struct mtk_drive_desc *tb; 817 int err, val1; 818 819 tb = &mtk_drive[desc->drv_n]; 820 821 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1); 822 if (err) 823 return err; 824 825 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; 826 827 return 0; 828 } 829 830 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, 831 const struct mtk_pin_desc *desc, u32 arg) 832 { 833 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); 834 } 835 836 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, 837 const struct mtk_pin_desc *desc, int *val) 838 { 839 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); 840 } 841 842 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, 843 const struct mtk_pin_desc *desc, bool pullup, 844 u32 arg) 845 { 846 int err; 847 848 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0); 849 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1); 850 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0); 851 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1) 852 */ 853 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1); 854 if (err) 855 return 0; 856 857 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, 858 !!(arg & 2)); 859 if (err) 860 return 0; 861 862 arg = pullup ? 0 : 1; 863 864 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg); 865 866 /* If PUPD register is not supported for that pin, let's fallback to 867 * general bias control. 868 */ 869 if (err == -ENOTSUPP) { 870 if (hw->soc->bias_set) { 871 err = hw->soc->bias_set(hw, desc, pullup); 872 if (err) 873 return err; 874 } else { 875 return -ENOTSUPP; 876 } 877 } 878 879 return err; 880 } 881 882 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 883 const struct mtk_pin_desc *desc, bool pullup, 884 u32 *val) 885 { 886 u32 t, t2; 887 int err; 888 889 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t); 890 891 /* If PUPD register is not supported for that pin, let's fallback to 892 * general bias control. 893 */ 894 if (err == -ENOTSUPP) { 895 if (hw->soc->bias_get) { 896 err = hw->soc->bias_get(hw, desc, pullup, val); 897 if (err) 898 return err; 899 } else { 900 return -ENOTSUPP; 901 } 902 } else { 903 /* t == 0 supposes PULLUP for the customized PULL setup */ 904 if (err) 905 return err; 906 907 if (pullup ^ !t) 908 return -EINVAL; 909 } 910 911 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t); 912 if (err) 913 return err; 914 915 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2); 916 if (err) 917 return err; 918 919 *val = (t | t2 << 1) & 0x7; 920 921 return 0; 922 } 923 924 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, 925 const struct mtk_pin_desc *desc, u32 arg) 926 { 927 int err; 928 int en = arg & 1; 929 int e0 = !!(arg & 2); 930 int e1 = !!(arg & 4); 931 932 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); 933 if (err) 934 return err; 935 936 if (!en) 937 return err; 938 939 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0); 940 if (err) 941 return err; 942 943 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); 944 if (err) 945 return err; 946 947 return err; 948 } 949 950 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, 951 const struct mtk_pin_desc *desc, u32 *val) 952 { 953 u32 en, e0, e1; 954 int err; 955 956 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); 957 if (err) 958 return err; 959 960 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0); 961 if (err) 962 return err; 963 964 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1); 965 if (err) 966 return err; 967 968 *val = (en | e0 << 1 | e1 << 2) & 0x7; 969 970 return 0; 971 } 972