1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * 5 * Author: Sean Wang <sean.wang@mediatek.com> 6 * 7 */ 8 9 #include <dt-bindings/pinctrl/mt65xx.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/platform_device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_irq.h> 17 18 #include "mtk-eint.h" 19 #include "pinctrl-mtk-common-v2.h" 20 21 /** 22 * struct mtk_drive_desc - the structure that holds the information 23 * of the driving current 24 * @min: the minimum current of this group 25 * @max: the maximum current of this group 26 * @step: the step current of this group 27 * @scal: the weight factor 28 * 29 * formula: output = ((input) / step - 1) * scal 30 */ 31 struct mtk_drive_desc { 32 u8 min; 33 u8 max; 34 u8 step; 35 u8 scal; 36 }; 37 38 /* The groups of drive strength */ 39 static const struct mtk_drive_desc mtk_drive[] = { 40 [DRV_GRP0] = { 4, 16, 4, 1 }, 41 [DRV_GRP1] = { 4, 16, 4, 2 }, 42 [DRV_GRP2] = { 2, 8, 2, 1 }, 43 [DRV_GRP3] = { 2, 8, 2, 2 }, 44 [DRV_GRP4] = { 2, 16, 2, 1 }, 45 }; 46 47 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) 48 { 49 writel_relaxed(val, pctl->base[i] + reg); 50 } 51 52 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) 53 { 54 return readl_relaxed(pctl->base[i] + reg); 55 } 56 57 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) 58 { 59 u32 val; 60 61 val = mtk_r32(pctl, i, reg); 62 val &= ~mask; 63 val |= set; 64 mtk_w32(pctl, i, reg, val); 65 } 66 67 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, 68 const struct mtk_pin_desc *desc, 69 int field, struct mtk_pin_field *pfd) 70 { 71 const struct mtk_pin_field_calc *c; 72 const struct mtk_pin_reg_calc *rc; 73 int start = 0, end, check; 74 bool found = false; 75 u32 bits; 76 77 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { 78 rc = &hw->soc->reg_cal[field]; 79 } else { 80 dev_dbg(hw->dev, 81 "Not support field %d for this soc\n", field); 82 return -ENOTSUPP; 83 } 84 85 end = rc->nranges - 1; 86 87 while (start <= end) { 88 check = (start + end) >> 1; 89 if (desc->number >= rc->range[check].s_pin 90 && desc->number <= rc->range[check].e_pin) { 91 found = true; 92 break; 93 } else if (start == end) 94 break; 95 else if (desc->number < rc->range[check].s_pin) 96 end = check - 1; 97 else 98 start = check + 1; 99 } 100 101 if (!found) { 102 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", 103 field, desc->number, desc->name); 104 return -ENOTSUPP; 105 } 106 107 c = rc->range + check; 108 109 if (c->i_base > hw->nbase - 1) { 110 dev_err(hw->dev, 111 "Invalid base for field %d for pin = %d (%s)\n", 112 field, desc->number, desc->name); 113 return -EINVAL; 114 } 115 116 /* Calculated bits as the overall offset the pin is located at, 117 * if c->fixed is held, that determines the all the pins in the 118 * range use the same field with the s_pin. 119 */ 120 bits = c->fixed ? c->s_bit : c->s_bit + 121 (desc->number - c->s_pin) * (c->x_bits); 122 123 /* Fill pfd from bits. For example 32-bit register applied is assumed 124 * when c->sz_reg is equal to 32. 125 */ 126 pfd->index = c->i_base; 127 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); 128 pfd->bitpos = bits % c->sz_reg; 129 pfd->mask = (1 << c->x_bits) - 1; 130 131 /* pfd->next is used for indicating that bit wrapping-around happens 132 * which requires the manipulation for bit 0 starting in the next 133 * register to form the complete field read/write. 134 */ 135 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; 136 137 return 0; 138 } 139 140 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, 141 const struct mtk_pin_desc *desc, 142 int field, struct mtk_pin_field *pfd) 143 { 144 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { 145 dev_err(hw->dev, "Invalid Field %d\n", field); 146 return -EINVAL; 147 } 148 149 return mtk_hw_pin_field_lookup(hw, desc, field, pfd); 150 } 151 152 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) 153 { 154 *l = 32 - pf->bitpos; 155 *h = get_count_order(pf->mask) - *l; 156 } 157 158 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, 159 struct mtk_pin_field *pf, int value) 160 { 161 int nbits_l, nbits_h; 162 163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 164 165 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, 166 (value & pf->mask) << pf->bitpos); 167 168 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, 169 (value & pf->mask) >> nbits_l); 170 } 171 172 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, 173 struct mtk_pin_field *pf, int *value) 174 { 175 int nbits_l, nbits_h, h, l; 176 177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 178 179 l = (mtk_r32(hw, pf->index, pf->offset) 180 >> pf->bitpos) & (BIT(nbits_l) - 1); 181 h = (mtk_r32(hw, pf->index, pf->offset + pf->next)) 182 & (BIT(nbits_h) - 1); 183 184 *value = (h << nbits_l) | l; 185 } 186 187 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 188 int field, int value) 189 { 190 struct mtk_pin_field pf; 191 int err; 192 193 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 194 if (err) 195 return err; 196 197 if (value < 0 || value > pf.mask) 198 return -EINVAL; 199 200 if (!pf.next) 201 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, 202 (value & pf.mask) << pf.bitpos); 203 else 204 mtk_hw_write_cross_field(hw, &pf, value); 205 206 return 0; 207 } 208 EXPORT_SYMBOL_GPL(mtk_hw_set_value); 209 210 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 211 int field, int *value) 212 { 213 struct mtk_pin_field pf; 214 int err; 215 216 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 217 if (err) 218 return err; 219 220 if (!pf.next) 221 *value = (mtk_r32(hw, pf.index, pf.offset) 222 >> pf.bitpos) & pf.mask; 223 else 224 mtk_hw_read_cross_field(hw, &pf, value); 225 226 return 0; 227 } 228 EXPORT_SYMBOL_GPL(mtk_hw_get_value); 229 230 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) 231 { 232 const struct mtk_pin_desc *desc; 233 int i = 0; 234 235 desc = (const struct mtk_pin_desc *)hw->soc->pins; 236 237 while (i < hw->soc->npins) { 238 if (desc[i].eint.eint_n == eint_n) 239 return desc[i].number; 240 i++; 241 } 242 243 return EINT_NA; 244 } 245 246 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, 247 unsigned int *gpio_n, 248 struct gpio_chip **gpio_chip) 249 { 250 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 251 const struct mtk_pin_desc *desc; 252 253 desc = (const struct mtk_pin_desc *)hw->soc->pins; 254 *gpio_chip = &hw->chip; 255 256 /* Be greedy to guess first gpio_n is equal to eint_n */ 257 if (desc[eint_n].eint.eint_n == eint_n) 258 *gpio_n = eint_n; 259 else 260 *gpio_n = mtk_xt_find_eint_num(hw, eint_n); 261 262 return *gpio_n == EINT_NA ? -EINVAL : 0; 263 } 264 265 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 266 { 267 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 268 const struct mtk_pin_desc *desc; 269 struct gpio_chip *gpio_chip; 270 unsigned int gpio_n; 271 int value, err; 272 273 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 274 if (err) 275 return err; 276 277 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 278 279 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); 280 if (err) 281 return err; 282 283 return !!value; 284 } 285 286 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 287 { 288 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 289 const struct mtk_pin_desc *desc; 290 struct gpio_chip *gpio_chip; 291 unsigned int gpio_n; 292 int err; 293 294 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 295 if (err) 296 return err; 297 298 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 299 300 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, 301 desc->eint.eint_m); 302 if (err) 303 return err; 304 305 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); 306 if (err) 307 return err; 308 309 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE); 310 /* SMT is supposed to be supported by every real GPIO and doesn't 311 * support virtual GPIOs, so the extra condition err != -ENOTSUPP 312 * is just for adding EINT support to these virtual GPIOs. It should 313 * add an extra flag in the pin descriptor when more pins with 314 * distinctive characteristic come out. 315 */ 316 if (err && err != -ENOTSUPP) 317 return err; 318 319 return 0; 320 } 321 322 static const struct mtk_eint_xt mtk_eint_xt = { 323 .get_gpio_n = mtk_xt_get_gpio_n, 324 .get_gpio_state = mtk_xt_get_gpio_state, 325 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 326 }; 327 328 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) 329 { 330 struct device_node *np = pdev->dev.of_node; 331 struct resource *res; 332 333 if (!IS_ENABLED(CONFIG_EINT_MTK)) 334 return 0; 335 336 if (!of_property_read_bool(np, "interrupt-controller")) 337 return -ENODEV; 338 339 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); 340 if (!hw->eint) 341 return -ENOMEM; 342 343 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); 344 if (!res) { 345 dev_err(&pdev->dev, "Unable to get eint resource\n"); 346 return -ENODEV; 347 } 348 349 hw->eint->base = devm_ioremap_resource(&pdev->dev, res); 350 if (IS_ERR(hw->eint->base)) 351 return PTR_ERR(hw->eint->base); 352 353 hw->eint->irq = irq_of_parse_and_map(np, 0); 354 if (!hw->eint->irq) 355 return -EINVAL; 356 357 if (!hw->soc->eint_hw) 358 return -ENODEV; 359 360 hw->eint->dev = &pdev->dev; 361 hw->eint->hw = hw->soc->eint_hw; 362 hw->eint->pctl = hw; 363 hw->eint->gpio_xlate = &mtk_eint_xt; 364 365 return mtk_eint_do_init(hw->eint); 366 } 367 EXPORT_SYMBOL_GPL(mtk_build_eint); 368 369 /* Revision 0 */ 370 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, 371 const struct mtk_pin_desc *desc) 372 { 373 int err; 374 375 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, 376 MTK_DISABLE); 377 if (err) 378 return err; 379 380 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 381 MTK_DISABLE); 382 if (err) 383 return err; 384 385 return 0; 386 } 387 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); 388 389 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, 390 const struct mtk_pin_desc *desc, int *res) 391 { 392 int v, v2; 393 int err; 394 395 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v); 396 if (err) 397 return err; 398 399 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2); 400 if (err) 401 return err; 402 403 if (v == MTK_ENABLE || v2 == MTK_ENABLE) 404 return -EINVAL; 405 406 *res = 1; 407 408 return 0; 409 } 410 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); 411 412 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, 413 const struct mtk_pin_desc *desc, bool pullup) 414 { 415 int err, arg; 416 417 arg = pullup ? 1 : 2; 418 419 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1); 420 if (err) 421 return err; 422 423 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 424 !!(arg & 2)); 425 if (err) 426 return err; 427 428 return 0; 429 } 430 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); 431 432 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, 433 const struct mtk_pin_desc *desc, bool pullup, int *res) 434 { 435 int reg, err, v; 436 437 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; 438 439 err = mtk_hw_get_value(hw, desc, reg, &v); 440 if (err) 441 return err; 442 443 if (!v) 444 return -EINVAL; 445 446 *res = 1; 447 448 return 0; 449 } 450 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); 451 452 /* Revision 1 */ 453 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, 454 const struct mtk_pin_desc *desc) 455 { 456 int err; 457 458 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 459 MTK_DISABLE); 460 if (err) 461 return err; 462 463 return 0; 464 } 465 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); 466 467 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, 468 const struct mtk_pin_desc *desc, int *res) 469 { 470 int v, err; 471 472 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 473 if (err) 474 return err; 475 476 if (v == MTK_ENABLE) 477 return -EINVAL; 478 479 *res = 1; 480 481 return 0; 482 } 483 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); 484 485 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, 486 const struct mtk_pin_desc *desc, bool pullup) 487 { 488 int err, arg; 489 490 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN; 491 492 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 493 MTK_ENABLE); 494 if (err) 495 return err; 496 497 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg); 498 if (err) 499 return err; 500 501 return 0; 502 } 503 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); 504 505 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, 506 const struct mtk_pin_desc *desc, bool pullup, 507 int *res) 508 { 509 int err, v; 510 511 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 512 if (err) 513 return err; 514 515 if (v == MTK_DISABLE) 516 return -EINVAL; 517 518 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v); 519 if (err) 520 return err; 521 522 if (pullup ^ (v == MTK_PULLUP)) 523 return -EINVAL; 524 525 *res = 1; 526 527 return 0; 528 } 529 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1); 530 531 /* Combo for the following pull register type: 532 * 1. PU + PD 533 * 2. PULLSEL + PULLEN 534 * 3. PUPD + R0 + R1 535 */ 536 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, 537 const struct mtk_pin_desc *desc, 538 u32 pullup, u32 arg) 539 { 540 int err, pu, pd; 541 542 if (arg == MTK_DISABLE) { 543 pu = 0; 544 pd = 0; 545 } else if ((arg == MTK_ENABLE) && pullup) { 546 pu = 1; 547 pd = 0; 548 } else if ((arg == MTK_ENABLE) && !pullup) { 549 pu = 0; 550 pd = 1; 551 } else { 552 err = -EINVAL; 553 goto out; 554 } 555 556 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); 557 if (err) 558 goto out; 559 560 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); 561 562 out: 563 return err; 564 } 565 566 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, 567 const struct mtk_pin_desc *desc, 568 u32 pullup, u32 arg) 569 { 570 int err, enable; 571 572 if (arg == MTK_DISABLE) 573 enable = 0; 574 else if (arg == MTK_ENABLE) 575 enable = 1; 576 else { 577 err = -EINVAL; 578 goto out; 579 } 580 581 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 582 if (err) 583 goto out; 584 585 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 586 587 out: 588 return err; 589 } 590 591 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw, 592 const struct mtk_pin_desc *desc, 593 u32 pullup, u32 arg) 594 { 595 int err, r0, r1; 596 597 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) { 598 pullup = 0; 599 r0 = 0; 600 r1 = 0; 601 } else if (arg == MTK_PUPD_SET_R1R0_01) { 602 r0 = 1; 603 r1 = 0; 604 } else if (arg == MTK_PUPD_SET_R1R0_10) { 605 r0 = 0; 606 r1 = 1; 607 } else if (arg == MTK_PUPD_SET_R1R0_11) { 608 r0 = 1; 609 r1 = 1; 610 } else { 611 err = -EINVAL; 612 goto out; 613 } 614 615 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 616 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup); 617 if (err) 618 goto out; 619 620 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0); 621 if (err) 622 goto out; 623 624 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1); 625 626 out: 627 return err; 628 } 629 630 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw, 631 const struct mtk_pin_desc *desc, 632 u32 *pullup, u32 *enable) 633 { 634 int err, pu, pd; 635 636 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); 637 if (err) 638 goto out; 639 640 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); 641 if (err) 642 goto out; 643 644 if (pu == 0 && pd == 0) { 645 *pullup = 0; 646 *enable = MTK_DISABLE; 647 } else if (pu == 1 && pd == 0) { 648 *pullup = 1; 649 *enable = MTK_ENABLE; 650 } else if (pu == 0 && pd == 1) { 651 *pullup = 0; 652 *enable = MTK_ENABLE; 653 } else 654 err = -EINVAL; 655 656 out: 657 return err; 658 } 659 660 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, 661 const struct mtk_pin_desc *desc, 662 u32 *pullup, u32 *enable) 663 { 664 int err; 665 666 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup); 667 if (err) 668 goto out; 669 670 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable); 671 672 out: 673 return err; 674 } 675 676 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw, 677 const struct mtk_pin_desc *desc, 678 u32 *pullup, u32 *enable) 679 { 680 int err, r0, r1; 681 682 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup); 683 if (err) 684 goto out; 685 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */ 686 *pullup = !(*pullup); 687 688 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0); 689 if (err) 690 goto out; 691 692 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1); 693 if (err) 694 goto out; 695 696 if ((r1 == 0) && (r0 == 0)) 697 *enable = MTK_PUPD_SET_R1R0_00; 698 else if ((r1 == 0) && (r0 == 1)) 699 *enable = MTK_PUPD_SET_R1R0_01; 700 else if ((r1 == 1) && (r0 == 0)) 701 *enable = MTK_PUPD_SET_R1R0_10; 702 else if ((r1 == 1) && (r0 == 1)) 703 *enable = MTK_PUPD_SET_R1R0_11; 704 else 705 err = -EINVAL; 706 707 out: 708 return err; 709 } 710 711 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, 712 const struct mtk_pin_desc *desc, 713 u32 pullup, u32 arg) 714 { 715 int err; 716 717 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); 718 if (!err) 719 goto out; 720 721 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg); 722 if (!err) 723 goto out; 724 725 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg); 726 727 out: 728 return err; 729 } 730 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); 731 732 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, 733 const struct mtk_pin_desc *desc, 734 u32 *pullup, u32 *enable) 735 { 736 int err; 737 738 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); 739 if (!err) 740 goto out; 741 742 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable); 743 if (!err) 744 goto out; 745 746 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable); 747 748 out: 749 return err; 750 } 751 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); 752 753 /* Revision 0 */ 754 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, 755 const struct mtk_pin_desc *desc, u32 arg) 756 { 757 const struct mtk_drive_desc *tb; 758 int err = -ENOTSUPP; 759 760 tb = &mtk_drive[desc->drv_n]; 761 /* 4mA when (e8, e4) = (0, 0) 762 * 8mA when (e8, e4) = (0, 1) 763 * 12mA when (e8, e4) = (1, 0) 764 * 16mA when (e8, e4) = (1, 1) 765 */ 766 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 767 arg = (arg / tb->step - 1) * tb->scal; 768 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4, 769 arg & 0x1); 770 if (err) 771 return err; 772 773 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8, 774 (arg & 0x2) >> 1); 775 if (err) 776 return err; 777 } 778 779 return err; 780 } 781 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); 782 783 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, 784 const struct mtk_pin_desc *desc, int *val) 785 { 786 const struct mtk_drive_desc *tb; 787 int err, val1, val2; 788 789 tb = &mtk_drive[desc->drv_n]; 790 791 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1); 792 if (err) 793 return err; 794 795 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2); 796 if (err) 797 return err; 798 799 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) 800 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) 801 */ 802 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; 803 804 return 0; 805 } 806 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); 807 808 /* Revision 1 */ 809 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, 810 const struct mtk_pin_desc *desc, u32 arg) 811 { 812 const struct mtk_drive_desc *tb; 813 int err = -ENOTSUPP; 814 815 tb = &mtk_drive[desc->drv_n]; 816 817 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 818 arg = (arg / tb->step - 1) * tb->scal; 819 820 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, 821 arg); 822 if (err) 823 return err; 824 } 825 826 return err; 827 } 828 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); 829 830 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, 831 const struct mtk_pin_desc *desc, int *val) 832 { 833 const struct mtk_drive_desc *tb; 834 int err, val1; 835 836 tb = &mtk_drive[desc->drv_n]; 837 838 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1); 839 if (err) 840 return err; 841 842 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; 843 844 return 0; 845 } 846 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); 847 848 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, 849 const struct mtk_pin_desc *desc, u32 arg) 850 { 851 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); 852 } 853 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); 854 855 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, 856 const struct mtk_pin_desc *desc, int *val) 857 { 858 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); 859 } 860 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); 861 862 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, 863 const struct mtk_pin_desc *desc, bool pullup, 864 u32 arg) 865 { 866 int err; 867 868 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0); 869 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1); 870 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0); 871 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1) 872 */ 873 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1); 874 if (err) 875 return 0; 876 877 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, 878 !!(arg & 2)); 879 if (err) 880 return 0; 881 882 arg = pullup ? 0 : 1; 883 884 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg); 885 886 /* If PUPD register is not supported for that pin, let's fallback to 887 * general bias control. 888 */ 889 if (err == -ENOTSUPP) { 890 if (hw->soc->bias_set) { 891 err = hw->soc->bias_set(hw, desc, pullup); 892 if (err) 893 return err; 894 } else { 895 return -ENOTSUPP; 896 } 897 } 898 899 return err; 900 } 901 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); 902 903 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 904 const struct mtk_pin_desc *desc, bool pullup, 905 u32 *val) 906 { 907 u32 t, t2; 908 int err; 909 910 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t); 911 912 /* If PUPD register is not supported for that pin, let's fallback to 913 * general bias control. 914 */ 915 if (err == -ENOTSUPP) { 916 if (hw->soc->bias_get) { 917 err = hw->soc->bias_get(hw, desc, pullup, val); 918 if (err) 919 return err; 920 } else { 921 return -ENOTSUPP; 922 } 923 } else { 924 /* t == 0 supposes PULLUP for the customized PULL setup */ 925 if (err) 926 return err; 927 928 if (pullup ^ !t) 929 return -EINVAL; 930 } 931 932 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t); 933 if (err) 934 return err; 935 936 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2); 937 if (err) 938 return err; 939 940 *val = (t | t2 << 1) & 0x7; 941 942 return 0; 943 } 944 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); 945 946 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, 947 const struct mtk_pin_desc *desc, u32 arg) 948 { 949 int err; 950 int en = arg & 1; 951 int e0 = !!(arg & 2); 952 int e1 = !!(arg & 4); 953 954 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); 955 if (err) 956 return err; 957 958 if (!en) 959 return err; 960 961 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0); 962 if (err) 963 return err; 964 965 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); 966 if (err) 967 return err; 968 969 return err; 970 } 971 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); 972 973 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, 974 const struct mtk_pin_desc *desc, u32 *val) 975 { 976 u32 en, e0, e1; 977 int err; 978 979 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); 980 if (err) 981 return err; 982 983 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0); 984 if (err) 985 return err; 986 987 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1); 988 if (err) 989 return err; 990 991 *val = (en | e0 << 1 | e1 << 2) & 0x7; 992 993 return 0; 994 } 995 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); 996 997 MODULE_LICENSE("GPL v2"); 998 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 999 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); 1000