1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * 5 * Author: Sean Wang <sean.wang@mediatek.com> 6 * 7 */ 8 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/platform_device.h> 13 #include <linux/io.h> 14 #include <linux/of_irq.h> 15 16 #include "mtk-eint.h" 17 #include "pinctrl-mtk-common-v2.h" 18 19 /** 20 * struct mtk_drive_desc - the structure that holds the information 21 * of the driving current 22 * @min: the minimum current of this group 23 * @max: the maximum current of this group 24 * @step: the step current of this group 25 * @scal: the weight factor 26 * 27 * formula: output = ((input) / step - 1) * scal 28 */ 29 struct mtk_drive_desc { 30 u8 min; 31 u8 max; 32 u8 step; 33 u8 scal; 34 }; 35 36 /* The groups of drive strength */ 37 static const struct mtk_drive_desc mtk_drive[] = { 38 [DRV_GRP0] = { 4, 16, 4, 1 }, 39 [DRV_GRP1] = { 4, 16, 4, 2 }, 40 [DRV_GRP2] = { 2, 8, 2, 1 }, 41 [DRV_GRP3] = { 2, 8, 2, 2 }, 42 [DRV_GRP4] = { 2, 16, 2, 1 }, 43 }; 44 45 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) 46 { 47 writel_relaxed(val, pctl->base[i] + reg); 48 } 49 50 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) 51 { 52 return readl_relaxed(pctl->base[i] + reg); 53 } 54 55 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) 56 { 57 u32 val; 58 59 val = mtk_r32(pctl, i, reg); 60 val &= ~mask; 61 val |= set; 62 mtk_w32(pctl, i, reg, val); 63 } 64 65 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, 66 const struct mtk_pin_desc *desc, 67 int field, struct mtk_pin_field *pfd) 68 { 69 const struct mtk_pin_field_calc *c, *e; 70 const struct mtk_pin_reg_calc *rc; 71 u32 bits; 72 73 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { 74 rc = &hw->soc->reg_cal[field]; 75 } else { 76 dev_dbg(hw->dev, 77 "Not support field %d for pin %d (%s)\n", 78 field, desc->number, desc->name); 79 return -ENOTSUPP; 80 } 81 82 c = rc->range; 83 e = c + rc->nranges; 84 85 while (c < e) { 86 if (desc->number >= c->s_pin && desc->number <= c->e_pin) 87 break; 88 c++; 89 } 90 91 if (c >= e) { 92 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", 93 field, desc->number, desc->name); 94 return -ENOTSUPP; 95 } 96 97 if (c->i_base > hw->nbase - 1) { 98 dev_err(hw->dev, 99 "Invalid base for field %d for pin = %d (%s)\n", 100 field, desc->number, desc->name); 101 return -EINVAL; 102 } 103 104 /* Calculated bits as the overall offset the pin is located at, 105 * if c->fixed is held, that determines the all the pins in the 106 * range use the same field with the s_pin. 107 */ 108 bits = c->fixed ? c->s_bit : c->s_bit + 109 (desc->number - c->s_pin) * (c->x_bits); 110 111 /* Fill pfd from bits. For example 32-bit register applied is assumed 112 * when c->sz_reg is equal to 32. 113 */ 114 pfd->index = c->i_base; 115 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); 116 pfd->bitpos = bits % c->sz_reg; 117 pfd->mask = (1 << c->x_bits) - 1; 118 119 /* pfd->next is used for indicating that bit wrapping-around happens 120 * which requires the manipulation for bit 0 starting in the next 121 * register to form the complete field read/write. 122 */ 123 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; 124 125 return 0; 126 } 127 128 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, 129 const struct mtk_pin_desc *desc, 130 int field, struct mtk_pin_field *pfd) 131 { 132 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { 133 dev_err(hw->dev, "Invalid Field %d\n", field); 134 return -EINVAL; 135 } 136 137 return mtk_hw_pin_field_lookup(hw, desc, field, pfd); 138 } 139 140 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) 141 { 142 *l = 32 - pf->bitpos; 143 *h = get_count_order(pf->mask) - *l; 144 } 145 146 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, 147 struct mtk_pin_field *pf, int value) 148 { 149 int nbits_l, nbits_h; 150 151 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 152 153 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, 154 (value & pf->mask) << pf->bitpos); 155 156 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1, 157 (value & pf->mask) >> nbits_l); 158 } 159 160 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, 161 struct mtk_pin_field *pf, int *value) 162 { 163 int nbits_l, nbits_h, h, l; 164 165 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 166 167 l = (mtk_r32(hw, pf->index, pf->offset) 168 >> pf->bitpos) & (BIT(nbits_l) - 1); 169 h = (mtk_r32(hw, pf->index, pf->offset + pf->next)) 170 & (BIT(nbits_h) - 1); 171 172 *value = (h << nbits_l) | l; 173 } 174 175 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 176 int field, int value) 177 { 178 struct mtk_pin_field pf; 179 int err; 180 181 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 182 if (err) 183 return err; 184 185 if (!pf.next) 186 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, 187 (value & pf.mask) << pf.bitpos); 188 else 189 mtk_hw_write_cross_field(hw, &pf, value); 190 191 return 0; 192 } 193 194 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 195 int field, int *value) 196 { 197 struct mtk_pin_field pf; 198 int err; 199 200 err = mtk_hw_pin_field_get(hw, desc, field, &pf); 201 if (err) 202 return err; 203 204 if (!pf.next) 205 *value = (mtk_r32(hw, pf.index, pf.offset) 206 >> pf.bitpos) & pf.mask; 207 else 208 mtk_hw_read_cross_field(hw, &pf, value); 209 210 return 0; 211 } 212 213 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) 214 { 215 const struct mtk_pin_desc *desc; 216 int i = 0; 217 218 desc = (const struct mtk_pin_desc *)hw->soc->pins; 219 220 while (i < hw->soc->npins) { 221 if (desc[i].eint.eint_n == eint_n) 222 return desc[i].number; 223 i++; 224 } 225 226 return EINT_NA; 227 } 228 229 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, 230 unsigned int *gpio_n, 231 struct gpio_chip **gpio_chip) 232 { 233 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 234 const struct mtk_pin_desc *desc; 235 236 desc = (const struct mtk_pin_desc *)hw->soc->pins; 237 *gpio_chip = &hw->chip; 238 239 /* Be greedy to guess first gpio_n is equal to eint_n */ 240 if (desc[eint_n].eint.eint_n == eint_n) 241 *gpio_n = eint_n; 242 else 243 *gpio_n = mtk_xt_find_eint_num(hw, eint_n); 244 245 return *gpio_n == EINT_NA ? -EINVAL : 0; 246 } 247 248 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) 249 { 250 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 251 const struct mtk_pin_desc *desc; 252 struct gpio_chip *gpio_chip; 253 unsigned int gpio_n; 254 int value, err; 255 256 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 257 if (err) 258 return err; 259 260 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 261 262 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); 263 if (err) 264 return err; 265 266 return !!value; 267 } 268 269 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) 270 { 271 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data; 272 const struct mtk_pin_desc *desc; 273 struct gpio_chip *gpio_chip; 274 unsigned int gpio_n; 275 int err; 276 277 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip); 278 if (err) 279 return err; 280 281 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; 282 283 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, 284 desc->eint.eint_m); 285 if (err) 286 return err; 287 288 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); 289 if (err) 290 return err; 291 292 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE); 293 if (err) 294 return err; 295 296 return 0; 297 } 298 299 static const struct mtk_eint_xt mtk_eint_xt = { 300 .get_gpio_n = mtk_xt_get_gpio_n, 301 .get_gpio_state = mtk_xt_get_gpio_state, 302 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, 303 }; 304 305 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) 306 { 307 struct device_node *np = pdev->dev.of_node; 308 struct resource *res; 309 310 if (!IS_ENABLED(CONFIG_EINT_MTK)) 311 return 0; 312 313 if (!of_property_read_bool(np, "interrupt-controller")) 314 return -ENODEV; 315 316 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL); 317 if (!hw->eint) 318 return -ENOMEM; 319 320 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); 321 if (!res) { 322 dev_err(&pdev->dev, "Unable to get eint resource\n"); 323 return -ENODEV; 324 } 325 326 hw->eint->base = devm_ioremap_resource(&pdev->dev, res); 327 if (IS_ERR(hw->eint->base)) 328 return PTR_ERR(hw->eint->base); 329 330 hw->eint->irq = irq_of_parse_and_map(np, 0); 331 if (!hw->eint->irq) 332 return -EINVAL; 333 334 if (!hw->soc->eint_hw) 335 return -ENODEV; 336 337 hw->eint->dev = &pdev->dev; 338 hw->eint->hw = hw->soc->eint_hw; 339 hw->eint->pctl = hw; 340 hw->eint->gpio_xlate = &mtk_eint_xt; 341 342 return mtk_eint_do_init(hw->eint); 343 } 344 345 /* Revision 0 */ 346 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, 347 const struct mtk_pin_desc *desc) 348 { 349 int err; 350 351 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, 352 MTK_DISABLE); 353 if (err) 354 return err; 355 356 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 357 MTK_DISABLE); 358 if (err) 359 return err; 360 361 return 0; 362 } 363 364 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, 365 const struct mtk_pin_desc *desc, int *res) 366 { 367 int v, v2; 368 int err; 369 370 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v); 371 if (err) 372 return err; 373 374 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2); 375 if (err) 376 return err; 377 378 if (v == MTK_ENABLE || v2 == MTK_ENABLE) 379 return -EINVAL; 380 381 *res = 1; 382 383 return 0; 384 } 385 386 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, 387 const struct mtk_pin_desc *desc, bool pullup) 388 { 389 int err, arg; 390 391 arg = pullup ? 1 : 2; 392 393 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1); 394 if (err) 395 return err; 396 397 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, 398 !!(arg & 2)); 399 if (err) 400 return err; 401 402 return 0; 403 } 404 405 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, 406 const struct mtk_pin_desc *desc, bool pullup, int *res) 407 { 408 int reg, err, v; 409 410 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; 411 412 err = mtk_hw_get_value(hw, desc, reg, &v); 413 if (err) 414 return err; 415 416 if (!v) 417 return -EINVAL; 418 419 *res = 1; 420 421 return 0; 422 } 423 424 /* Revision 1 */ 425 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, 426 const struct mtk_pin_desc *desc) 427 { 428 int err; 429 430 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 431 MTK_DISABLE); 432 if (err) 433 return err; 434 435 return 0; 436 } 437 438 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, 439 const struct mtk_pin_desc *desc, int *res) 440 { 441 int v, err; 442 443 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 444 if (err) 445 return err; 446 447 if (v == MTK_ENABLE) 448 return -EINVAL; 449 450 *res = 1; 451 452 return 0; 453 } 454 455 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, 456 const struct mtk_pin_desc *desc, bool pullup) 457 { 458 int err, arg; 459 460 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN; 461 462 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, 463 MTK_ENABLE); 464 if (err) 465 return err; 466 467 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg); 468 if (err) 469 return err; 470 471 return 0; 472 } 473 474 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, 475 const struct mtk_pin_desc *desc, bool pullup, 476 int *res) 477 { 478 int err, v; 479 480 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v); 481 if (err) 482 return err; 483 484 if (v == MTK_DISABLE) 485 return -EINVAL; 486 487 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v); 488 if (err) 489 return err; 490 491 if (pullup ^ (v == MTK_PULLUP)) 492 return -EINVAL; 493 494 *res = 1; 495 496 return 0; 497 } 498 499 /* Revision 0 */ 500 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, 501 const struct mtk_pin_desc *desc, u32 arg) 502 { 503 const struct mtk_drive_desc *tb; 504 int err = -ENOTSUPP; 505 506 tb = &mtk_drive[desc->drv_n]; 507 /* 4mA when (e8, e4) = (0, 0) 508 * 8mA when (e8, e4) = (0, 1) 509 * 12mA when (e8, e4) = (1, 0) 510 * 16mA when (e8, e4) = (1, 1) 511 */ 512 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 513 arg = (arg / tb->step - 1) * tb->scal; 514 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4, 515 arg & 0x1); 516 if (err) 517 return err; 518 519 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8, 520 (arg & 0x2) >> 1); 521 if (err) 522 return err; 523 } 524 525 return err; 526 } 527 528 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, 529 const struct mtk_pin_desc *desc, int *val) 530 { 531 const struct mtk_drive_desc *tb; 532 int err, val1, val2; 533 534 tb = &mtk_drive[desc->drv_n]; 535 536 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1); 537 if (err) 538 return err; 539 540 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2); 541 if (err) 542 return err; 543 544 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) 545 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) 546 */ 547 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step; 548 549 return 0; 550 } 551 552 /* Revision 1 */ 553 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, 554 const struct mtk_pin_desc *desc, u32 arg) 555 { 556 const struct mtk_drive_desc *tb; 557 int err = -ENOTSUPP; 558 559 tb = &mtk_drive[desc->drv_n]; 560 561 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { 562 arg = (arg / tb->step - 1) * tb->scal; 563 564 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, 565 arg); 566 if (err) 567 return err; 568 } 569 570 return err; 571 } 572 573 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, 574 const struct mtk_pin_desc *desc, int *val) 575 { 576 const struct mtk_drive_desc *tb; 577 int err, val1; 578 579 tb = &mtk_drive[desc->drv_n]; 580 581 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1); 582 if (err) 583 return err; 584 585 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step; 586 587 return 0; 588 } 589 590 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, 591 const struct mtk_pin_desc *desc, bool pullup, 592 u32 arg) 593 { 594 int err; 595 596 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0); 597 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1); 598 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0); 599 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1) 600 */ 601 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1); 602 if (err) 603 return 0; 604 605 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, 606 !!(arg & 2)); 607 if (err) 608 return 0; 609 610 arg = pullup ? 0 : 1; 611 612 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg); 613 614 /* If PUPD register is not supported for that pin, let's fallback to 615 * general bias control. 616 */ 617 if (err == -ENOTSUPP) { 618 if (hw->soc->bias_set) { 619 err = hw->soc->bias_set(hw, desc, pullup); 620 if (err) 621 return err; 622 } else { 623 return -ENOTSUPP; 624 } 625 } 626 627 return err; 628 } 629 630 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 631 const struct mtk_pin_desc *desc, bool pullup, 632 u32 *val) 633 { 634 u32 t, t2; 635 int err; 636 637 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t); 638 639 /* If PUPD register is not supported for that pin, let's fallback to 640 * general bias control. 641 */ 642 if (err == -ENOTSUPP) { 643 if (hw->soc->bias_get) { 644 err = hw->soc->bias_get(hw, desc, pullup, val); 645 if (err) 646 return err; 647 } else { 648 return -ENOTSUPP; 649 } 650 } else { 651 /* t == 0 supposes PULLUP for the customized PULL setup */ 652 if (err) 653 return err; 654 655 if (pullup ^ !t) 656 return -EINVAL; 657 } 658 659 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t); 660 if (err) 661 return err; 662 663 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2); 664 if (err) 665 return err; 666 667 *val = (t | t2 << 1) & 0x7; 668 669 return 0; 670 } 671