1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/platform_device.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/regmap.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <dt-bindings/pinctrl/mt65xx.h> 23 24 #include "pinctrl-mtk-common.h" 25 #include "pinctrl-mtk-mt8173.h" 26 27 #define DRV_BASE 0xb00 28 29 static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { 30 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ 31 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ 32 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */ 33 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */ 34 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */ 35 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */ 36 37 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */ 38 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */ 39 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */ 40 MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */ 41 MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */ 42 MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */ 43 MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */ 44 MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */ 45 MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */ 46 MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */ 47 MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */ 48 MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */ 49 50 MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */ 51 MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ 52 MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ 53 MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ 54 MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ 55 MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */ 56 57 MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ 58 MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ 59 MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ 60 MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ 61 MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */ 62 MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */ 63 64 MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ 65 MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ 66 MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ 67 MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ 68 MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */ 69 MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ 70 }; 71 72 static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, 73 unsigned char align, bool isup, unsigned int r1r0) 74 { 75 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, 76 ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); 77 } 78 79 static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { 80 MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), 81 MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), 82 MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10), 83 MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10), 84 MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), 85 MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), 86 MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), 87 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13), 88 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13), 89 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13), 90 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13), 91 MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), 92 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), 93 MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), 94 MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6), 95 MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7), 96 MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), 97 MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0), 98 MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11), 99 MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12), 100 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13), 101 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13), 102 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13), 103 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13), 104 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13), 105 MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14), 106 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13), 107 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13), 108 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13), 109 MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15), 110 MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0), 111 MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1), 112 MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2), 113 MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13), 114 MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14), 115 MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15), 116 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13), 117 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13), 118 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13), 119 MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4), 120 MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1), 121 MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2), 122 MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5), 123 MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6), 124 MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7), 125 MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0), 126 MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8), 127 MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9), 128 MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8), 129 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) 130 }; 131 132 static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { 133 MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1), 134 MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2), 135 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10), 136 MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10), 137 MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), 138 MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), 139 MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), 140 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14), 141 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14), 142 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14), 143 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14), 144 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), 145 MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), 146 MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), 147 MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6), 148 MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7), 149 MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), 150 MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0), 151 MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11), 152 MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12), 153 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14), 154 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14), 155 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14), 156 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14), 157 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14), 158 MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14), 159 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14), 160 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14), 161 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14), 162 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15), 163 MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0), 164 MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1), 165 MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2), 166 MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13), 167 MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14), 168 MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15), 169 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), 170 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), 171 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), 172 MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4), 173 MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), 174 MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), 175 MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), 176 MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6), 177 MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7), 178 MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0), 179 MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8), 180 MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9), 181 MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8), 182 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) 183 }; 184 185 static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, 186 unsigned char align, int value, enum pin_config_param arg) 187 { 188 if (arg == PIN_CONFIG_INPUT_ENABLE) 189 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, 190 ARRAY_SIZE(mt8173_ies_set), pin, align, value); 191 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) 192 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, 193 ARRAY_SIZE(mt8173_smt_set), pin, align, value); 194 return -EINVAL; 195 } 196 197 static const struct mtk_drv_group_desc mt8173_drv_grp[] = { 198 /* 0E4E8SR 4/8/12/16 */ 199 MTK_DRV_GRP(4, 16, 1, 2, 4), 200 /* 0E2E4SR 2/4/6/8 */ 201 MTK_DRV_GRP(2, 8, 1, 2, 2), 202 /* E8E4E2 2/4/6/8/10/12/14/16 */ 203 MTK_DRV_GRP(2, 16, 0, 2, 2) 204 }; 205 206 static const struct mtk_pin_drv_grp mt8173_pin_drv[] = { 207 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0), 208 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0), 209 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0), 210 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0), 211 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0), 212 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0), 213 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0), 214 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0), 215 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0), 216 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0), 217 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1), 218 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1), 219 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1), 220 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1), 221 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1), 222 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1), 223 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1), 224 MTK_PIN_DRV_GRP(17, 0xce0, 8, 2), 225 MTK_PIN_DRV_GRP(22, 0xce0, 8, 2), 226 MTK_PIN_DRV_GRP(23, 0xce0, 8, 2), 227 MTK_PIN_DRV_GRP(24, 0xce0, 8, 2), 228 MTK_PIN_DRV_GRP(25, 0xce0, 8, 2), 229 MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2), 230 MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2), 231 MTK_PIN_DRV_GRP(28, 0xd70, 8, 2), 232 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1), 233 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1), 234 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1), 235 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1), 236 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1), 237 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1), 238 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1), 239 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1), 240 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1), 241 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1), 242 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0), 243 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0), 244 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0), 245 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1), 246 MTK_PIN_DRV_GRP(57, 0xc20, 8, 2), 247 MTK_PIN_DRV_GRP(58, 0xc20, 8, 2), 248 MTK_PIN_DRV_GRP(59, 0xc20, 8, 2), 249 MTK_PIN_DRV_GRP(60, 0xc20, 8, 2), 250 MTK_PIN_DRV_GRP(61, 0xc20, 8, 2), 251 MTK_PIN_DRV_GRP(62, 0xc20, 8, 2), 252 MTK_PIN_DRV_GRP(63, 0xc20, 8, 2), 253 MTK_PIN_DRV_GRP(64, 0xc20, 8, 2), 254 MTK_PIN_DRV_GRP(65, 0xc00, 8, 2), 255 MTK_PIN_DRV_GRP(66, 0xc10, 8, 2), 256 MTK_PIN_DRV_GRP(67, 0xd10, 8, 2), 257 MTK_PIN_DRV_GRP(68, 0xd00, 8, 2), 258 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1), 259 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1), 260 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1), 261 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1), 262 MTK_PIN_DRV_GRP(73, 0xc60, 8, 2), 263 MTK_PIN_DRV_GRP(74, 0xc60, 8, 2), 264 MTK_PIN_DRV_GRP(75, 0xc60, 8, 2), 265 MTK_PIN_DRV_GRP(76, 0xc60, 8, 2), 266 MTK_PIN_DRV_GRP(77, 0xc40, 8, 2), 267 MTK_PIN_DRV_GRP(78, 0xc50, 8, 2), 268 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1), 269 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1), 270 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1), 271 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1), 272 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1), 273 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1), 274 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1), 275 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1), 276 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1), 277 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1), 278 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1), 279 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1), 280 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1), 281 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1), 282 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0), 283 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0), 284 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0), 285 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0), 286 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1), 287 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1), 288 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1), 289 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1), 290 MTK_PIN_DRV_GRP(100, 0xca0, 8, 2), 291 MTK_PIN_DRV_GRP(101, 0xca0, 8, 2), 292 MTK_PIN_DRV_GRP(102, 0xca0, 8, 2), 293 MTK_PIN_DRV_GRP(103, 0xca0, 8, 2), 294 MTK_PIN_DRV_GRP(104, 0xc80, 8, 2), 295 MTK_PIN_DRV_GRP(105, 0xc90, 8, 2), 296 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1), 297 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1), 298 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1), 299 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1), 300 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1), 301 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1), 302 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1), 303 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1), 304 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1), 305 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1), 306 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1), 307 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1), 308 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1), 309 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1), 310 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1), 311 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1), 312 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1), 313 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1), 314 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1), 315 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1), 316 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1), 317 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1), 318 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1), 319 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1), 320 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1) 321 }; 322 323 static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { 324 .pins = mtk_pins_mt8173, 325 .npins = ARRAY_SIZE(mtk_pins_mt8173), 326 .grp_desc = mt8173_drv_grp, 327 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), 328 .pin_drv_grp = mt8173_pin_drv, 329 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), 330 .spec_pull_set = mt8173_spec_pull_set, 331 .spec_ies_smt_set = mt8173_ies_smt_set, 332 .dir_offset = 0x0000, 333 .pullen_offset = 0x0100, 334 .pullsel_offset = 0x0200, 335 .dout_offset = 0x0400, 336 .din_offset = 0x0500, 337 .pinmux_offset = 0x0600, 338 .type1_start = 135, 339 .type1_end = 135, 340 .port_shf = 4, 341 .port_mask = 0xf, 342 .port_align = 4, 343 .eint_offsets = { 344 .name = "mt8173_eint", 345 .stat = 0x000, 346 .ack = 0x040, 347 .mask = 0x080, 348 .mask_set = 0x0c0, 349 .mask_clr = 0x100, 350 .sens = 0x140, 351 .sens_set = 0x180, 352 .sens_clr = 0x1c0, 353 .soft = 0x200, 354 .soft_set = 0x240, 355 .soft_clr = 0x280, 356 .pol = 0x300, 357 .pol_set = 0x340, 358 .pol_clr = 0x380, 359 .dom_en = 0x400, 360 .dbnc_ctrl = 0x500, 361 .dbnc_set = 0x600, 362 .dbnc_clr = 0x700, 363 .port_mask = 7, 364 .ports = 6, 365 }, 366 .ap_num = 224, 367 .db_cnt = 16, 368 }; 369 370 static int mt8173_pinctrl_probe(struct platform_device *pdev) 371 { 372 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL); 373 } 374 375 static const struct of_device_id mt8173_pctrl_match[] = { 376 { 377 .compatible = "mediatek,mt8173-pinctrl", 378 }, 379 { } 380 }; 381 382 static struct platform_driver mtk_pinctrl_driver = { 383 .probe = mt8173_pinctrl_probe, 384 .driver = { 385 .name = "mediatek-mt8173-pinctrl", 386 .of_match_table = mt8173_pctrl_match, 387 .pm = &mtk_eint_pm_ops, 388 }, 389 }; 390 391 static int __init mtk_pinctrl_init(void) 392 { 393 return platform_driver_register(&mtk_pinctrl_driver); 394 } 395 arch_initcall(mtk_pinctrl_init); 396