1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * The MT7986 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2021 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9 #include "pinctrl-moore.h"
10
11 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
12 #define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
13
14 #define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
15 _x_bits) \
16 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
17 _x_bits, 32, 0)
18
19 /**
20 * enum - Locking variants of the iocfg bases
21 *
22 * MT7986 have multiple bases to program pin configuration listed as the below:
23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
25 * _i_based could be used to indicate what base the pin should be mapped into.
26 *
27 * Each iocfg register base control different group of pads on the SoC
28 *
29 *
30 * chip carrier
31 *
32 * A B C D E F G H
33 * +------------------------+
34 * 8 | o o o o o o o o |
35 * 7 | o o o o o o o o |
36 * 6 | o o o o o o o o |
37 * 5 | o o o o o o o o |
38 * 4 | o o o o o o o o |
39 * 3 | o o o o o o o o |
40 * 2 | o o o o o o o o |
41 * 1 | o o o o o o o o |
42 * +------------------------+
43 *
44 * inside Chip carrier
45 *
46 * A B C D E F G H
47 * +------------------------+
48 * 8 | |
49 * 7 | TL TR |
50 * 6 | +---------+ |
51 * 5 | LT | | RT |
52 * 4 | | | |
53 * 3 | LB | | RB |
54 * 2 | +---------+ |
55 * 1 | |
56 * +------------------------+
57 *
58 */
59
60 enum {
61 GPIO_BASE,
62 IOCFG_RT_BASE,
63 IOCFG_RB_BASE,
64 IOCFG_LT_BASE,
65 IOCFG_LB_BASE,
66 IOCFG_TR_BASE,
67 IOCFG_TL_BASE,
68 };
69
70 static const char *const mt7986_pinctrl_register_base_names[] = {
71 "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
72 "iocfg_tl",
73 };
74
75 static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
77 };
78
79 static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
81 };
82
83 static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
85 };
86
87 static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
89 };
90
91 static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
94 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
95 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
96 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
97 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
98 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
99 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
100 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
101 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
102 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
103 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
104 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
105 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
106 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
107 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
108 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
109 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
110 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
111 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
112 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
113 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
114 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
115 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
116 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
117 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
118 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
119 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
120 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
121 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
122 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
123 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
124 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
125 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
126 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
127 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
128 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
129 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
130 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
131 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
132 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
133 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
134 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
135 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
136 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
137 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
138 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
139 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
140 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
141 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
142 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
143 };
144
145 static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
146 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
147 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
148 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
149 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
150 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
151 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
152 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
153 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
154 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
155 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
156 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
157 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
158 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
159 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
160 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
161 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
162 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
163 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
164 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
165 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
166 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
167 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
168 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
169 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
170 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
171 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
172 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
173 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
174 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
175 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
176 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
177 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
178 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
179 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
180 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
181 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
182 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
183 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
184 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
185 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
186 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
187 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
188 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
189 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
190 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
191 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
192 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
193 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
194 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
195 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
196 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
197 };
198
199 static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
200 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
201 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
202 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
203 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
204 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
205 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
206 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
207 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
208 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
209 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
210 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
211 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
212 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
213 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
214 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
215 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
216 };
217
218 static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
219 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
220 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
221 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
222 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
223 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
224 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
225 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
226 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
227 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
228 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
229 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
230 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
231 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
232 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
233 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
234 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
235 };
236
237 static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
238 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
239 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
240 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
241 PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
242 PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
243 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
244 PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
245 PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
246 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
247 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
248 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
249 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
250 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
251 PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
252 PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
253 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
254 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
255 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
256 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
257 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
258 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
259 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
260 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
261 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
262 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
263 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
264 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
265 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
266 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
267 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
268 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
269 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
270 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
271 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
272 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
273 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
274 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
275 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
276 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
277 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
278 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
279 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
280 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
281 PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
282 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
283 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
284 PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
285 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
286 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
287 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
288 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
289 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
290 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
291 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
292 PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
293 PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
294 };
295
296 static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
297 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
298 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
299 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
300 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
301 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
302 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
303 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
304 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
305 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
306 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
307 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
308 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
309 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
310 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
311 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
312 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
313 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
314 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
315 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
316 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
317 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
318 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
319 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
320 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
321 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
322 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
323 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
324 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
325 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
326 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
327 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
328 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
329 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
330 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
331 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
332 };
333
334 static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
335 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
336 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
337 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
338 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
339 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
340 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
341 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
342 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
343 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
344 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
345 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
346 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
347 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
348 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
349 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
350 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
351 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
352 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
353 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
354 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
355 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
356 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
357 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
358 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
359 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
360 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
361 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
362 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
363 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
364 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
365 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
366 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
367 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
368 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
369 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
370 };
371
372 static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
373 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
374 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
375 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
376 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
377 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
378 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
379 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
380 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
381 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
382 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
383 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
384 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
385 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
386 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
387 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
388 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
389 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
390 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
391 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
392 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
393 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
394 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
395 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
396 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
397 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
398 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
399 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
400 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
401 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
402 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
403 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
404 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
405 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
406 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
407 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
408 };
409
410 static const unsigned int mt7986_pull_type[] = {
411 MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
412 MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
413 MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
414 MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
415 MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
416 MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
417 MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
418 MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
419 MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
420 MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
421 MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
422 MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
423 MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
424 MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
425 MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
426 MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
427 MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
428 MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
429 MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
430 MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
431 MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
432 MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
433 MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
434 MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
435 MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
436 MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
437 MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
438 MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
439 MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
440 MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
441 MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
442 MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
443 MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
444 MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
445 MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
446 MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
447 MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
448 MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
449 MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
450 MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
451 MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
452 MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
453 MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
454 MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
455 MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
456 MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
457 MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
458 MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
459 MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
460 MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
461 MTK_PULL_PU_PD_TYPE,/*100*/
462 };
463
464 static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
465 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
466 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
467 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
468 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
469 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
470 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
471 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
472 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
473 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
474 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
475 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
476 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
477 };
478
479 static const struct mtk_pin_desc mt7986a_pins[] = {
480 MT7986_PIN(0, "SYS_WATCHDOG"),
481 MT7986_PIN(1, "WF2G_LED"),
482 MT7986_PIN(2, "WF5G_LED"),
483 MT7986_PIN(3, "I2C_SCL"),
484 MT7986_PIN(4, "I2C_SDA"),
485 MT7986_PIN(5, "GPIO_0"),
486 MT7986_PIN(6, "GPIO_1"),
487 MT7986_PIN(7, "GPIO_2"),
488 MT7986_PIN(8, "GPIO_3"),
489 MT7986_PIN(9, "GPIO_4"),
490 MT7986_PIN(10, "GPIO_5"),
491 MT7986_PIN(11, "GPIO_6"),
492 MT7986_PIN(12, "GPIO_7"),
493 MT7986_PIN(13, "GPIO_8"),
494 MT7986_PIN(14, "GPIO_9"),
495 MT7986_PIN(15, "GPIO_10"),
496 MT7986_PIN(16, "GPIO_11"),
497 MT7986_PIN(17, "GPIO_12"),
498 MT7986_PIN(18, "GPIO_13"),
499 MT7986_PIN(19, "GPIO_14"),
500 MT7986_PIN(20, "GPIO_15"),
501 MT7986_PIN(21, "PWM0"),
502 MT7986_PIN(22, "PWM1"),
503 MT7986_PIN(23, "SPI0_CLK"),
504 MT7986_PIN(24, "SPI0_MOSI"),
505 MT7986_PIN(25, "SPI0_MISO"),
506 MT7986_PIN(26, "SPI0_CS"),
507 MT7986_PIN(27, "SPI0_HOLD"),
508 MT7986_PIN(28, "SPI0_WP"),
509 MT7986_PIN(29, "SPI1_CLK"),
510 MT7986_PIN(30, "SPI1_MOSI"),
511 MT7986_PIN(31, "SPI1_MISO"),
512 MT7986_PIN(32, "SPI1_CS"),
513 MT7986_PIN(33, "SPI2_CLK"),
514 MT7986_PIN(34, "SPI2_MOSI"),
515 MT7986_PIN(35, "SPI2_MISO"),
516 MT7986_PIN(36, "SPI2_CS"),
517 MT7986_PIN(37, "SPI2_HOLD"),
518 MT7986_PIN(38, "SPI2_WP"),
519 MT7986_PIN(39, "UART0_RXD"),
520 MT7986_PIN(40, "UART0_TXD"),
521 MT7986_PIN(41, "PCIE_PERESET_N"),
522 MT7986_PIN(42, "UART1_RXD"),
523 MT7986_PIN(43, "UART1_TXD"),
524 MT7986_PIN(44, "UART1_CTS"),
525 MT7986_PIN(45, "UART1_RTS"),
526 MT7986_PIN(46, "UART2_RXD"),
527 MT7986_PIN(47, "UART2_TXD"),
528 MT7986_PIN(48, "UART2_CTS"),
529 MT7986_PIN(49, "UART2_RTS"),
530 MT7986_PIN(50, "EMMC_DATA_0"),
531 MT7986_PIN(51, "EMMC_DATA_1"),
532 MT7986_PIN(52, "EMMC_DATA_2"),
533 MT7986_PIN(53, "EMMC_DATA_3"),
534 MT7986_PIN(54, "EMMC_DATA_4"),
535 MT7986_PIN(55, "EMMC_DATA_5"),
536 MT7986_PIN(56, "EMMC_DATA_6"),
537 MT7986_PIN(57, "EMMC_DATA_7"),
538 MT7986_PIN(58, "EMMC_CMD"),
539 MT7986_PIN(59, "EMMC_CK"),
540 MT7986_PIN(60, "EMMC_DSL"),
541 MT7986_PIN(61, "EMMC_RSTB"),
542 MT7986_PIN(62, "PCM_DTX"),
543 MT7986_PIN(63, "PCM_DRX"),
544 MT7986_PIN(64, "PCM_CLK"),
545 MT7986_PIN(65, "PCM_FS"),
546 MT7986_PIN(66, "MT7531_INT"),
547 MT7986_PIN(67, "SMI_MDC"),
548 MT7986_PIN(68, "SMI_MDIO"),
549 MT7986_PIN(69, "WF0_DIG_RESETB"),
550 MT7986_PIN(70, "WF0_CBA_RESETB"),
551 MT7986_PIN(71, "WF0_XO_REQ"),
552 MT7986_PIN(72, "WF0_TOP_CLK"),
553 MT7986_PIN(73, "WF0_TOP_DATA"),
554 MT7986_PIN(74, "WF0_HB1"),
555 MT7986_PIN(75, "WF0_HB2"),
556 MT7986_PIN(76, "WF0_HB3"),
557 MT7986_PIN(77, "WF0_HB4"),
558 MT7986_PIN(78, "WF0_HB0"),
559 MT7986_PIN(79, "WF0_HB0_B"),
560 MT7986_PIN(80, "WF0_HB5"),
561 MT7986_PIN(81, "WF0_HB6"),
562 MT7986_PIN(82, "WF0_HB7"),
563 MT7986_PIN(83, "WF0_HB8"),
564 MT7986_PIN(84, "WF0_HB9"),
565 MT7986_PIN(85, "WF0_HB10"),
566 MT7986_PIN(86, "WF1_DIG_RESETB"),
567 MT7986_PIN(87, "WF1_CBA_RESETB"),
568 MT7986_PIN(88, "WF1_XO_REQ"),
569 MT7986_PIN(89, "WF1_TOP_CLK"),
570 MT7986_PIN(90, "WF1_TOP_DATA"),
571 MT7986_PIN(91, "WF1_HB1"),
572 MT7986_PIN(92, "WF1_HB2"),
573 MT7986_PIN(93, "WF1_HB3"),
574 MT7986_PIN(94, "WF1_HB4"),
575 MT7986_PIN(95, "WF1_HB0"),
576 MT7986_PIN(96, "WF1_HB0_B"),
577 MT7986_PIN(97, "WF1_HB5"),
578 MT7986_PIN(98, "WF1_HB6"),
579 MT7986_PIN(99, "WF1_HB7"),
580 MT7986_PIN(100, "WF1_HB8"),
581 };
582
583 static const struct mtk_pin_desc mt7986b_pins[] = {
584 MT7986_PIN(0, "SYS_WATCHDOG"),
585 MT7986_PIN(1, "WF2G_LED"),
586 MT7986_PIN(2, "WF5G_LED"),
587 MT7986_PIN(3, "I2C_SCL"),
588 MT7986_PIN(4, "I2C_SDA"),
589 MT7986_PIN(5, "GPIO_0"),
590 MT7986_PIN(6, "GPIO_1"),
591 MT7986_PIN(7, "GPIO_2"),
592 MT7986_PIN(8, "GPIO_3"),
593 MT7986_PIN(9, "GPIO_4"),
594 MT7986_PIN(10, "GPIO_5"),
595 MT7986_PIN(11, "GPIO_6"),
596 MT7986_PIN(12, "GPIO_7"),
597 MT7986_PIN(13, "GPIO_8"),
598 MT7986_PIN(14, "GPIO_9"),
599 MT7986_PIN(15, "GPIO_10"),
600 MT7986_PIN(16, "GPIO_11"),
601 MT7986_PIN(17, "GPIO_12"),
602 MT7986_PIN(18, "GPIO_13"),
603 MT7986_PIN(19, "GPIO_14"),
604 MT7986_PIN(20, "GPIO_15"),
605 MT7986_PIN(21, "PWM0"),
606 MT7986_PIN(22, "PWM1"),
607 MT7986_PIN(23, "SPI0_CLK"),
608 MT7986_PIN(24, "SPI0_MOSI"),
609 MT7986_PIN(25, "SPI0_MISO"),
610 MT7986_PIN(26, "SPI0_CS"),
611 MT7986_PIN(27, "SPI0_HOLD"),
612 MT7986_PIN(28, "SPI0_WP"),
613 MT7986_PIN(29, "SPI1_CLK"),
614 MT7986_PIN(30, "SPI1_MOSI"),
615 MT7986_PIN(31, "SPI1_MISO"),
616 MT7986_PIN(32, "SPI1_CS"),
617 MT7986_PIN(33, "SPI2_CLK"),
618 MT7986_PIN(34, "SPI2_MOSI"),
619 MT7986_PIN(35, "SPI2_MISO"),
620 MT7986_PIN(36, "SPI2_CS"),
621 MT7986_PIN(37, "SPI2_HOLD"),
622 MT7986_PIN(38, "SPI2_WP"),
623 MT7986_PIN(39, "UART0_RXD"),
624 MT7986_PIN(40, "UART0_TXD"),
625 MT7986_NOT_BALLOUT_PIN(41),
626 MT7986_NOT_BALLOUT_PIN(42),
627 MT7986_NOT_BALLOUT_PIN(43),
628 MT7986_NOT_BALLOUT_PIN(44),
629 MT7986_NOT_BALLOUT_PIN(45),
630 MT7986_NOT_BALLOUT_PIN(46),
631 MT7986_NOT_BALLOUT_PIN(47),
632 MT7986_NOT_BALLOUT_PIN(48),
633 MT7986_NOT_BALLOUT_PIN(49),
634 MT7986_NOT_BALLOUT_PIN(50),
635 MT7986_NOT_BALLOUT_PIN(51),
636 MT7986_NOT_BALLOUT_PIN(52),
637 MT7986_NOT_BALLOUT_PIN(53),
638 MT7986_NOT_BALLOUT_PIN(54),
639 MT7986_NOT_BALLOUT_PIN(55),
640 MT7986_NOT_BALLOUT_PIN(56),
641 MT7986_NOT_BALLOUT_PIN(57),
642 MT7986_NOT_BALLOUT_PIN(58),
643 MT7986_NOT_BALLOUT_PIN(59),
644 MT7986_NOT_BALLOUT_PIN(60),
645 MT7986_NOT_BALLOUT_PIN(61),
646 MT7986_NOT_BALLOUT_PIN(62),
647 MT7986_NOT_BALLOUT_PIN(63),
648 MT7986_NOT_BALLOUT_PIN(64),
649 MT7986_NOT_BALLOUT_PIN(65),
650 MT7986_PIN(66, "MT7531_INT"),
651 MT7986_PIN(67, "SMI_MDC"),
652 MT7986_PIN(68, "SMI_MDIO"),
653 MT7986_PIN(69, "WF0_DIG_RESETB"),
654 MT7986_PIN(70, "WF0_CBA_RESETB"),
655 MT7986_PIN(71, "WF0_XO_REQ"),
656 MT7986_PIN(72, "WF0_TOP_CLK"),
657 MT7986_PIN(73, "WF0_TOP_DATA"),
658 MT7986_PIN(74, "WF0_HB1"),
659 MT7986_PIN(75, "WF0_HB2"),
660 MT7986_PIN(76, "WF0_HB3"),
661 MT7986_PIN(77, "WF0_HB4"),
662 MT7986_PIN(78, "WF0_HB0"),
663 MT7986_PIN(79, "WF0_HB0_B"),
664 MT7986_PIN(80, "WF0_HB5"),
665 MT7986_PIN(81, "WF0_HB6"),
666 MT7986_PIN(82, "WF0_HB7"),
667 MT7986_PIN(83, "WF0_HB8"),
668 MT7986_PIN(84, "WF0_HB9"),
669 MT7986_PIN(85, "WF0_HB10"),
670 MT7986_PIN(86, "WF1_DIG_RESETB"),
671 MT7986_PIN(87, "WF1_CBA_RESETB"),
672 MT7986_PIN(88, "WF1_XO_REQ"),
673 MT7986_PIN(89, "WF1_TOP_CLK"),
674 MT7986_PIN(90, "WF1_TOP_DATA"),
675 MT7986_PIN(91, "WF1_HB1"),
676 MT7986_PIN(92, "WF1_HB2"),
677 MT7986_PIN(93, "WF1_HB3"),
678 MT7986_PIN(94, "WF1_HB4"),
679 MT7986_PIN(95, "WF1_HB0"),
680 MT7986_PIN(96, "WF1_HB0_B"),
681 MT7986_PIN(97, "WF1_HB5"),
682 MT7986_PIN(98, "WF1_HB6"),
683 MT7986_PIN(99, "WF1_HB7"),
684 MT7986_PIN(100, "WF1_HB8"),
685 };
686
687 /* List all groups consisting of these pins dedicated to the enablement of
688 * certain hardware block and the corresponding mode for all of the pins.
689 * The hardware probably has multiple combinations of these pinouts.
690 */
691
692 static int mt7986_watchdog_pins[] = { 0, };
693 static int mt7986_watchdog_funcs[] = { 1, };
694
695 static int mt7986_wifi_led_pins[] = { 1, 2, };
696 static int mt7986_wifi_led_funcs[] = { 1, 1, };
697
698 static int mt7986_i2c_pins[] = { 3, 4, };
699 static int mt7986_i2c_funcs[] = { 1, 1, };
700
701 static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
702 static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
703
704 static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
705 static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
706
707 static int mt7986_pwm1_1_pins[] = { 20, };
708 static int mt7986_pwm1_1_funcs[] = { 2, };
709
710 static int mt7986_pwm0_pins[] = { 21, };
711 static int mt7986_pwm0_funcs[] = { 1, };
712
713 static int mt7986_pwm1_0_pins[] = { 22, };
714 static int mt7986_pwm1_0_funcs[] = { 1, };
715
716 static int mt7986_emmc_45_pins[] = {
717 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
718 static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
719
720 static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
721 static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
722
723 static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
724 static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
725
726 static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
727 static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
728
729 static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
730 static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
731
732 static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
733 static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
734
735 static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
736 static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
737
738 static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
739 static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
740
741 static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
742 static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
743
744 static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
745 static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
746
747 static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
748 static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
749
750 static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
751 static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
752
753 static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
754 static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
755
756 static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
757 static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
758
759 static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
760 static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
761
762 static int mt7986_uart0_pins[] = { 39, 40, };
763 static int mt7986_uart0_funcs[] = { 1, 1, };
764
765 static int mt7986_pcie_reset_pins[] = { 41, };
766 static int mt7986_pcie_reset_funcs[] = { 1, };
767
768 static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
769 static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
770
771 static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
772 static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
773
774 static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
775 static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
776
777 static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
778 static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
779
780 static int mt7986_emmc_51_pins[] = {
781 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
782 static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
783
784 static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
785 static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
786
787 static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
788 static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
789
790 static int mt7986_switch_int_pins[] = { 66, };
791 static int mt7986_switch_int_funcs[] = { 1, };
792
793 static int mt7986_mdc_mdio_pins[] = { 67, 68, };
794 static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
795
796 static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
797 static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
798
799 static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
800 static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
801
802 static int mt7986_wf_dbdc_pins[] = {
803 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
804 static int mt7986_wf_dbdc_funcs[] = {
805 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
806
807 static int mt7986_pcie_clk_pins[] = { 9, };
808 static int mt7986_pcie_clk_funcs[] = { 1, };
809
810 static int mt7986_pcie_wake_pins[] = { 10, };
811 static int mt7986_pcie_wake_funcs[] = { 1, };
812
813 static const struct group_desc mt7986_groups[] = {
814 PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
815 PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
816 PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
817 PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
818 PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
819 PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
820 PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
821 PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
822 PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
823 PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
824 PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
825 PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
826 PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
827 PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
828 PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
829 PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
830 PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
831 PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
832 PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
833 PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
834 PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
835 PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
836 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
837 PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
838 PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
839 PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
840 PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
841 PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
842 PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
843 PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
844 PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
845 PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
846 PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
847 PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
848 PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
849 PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
850 PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
851 PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
852 PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
853 };
854
855 /* Joint those groups owning the same capability in user point of view which
856 * allows that people tend to use through the device tree.
857 */
858
859 static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
860 static const char *mt7986_emmc_groups[] = {
861 "emmc_45", "emmc_51", };
862 static const char *mt7986_ethernet_groups[] = {
863 "switch_int", "mdc_mdio", };
864 static const char *mt7986_i2c_groups[] = { "i2c", };
865 static const char *mt7986_led_groups[] = { "wifi_led", };
866 static const char *mt7986_flash_groups[] = { "snfi", };
867 static const char *mt7986_pcie_groups[] = {
868 "pcie_clk", "pcie_wake", "pcie_pereset" };
869 static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
870 static const char *mt7986_spi_groups[] = {
871 "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
872 static const char *mt7986_uart_groups[] = {
873 "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
874 "uart1_2_rx_tx", "uart1_2_cts_rts",
875 "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
876 "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
877 };
878 static const char *mt7986_wdt_groups[] = { "watchdog", };
879 static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
880
881 static const struct function_desc mt7986_functions[] = {
882 {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
883 {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
884 {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
885 {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
886 {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
887 {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
888 {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
889 {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
890 {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
891 {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
892 {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
893 {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
894 };
895
896 static const struct mtk_eint_hw mt7986a_eint_hw = {
897 .port_mask = 7,
898 .ports = 7,
899 .ap_num = ARRAY_SIZE(mt7986a_pins),
900 .db_cnt = 16,
901 .db_time = debounce_time_mt6765,
902 };
903
904 static const struct mtk_eint_hw mt7986b_eint_hw = {
905 .port_mask = 7,
906 .ports = 7,
907 .ap_num = ARRAY_SIZE(mt7986b_pins),
908 .db_cnt = 16,
909 .db_time = debounce_time_mt6765,
910 };
911
912 static struct mtk_pin_soc mt7986a_data = {
913 .reg_cal = mt7986_reg_cals,
914 .pins = mt7986a_pins,
915 .npins = ARRAY_SIZE(mt7986a_pins),
916 .grps = mt7986_groups,
917 .ngrps = ARRAY_SIZE(mt7986_groups),
918 .funcs = mt7986_functions,
919 .nfuncs = ARRAY_SIZE(mt7986_functions),
920 .eint_hw = &mt7986a_eint_hw,
921 .gpio_m = 0,
922 .ies_present = false,
923 .base_names = mt7986_pinctrl_register_base_names,
924 .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
925 .bias_disable_set = mtk_pinconf_bias_disable_set,
926 .bias_disable_get = mtk_pinconf_bias_disable_get,
927 .bias_set = mtk_pinconf_bias_set,
928 .bias_get = mtk_pinconf_bias_get,
929 .pull_type = mt7986_pull_type,
930 .bias_set_combo = mtk_pinconf_bias_set_combo,
931 .bias_get_combo = mtk_pinconf_bias_get_combo,
932 .drive_set = mtk_pinconf_drive_set_rev1,
933 .drive_get = mtk_pinconf_drive_get_rev1,
934 .adv_pull_get = mtk_pinconf_adv_pull_get,
935 .adv_pull_set = mtk_pinconf_adv_pull_set,
936 };
937
938 static struct mtk_pin_soc mt7986b_data = {
939 .reg_cal = mt7986_reg_cals,
940 .pins = mt7986b_pins,
941 .npins = ARRAY_SIZE(mt7986b_pins),
942 .grps = mt7986_groups,
943 .ngrps = ARRAY_SIZE(mt7986_groups),
944 .funcs = mt7986_functions,
945 .nfuncs = ARRAY_SIZE(mt7986_functions),
946 .eint_hw = &mt7986b_eint_hw,
947 .gpio_m = 0,
948 .ies_present = false,
949 .base_names = mt7986_pinctrl_register_base_names,
950 .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
951 .bias_disable_set = mtk_pinconf_bias_disable_set,
952 .bias_disable_get = mtk_pinconf_bias_disable_get,
953 .bias_set = mtk_pinconf_bias_set,
954 .bias_get = mtk_pinconf_bias_get,
955 .pull_type = mt7986_pull_type,
956 .bias_set_combo = mtk_pinconf_bias_set_combo,
957 .bias_get_combo = mtk_pinconf_bias_get_combo,
958 .drive_set = mtk_pinconf_drive_set_rev1,
959 .drive_get = mtk_pinconf_drive_get_rev1,
960 .adv_pull_get = mtk_pinconf_adv_pull_get,
961 .adv_pull_set = mtk_pinconf_adv_pull_set,
962 };
963
964 static const struct of_device_id mt7986a_pinctrl_of_match[] = {
965 {.compatible = "mediatek,mt7986a-pinctrl",},
966 {}
967 };
968
969 static const struct of_device_id mt7986b_pinctrl_of_match[] = {
970 {.compatible = "mediatek,mt7986b-pinctrl",},
971 {}
972 };
973
mt7986a_pinctrl_probe(struct platform_device * pdev)974 static int mt7986a_pinctrl_probe(struct platform_device *pdev)
975 {
976 return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
977 }
978
mt7986b_pinctrl_probe(struct platform_device * pdev)979 static int mt7986b_pinctrl_probe(struct platform_device *pdev)
980 {
981 return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
982 }
983
984 static struct platform_driver mt7986a_pinctrl_driver = {
985 .driver = {
986 .name = "mt7986a-pinctrl",
987 .of_match_table = mt7986a_pinctrl_of_match,
988 },
989 .probe = mt7986a_pinctrl_probe,
990 };
991
992 static struct platform_driver mt7986b_pinctrl_driver = {
993 .driver = {
994 .name = "mt7986b-pinctrl",
995 .of_match_table = mt7986b_pinctrl_of_match,
996 },
997 .probe = mt7986b_pinctrl_probe,
998 };
999
mt7986a_pinctrl_init(void)1000 static int __init mt7986a_pinctrl_init(void)
1001 {
1002 return platform_driver_register(&mt7986a_pinctrl_driver);
1003 }
1004
mt7986b_pinctrl_init(void)1005 static int __init mt7986b_pinctrl_init(void)
1006 {
1007 return platform_driver_register(&mt7986b_pinctrl_driver);
1008 }
1009
1010 arch_initcall(mt7986a_pinctrl_init);
1011 arch_initcall(mt7986b_pinctrl_init);
1012