1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2017-2018 MediaTek Inc.
4  *
5  * Author: Sean Wang <sean.wang@mediatek.com>
6  *
7  */
8 
9 #include "pinctrl-moore.h"
10 
11 #define MT7622_PIN(_number, _name)					\
12 	MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
13 
14 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
15 	PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
16 	PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
17 	PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
18 	PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
19 	PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
20 	PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
21 	PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
22 	PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
23 	PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
24 	PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
25 	PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
26 	PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
27 	PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
28 	PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
29 	PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
30 	PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
31 	PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
32 	PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
33 	PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
34 	PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
35 	PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
36 	PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
37 	PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
38 	PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
39 	PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
40 	PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
41 };
42 
43 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
44 	PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
45 };
46 
47 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
48 	PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
49 };
50 
51 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
52 	PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
53 };
54 
55 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
56 	PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
57 	PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
58 	PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
59 	PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
60 	PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
61 	PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
62 	PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
63 };
64 
65 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
66 	PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
67 	PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
68 	PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
69 	PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
70 	PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
71 	PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
72 	PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
73 };
74 
75 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
76 	PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
77 	PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
78 	PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
79 	PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
80 	PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
81 	PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
82 	PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
83 };
84 
85 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
86 	PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
87 	PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
88 	PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
89 	PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
90 	PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
91 	PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
92 	PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
93 };
94 
95 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
96 	PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
97 	PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
98 	PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
99 	PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
100 	PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
101 	PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
102 	PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
103 };
104 
105 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
106 	PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
107 	PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
108 	PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
109 	PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
110 	PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
111 	PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
112 	PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
113 };
114 
115 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
116 	PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
117 	PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
118 	PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
119 	PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
120 	PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
121 	PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
122 	PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
123 };
124 
125 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
126 	PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
127 	PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
128 	PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
129 	PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
130 	PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
131 	PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
132 	PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
133 	PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
134 	PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
135 	PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
136 	PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
137 	PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
138 };
139 
140 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
141 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
142 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
143 	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
144 	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
145 	[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
146 	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
147 	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
148 	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
149 	[PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
150 	[PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
151 	[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
152 	[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
153 };
154 
155 static const struct mtk_pin_desc mt7622_pins[] = {
156 	MT7622_PIN(0, "GPIO_A"),
157 	MT7622_PIN(1, "I2S1_IN"),
158 	MT7622_PIN(2, "I2S1_OUT"),
159 	MT7622_PIN(3, "I2S_BCLK"),
160 	MT7622_PIN(4, "I2S_WS"),
161 	MT7622_PIN(5, "I2S_MCLK"),
162 	MT7622_PIN(6, "TXD0"),
163 	MT7622_PIN(7, "RXD0"),
164 	MT7622_PIN(8, "SPI_WP"),
165 	MT7622_PIN(9, "SPI_HOLD"),
166 	MT7622_PIN(10, "SPI_CLK"),
167 	MT7622_PIN(11, "SPI_MOSI"),
168 	MT7622_PIN(12, "SPI_MISO"),
169 	MT7622_PIN(13, "SPI_CS"),
170 	MT7622_PIN(14, "I2C_SDA"),
171 	MT7622_PIN(15, "I2C_SCL"),
172 	MT7622_PIN(16, "I2S2_IN"),
173 	MT7622_PIN(17, "I2S3_IN"),
174 	MT7622_PIN(18, "I2S4_IN"),
175 	MT7622_PIN(19, "I2S2_OUT"),
176 	MT7622_PIN(20, "I2S3_OUT"),
177 	MT7622_PIN(21, "I2S4_OUT"),
178 	MT7622_PIN(22, "GPIO_B"),
179 	MT7622_PIN(23, "MDC"),
180 	MT7622_PIN(24, "MDIO"),
181 	MT7622_PIN(25, "G2_TXD0"),
182 	MT7622_PIN(26, "G2_TXD1"),
183 	MT7622_PIN(27, "G2_TXD2"),
184 	MT7622_PIN(28, "G2_TXD3"),
185 	MT7622_PIN(29, "G2_TXEN"),
186 	MT7622_PIN(30, "G2_TXC"),
187 	MT7622_PIN(31, "G2_RXD0"),
188 	MT7622_PIN(32, "G2_RXD1"),
189 	MT7622_PIN(33, "G2_RXD2"),
190 	MT7622_PIN(34, "G2_RXD3"),
191 	MT7622_PIN(35, "G2_RXDV"),
192 	MT7622_PIN(36, "G2_RXC"),
193 	MT7622_PIN(37, "NCEB"),
194 	MT7622_PIN(38, "NWEB"),
195 	MT7622_PIN(39, "NREB"),
196 	MT7622_PIN(40, "NDL4"),
197 	MT7622_PIN(41, "NDL5"),
198 	MT7622_PIN(42, "NDL6"),
199 	MT7622_PIN(43, "NDL7"),
200 	MT7622_PIN(44, "NRB"),
201 	MT7622_PIN(45, "NCLE"),
202 	MT7622_PIN(46, "NALE"),
203 	MT7622_PIN(47, "NDL0"),
204 	MT7622_PIN(48, "NDL1"),
205 	MT7622_PIN(49, "NDL2"),
206 	MT7622_PIN(50, "NDL3"),
207 	MT7622_PIN(51, "MDI_TP_P0"),
208 	MT7622_PIN(52, "MDI_TN_P0"),
209 	MT7622_PIN(53, "MDI_RP_P0"),
210 	MT7622_PIN(54, "MDI_RN_P0"),
211 	MT7622_PIN(55, "MDI_TP_P1"),
212 	MT7622_PIN(56, "MDI_TN_P1"),
213 	MT7622_PIN(57, "MDI_RP_P1"),
214 	MT7622_PIN(58, "MDI_RN_P1"),
215 	MT7622_PIN(59, "MDI_RP_P2"),
216 	MT7622_PIN(60, "MDI_RN_P2"),
217 	MT7622_PIN(61, "MDI_TP_P2"),
218 	MT7622_PIN(62, "MDI_TN_P2"),
219 	MT7622_PIN(63, "MDI_TP_P3"),
220 	MT7622_PIN(64, "MDI_TN_P3"),
221 	MT7622_PIN(65, "MDI_RP_P3"),
222 	MT7622_PIN(66, "MDI_RN_P3"),
223 	MT7622_PIN(67, "MDI_RP_P4"),
224 	MT7622_PIN(68, "MDI_RN_P4"),
225 	MT7622_PIN(69, "MDI_TP_P4"),
226 	MT7622_PIN(70, "MDI_TN_P4"),
227 	MT7622_PIN(71, "PMIC_SCL"),
228 	MT7622_PIN(72, "PMIC_SDA"),
229 	MT7622_PIN(73, "SPIC1_CLK"),
230 	MT7622_PIN(74, "SPIC1_MOSI"),
231 	MT7622_PIN(75, "SPIC1_MISO"),
232 	MT7622_PIN(76, "SPIC1_CS"),
233 	MT7622_PIN(77, "GPIO_D"),
234 	MT7622_PIN(78, "WATCHDOG"),
235 	MT7622_PIN(79, "RTS3_N"),
236 	MT7622_PIN(80, "CTS3_N"),
237 	MT7622_PIN(81, "TXD3"),
238 	MT7622_PIN(82, "RXD3"),
239 	MT7622_PIN(83, "PERST0_N"),
240 	MT7622_PIN(84, "PERST1_N"),
241 	MT7622_PIN(85, "WLED_N"),
242 	MT7622_PIN(86, "EPHY_LED0_N"),
243 	MT7622_PIN(87, "AUXIN0"),
244 	MT7622_PIN(88, "AUXIN1"),
245 	MT7622_PIN(89, "AUXIN2"),
246 	MT7622_PIN(90, "AUXIN3"),
247 	MT7622_PIN(91, "TXD4"),
248 	MT7622_PIN(92, "RXD4"),
249 	MT7622_PIN(93, "RTS4_N"),
250 	MT7622_PIN(94, "CTS4_N"),
251 	MT7622_PIN(95, "PWM1"),
252 	MT7622_PIN(96, "PWM2"),
253 	MT7622_PIN(97, "PWM3"),
254 	MT7622_PIN(98, "PWM4"),
255 	MT7622_PIN(99, "PWM5"),
256 	MT7622_PIN(100, "PWM6"),
257 	MT7622_PIN(101, "PWM7"),
258 	MT7622_PIN(102, "GPIO_E"),
259 };
260 
261 /* List all groups consisting of these pins dedicated to the enablement of
262  * certain hardware block and the corresponding mode for all of the pins. The
263  * hardware probably has multiple combinations of these pinouts.
264  */
265 
266 /* ANTSEL */
267 static int mt7622_antsel0_pins[] = { 91, };
268 static int mt7622_antsel0_funcs[] = { 5, };
269 static int mt7622_antsel1_pins[] = { 92, };
270 static int mt7622_antsel1_funcs[] = { 5, };
271 static int mt7622_antsel2_pins[] = { 93, };
272 static int mt7622_antsel2_funcs[] = { 5, };
273 static int mt7622_antsel3_pins[] = { 94, };
274 static int mt7622_antsel3_funcs[] = { 5, };
275 static int mt7622_antsel4_pins[] = { 95, };
276 static int mt7622_antsel4_funcs[] = { 5, };
277 static int mt7622_antsel5_pins[] = { 96, };
278 static int mt7622_antsel5_funcs[] = { 5, };
279 static int mt7622_antsel6_pins[] = { 97, };
280 static int mt7622_antsel6_funcs[] = { 5, };
281 static int mt7622_antsel7_pins[] = { 98, };
282 static int mt7622_antsel7_funcs[] = { 5, };
283 static int mt7622_antsel8_pins[] = { 99, };
284 static int mt7622_antsel8_funcs[] = { 5, };
285 static int mt7622_antsel9_pins[] = { 100, };
286 static int mt7622_antsel9_funcs[] = { 5, };
287 static int mt7622_antsel10_pins[] = { 101, };
288 static int mt7622_antsel10_funcs[] = { 5, };
289 static int mt7622_antsel11_pins[] = { 102, };
290 static int mt7622_antsel11_funcs[] = { 5, };
291 static int mt7622_antsel12_pins[] = { 73, };
292 static int mt7622_antsel12_funcs[] = { 5, };
293 static int mt7622_antsel13_pins[] = { 74, };
294 static int mt7622_antsel13_funcs[] = { 5, };
295 static int mt7622_antsel14_pins[] = { 75, };
296 static int mt7622_antsel14_funcs[] = { 5, };
297 static int mt7622_antsel15_pins[] = { 76, };
298 static int mt7622_antsel15_funcs[] = { 5, };
299 static int mt7622_antsel16_pins[] = { 77, };
300 static int mt7622_antsel16_funcs[] = { 5, };
301 static int mt7622_antsel17_pins[] = { 22, };
302 static int mt7622_antsel17_funcs[] = { 5, };
303 static int mt7622_antsel18_pins[] = { 79, };
304 static int mt7622_antsel18_funcs[] = { 5, };
305 static int mt7622_antsel19_pins[] = { 80, };
306 static int mt7622_antsel19_funcs[] = { 5, };
307 static int mt7622_antsel20_pins[] = { 81, };
308 static int mt7622_antsel20_funcs[] = { 5, };
309 static int mt7622_antsel21_pins[] = { 82, };
310 static int mt7622_antsel21_funcs[] = { 5, };
311 static int mt7622_antsel22_pins[] = { 14, };
312 static int mt7622_antsel22_funcs[] = { 5, };
313 static int mt7622_antsel23_pins[] = { 15, };
314 static int mt7622_antsel23_funcs[] = { 5, };
315 static int mt7622_antsel24_pins[] = { 16, };
316 static int mt7622_antsel24_funcs[] = { 5, };
317 static int mt7622_antsel25_pins[] = { 17, };
318 static int mt7622_antsel25_funcs[] = { 5, };
319 static int mt7622_antsel26_pins[] = { 18, };
320 static int mt7622_antsel26_funcs[] = { 5, };
321 static int mt7622_antsel27_pins[] = { 19, };
322 static int mt7622_antsel27_funcs[] = { 5, };
323 static int mt7622_antsel28_pins[] = { 20, };
324 static int mt7622_antsel28_funcs[] = { 5, };
325 static int mt7622_antsel29_pins[] = { 21, };
326 static int mt7622_antsel29_funcs[] = { 5, };
327 
328 /* EMMC */
329 static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
330 static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
331 
332 static int mt7622_emmc_rst_pins[] = { 37, };
333 static int mt7622_emmc_rst_funcs[] = { 1, };
334 
335 /* LED for EPHY */
336 static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
337 static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
338 static int mt7622_ephy0_led_pins[] = { 86, };
339 static int mt7622_ephy0_led_funcs[] = { 0, };
340 static int mt7622_ephy1_led_pins[] = { 91, };
341 static int mt7622_ephy1_led_funcs[] = { 2, };
342 static int mt7622_ephy2_led_pins[] = { 92, };
343 static int mt7622_ephy2_led_funcs[] = { 2, };
344 static int mt7622_ephy3_led_pins[] = { 93, };
345 static int mt7622_ephy3_led_funcs[] = { 2, };
346 static int mt7622_ephy4_led_pins[] = { 94, };
347 static int mt7622_ephy4_led_funcs[] = { 2, };
348 
349 /* Embedded Switch */
350 static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
351 				 62, 63, 64, 65, 66, 67, 68, 69, 70, };
352 static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
353 				  0, 0, 0, 0, 0, 0, 0, 0, 0, };
354 static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
355 static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
356 static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
357 					  68, 69, 70, };
358 static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
359 					   0, 0, 0, };
360 /* RGMII via ESW */
361 static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
362 					   67, 68, 69, 70, };
363 static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
364 					    0, };
365 
366 /* RGMII via GMAC1 */
367 static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
368 					     67, 68, 69, 70, };
369 static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
370 					      2, };
371 
372 /* RGMII via GMAC2 */
373 static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
374 					     33, 34, 35, 36, };
375 static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
376 					      0, };
377 
378 /* I2C */
379 static int mt7622_i2c0_pins[] = { 14, 15, };
380 static int mt7622_i2c0_funcs[] = { 0, 0, };
381 static int mt7622_i2c1_0_pins[] = { 55, 56, };
382 static int mt7622_i2c1_0_funcs[] = { 0, 0, };
383 static int mt7622_i2c1_1_pins[] = { 73, 74, };
384 static int mt7622_i2c1_1_funcs[] = { 3, 3, };
385 static int mt7622_i2c1_2_pins[] = { 87, 88, };
386 static int mt7622_i2c1_2_funcs[] = { 0, 0, };
387 static int mt7622_i2c2_0_pins[] = { 57, 58, };
388 static int mt7622_i2c2_0_funcs[] = { 0, 0, };
389 static int mt7622_i2c2_1_pins[] = { 75, 76, };
390 static int mt7622_i2c2_1_funcs[] = { 3, 3, };
391 static int mt7622_i2c2_2_pins[] = { 89, 90, };
392 static int mt7622_i2c2_2_funcs[] = { 0, 0, };
393 
394 /* I2S */
395 static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
396 static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
397 static int mt7622_i2s1_in_data_pins[] = { 1, };
398 static int mt7622_i2s1_in_data_funcs[] = { 0, };
399 static int mt7622_i2s2_in_data_pins[] = { 16, };
400 static int mt7622_i2s2_in_data_funcs[] = { 0, };
401 static int mt7622_i2s3_in_data_pins[] = { 17, };
402 static int mt7622_i2s3_in_data_funcs[] = { 0, };
403 static int mt7622_i2s4_in_data_pins[] = { 18, };
404 static int mt7622_i2s4_in_data_funcs[] = { 0, };
405 static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
406 static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
407 static int mt7622_i2s1_out_data_pins[] = { 2, };
408 static int mt7622_i2s1_out_data_funcs[] = { 0, };
409 static int mt7622_i2s2_out_data_pins[] = { 19, };
410 static int mt7622_i2s2_out_data_funcs[] = { 0, };
411 static int mt7622_i2s3_out_data_pins[] = { 20, };
412 static int mt7622_i2s3_out_data_funcs[] = { 0, };
413 static int mt7622_i2s4_out_data_pins[] = { 21, };
414 static int mt7622_i2s4_out_data_funcs[] = { 0, };
415 
416 /* IR */
417 static int mt7622_ir_0_tx_pins[] = { 16, };
418 static int mt7622_ir_0_tx_funcs[] = { 4, };
419 static int mt7622_ir_1_tx_pins[] = { 59, };
420 static int mt7622_ir_1_tx_funcs[] = { 5, };
421 static int mt7622_ir_2_tx_pins[] = { 99, };
422 static int mt7622_ir_2_tx_funcs[] = { 3, };
423 static int mt7622_ir_0_rx_pins[] = { 17, };
424 static int mt7622_ir_0_rx_funcs[] = { 4, };
425 static int mt7622_ir_1_rx_pins[] = { 60, };
426 static int mt7622_ir_1_rx_funcs[] = { 5, };
427 static int mt7622_ir_2_rx_pins[] = { 100, };
428 static int mt7622_ir_2_rx_funcs[] = { 3, };
429 
430 /* MDIO */
431 static int mt7622_mdc_mdio_pins[] = { 23, 24, };
432 static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
433 
434 /* PCIE */
435 static int mt7622_pcie0_0_waken_pins[] = { 14, };
436 static int mt7622_pcie0_0_waken_funcs[] = { 2, };
437 static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
438 static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
439 static int mt7622_pcie0_1_waken_pins[] = { 79, };
440 static int mt7622_pcie0_1_waken_funcs[] = { 4, };
441 static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
442 static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
443 static int mt7622_pcie1_0_waken_pins[] = { 14, };
444 static int mt7622_pcie1_0_waken_funcs[] = { 3, };
445 static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
446 static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
447 
448 static int mt7622_pcie0_pad_perst_pins[] = { 83, };
449 static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
450 static int mt7622_pcie1_pad_perst_pins[] = { 84, };
451 static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
452 
453 /* PMIC bus */
454 static int mt7622_pmic_bus_pins[] = { 71, 72, };
455 static int mt7622_pmic_bus_funcs[] = { 0, 0, };
456 
457 /* Parallel NAND */
458 static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
459 				   48, 49, 50, };
460 static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
461 				    0, };
462 
463 /* PWM */
464 static int mt7622_pwm_ch1_0_pins[] = { 51, };
465 static int mt7622_pwm_ch1_0_funcs[] = { 3, };
466 static int mt7622_pwm_ch1_1_pins[] = { 73, };
467 static int mt7622_pwm_ch1_1_funcs[] = { 4, };
468 static int mt7622_pwm_ch1_2_pins[] = { 95, };
469 static int mt7622_pwm_ch1_2_funcs[] = { 0, };
470 static int mt7622_pwm_ch2_0_pins[] = { 52, };
471 static int mt7622_pwm_ch2_0_funcs[] = { 3, };
472 static int mt7622_pwm_ch2_1_pins[] = { 74, };
473 static int mt7622_pwm_ch2_1_funcs[] = { 4, };
474 static int mt7622_pwm_ch2_2_pins[] = { 96, };
475 static int mt7622_pwm_ch2_2_funcs[] = { 0, };
476 static int mt7622_pwm_ch3_0_pins[] = { 53, };
477 static int mt7622_pwm_ch3_0_funcs[] = { 3, };
478 static int mt7622_pwm_ch3_1_pins[] = { 75, };
479 static int mt7622_pwm_ch3_1_funcs[] = { 4, };
480 static int mt7622_pwm_ch3_2_pins[] = { 97, };
481 static int mt7622_pwm_ch3_2_funcs[] = { 0, };
482 static int mt7622_pwm_ch4_0_pins[] = { 54, };
483 static int mt7622_pwm_ch4_0_funcs[] = { 3, };
484 static int mt7622_pwm_ch4_1_pins[] = { 67, };
485 static int mt7622_pwm_ch4_1_funcs[] = { 3, };
486 static int mt7622_pwm_ch4_2_pins[] = { 76, };
487 static int mt7622_pwm_ch4_2_funcs[] = { 4, };
488 static int mt7622_pwm_ch4_3_pins[] = { 98, };
489 static int mt7622_pwm_ch4_3_funcs[] = { 0, };
490 static int mt7622_pwm_ch5_0_pins[] = { 68, };
491 static int mt7622_pwm_ch5_0_funcs[] = { 3, };
492 static int mt7622_pwm_ch5_1_pins[] = { 77, };
493 static int mt7622_pwm_ch5_1_funcs[] = { 4, };
494 static int mt7622_pwm_ch5_2_pins[] = { 99, };
495 static int mt7622_pwm_ch5_2_funcs[] = { 0, };
496 static int mt7622_pwm_ch6_0_pins[] = { 69, };
497 static int mt7622_pwm_ch6_0_funcs[] = { 3, };
498 static int mt7622_pwm_ch6_1_pins[] = { 78, };
499 static int mt7622_pwm_ch6_1_funcs[] = { 4, };
500 static int mt7622_pwm_ch6_2_pins[] = { 81, };
501 static int mt7622_pwm_ch6_2_funcs[] = { 4, };
502 static int mt7622_pwm_ch6_3_pins[] = { 100, };
503 static int mt7622_pwm_ch6_3_funcs[] = { 0, };
504 
505 /* SD */
506 static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
507 static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
508 static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
509 static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
510 
511 /* Serial NAND */
512 static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
513 static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
514 
515 /* SPI NOR */
516 static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
517 static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
518 
519 /* SPIC */
520 static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
521 static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
522 static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
523 static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
524 static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
525 static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
526 static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
527 static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
528 static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
529 static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
530 static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
531 static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
532 
533 /* TDM */
534 static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
535 static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
536 static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
537 static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
538 static int mt7622_tdm_0_out_data_pins[] = { 20, };
539 static int mt7622_tdm_0_out_data_funcs[] = { 3, };
540 static int mt7622_tdm_0_in_data_pins[] = { 21, };
541 static int mt7622_tdm_0_in_data_funcs[] = { 3, };
542 static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
543 static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
544 static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
545 static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
546 static int mt7622_tdm_1_out_data_pins[] = { 55, };
547 static int mt7622_tdm_1_out_data_funcs[] = { 3, };
548 static int mt7622_tdm_1_in_data_pins[] = { 56, };
549 static int mt7622_tdm_1_in_data_funcs[] = { 3, };
550 
551 /* UART */
552 static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
553 static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
554 static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
555 static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
556 static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
557 static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
558 static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
559 static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
560 static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
561 static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
562 static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
563 static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
564 static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
565 static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
566 static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
567 static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
568 static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
569 static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
570 static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
571 static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
572 static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
573 static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
574 static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
575 static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
576 static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
577 static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
578 static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
579 static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
580 static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
581 static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
582 static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
583 static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
584 static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
585 static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
586 static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
587 static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
588 static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
589 static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
590 static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
591 static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
592 
593 /* Watchdog */
594 static int mt7622_watchdog_pins[] = { 78, };
595 static int mt7622_watchdog_funcs[] = { 0, };
596 
597 /* WLAN LED */
598 static int mt7622_wled_pins[] = { 85, };
599 static int mt7622_wled_funcs[] = { 0, };
600 
601 static const struct group_desc mt7622_groups[] = {
602 	PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
603 	PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
604 	PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
605 	PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
606 	PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
607 	PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
608 	PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
609 	PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
610 	PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
611 	PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
612 	PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
613 	PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
614 	PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
615 	PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
616 	PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
617 	PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
618 	PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
619 	PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
620 	PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
621 	PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
622 	PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
623 	PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
624 	PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
625 	PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
626 	PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
627 	PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
628 	PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
629 	PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
630 	PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
631 	PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
632 	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
633 	PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
634 	PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
635 	PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
636 	PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
637 	PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
638 	PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
639 	PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
640 	PINCTRL_PIN_GROUP("esw", mt7622_esw),
641 	PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
642 	PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
643 	PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
644 	PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
645 	PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
646 	PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
647 	PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
648 	PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
649 	PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
650 	PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
651 	PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
652 	PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
653 	PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
654 	PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
655 	PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
656 	PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
657 	PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
658 	PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
659 	PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
660 	PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
661 	PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
662 	PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
663 	PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
664 	PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
665 	PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
666 	PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
667 	PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
668 	PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
669 	PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
670 	PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
671 	PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
672 	PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
673 	PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
674 	PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
675 	PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
676 	PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
677 	PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
678 	PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
679 	PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
680 	PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
681 	PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
682 	PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
683 	PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
684 	PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
685 	PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
686 	PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
687 	PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
688 	PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
689 	PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
690 	PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
691 	PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
692 	PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
693 	PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
694 	PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
695 	PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
696 	PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
697 	PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
698 	PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
699 	PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
700 	PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
701 	PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
702 	PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
703 	PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
704 	PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
705 	PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
706 	PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
707 	PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
708 	PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
709 	PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
710 	PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
711 			  mt7622_tdm_0_out_mclk_bclk_ws),
712 	PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
713 			  mt7622_tdm_0_in_mclk_bclk_ws),
714 	PINCTRL_PIN_GROUP("tdm_0_out_data",  mt7622_tdm_0_out_data),
715 	PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
716 	PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
717 			  mt7622_tdm_1_out_mclk_bclk_ws),
718 	PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
719 			  mt7622_tdm_1_in_mclk_bclk_ws),
720 	PINCTRL_PIN_GROUP("tdm_1_out_data",  mt7622_tdm_1_out_data),
721 	PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
722 	PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
723 	PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
724 	PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
725 	PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
726 	PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
727 	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
728 	PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
729 	PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
730 	PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
731 	PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
732 	PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
733 	PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
734 	PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
735 	PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
736 	PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
737 	PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
738 	PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
739 	PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
740 	PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
741 	PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
742 	PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
743 	PINCTRL_PIN_GROUP("wled", mt7622_wled),
744 };
745 
746 /* Joint those groups owning the same capability in user point of view which
747  * allows that people tend to use through the device tree.
748  */
749 static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
750 					      "antsel3", "antsel4", "antsel5",
751 					      "antsel6", "antsel7", "antsel8",
752 					      "antsel9", "antsel10", "antsel11",
753 					      "antsel12", "antsel13", "antsel14",
754 					      "antsel15", "antsel16", "antsel17",
755 					      "antsel18", "antsel19", "antsel20",
756 					      "antsel21", "antsel22", "antsel23",
757 					      "antsel24", "antsel25", "antsel26",
758 					      "antsel27", "antsel28", "antsel29",};
759 static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
760 static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
761 						"esw_p2_p3_p4", "mdc_mdio",
762 						"rgmii_via_gmac1",
763 						"rgmii_via_gmac2",
764 						"rgmii_via_esw", };
765 static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
766 					   "i2c1_2", "i2c2_0", "i2c2_1",
767 					   "i2c2_2", };
768 static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
769 					   "i2s_in_mclk_bclk_ws",
770 					   "i2s1_in_data", "i2s2_in_data",
771 					   "i2s3_in_data", "i2s4_in_data",
772 					   "i2s1_out_data", "i2s2_out_data",
773 					   "i2s3_out_data", "i2s4_out_data", };
774 static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
775 					  "ir_0_rx", "ir_1_rx", "ir_2_rx"};
776 static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
777 					   "ephy1_led", "ephy2_led",
778 					   "ephy3_led", "ephy4_led",
779 					   "wled", };
780 static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
781 static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
782 					    "pcie0_1_waken", "pcie0_1_clkreq",
783 					    "pcie1_0_waken", "pcie1_0_clkreq",
784 					    "pcie0_pad_perst",
785 					    "pcie1_pad_perst", };
786 static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
787 static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
788 					   "pwm_ch1_2", "pwm_ch2_0",
789 					   "pwm_ch2_1", "pwm_ch2_2",
790 					   "pwm_ch3_0", "pwm_ch3_1",
791 					   "pwm_ch3_2", "pwm_ch4_0",
792 					   "pwm_ch4_1", "pwm_ch4_2",
793 					   "pwm_ch4_3", "pwm_ch5_0",
794 					   "pwm_ch5_1", "pwm_ch5_2",
795 					   "pwm_ch6_0", "pwm_ch6_1",
796 					   "pwm_ch6_2", "pwm_ch6_3", };
797 static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
798 static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
799 					    "spic1_1", "spic2_0",
800 					    "spic2_0_wp_hold", };
801 static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
802 					   "tdm_0_in_mclk_bclk_ws",
803 					   "tdm_0_out_data",
804 					   "tdm_0_in_data",
805 					   "tdm_1_out_mclk_bclk_ws",
806 					   "tdm_1_in_mclk_bclk_ws",
807 					   "tdm_1_out_data",
808 					   "tdm_1_in_data", };
809 
810 static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
811 					    "uart1_0_tx_rx", "uart1_0_rts_cts",
812 					    "uart1_1_tx_rx", "uart1_1_rts_cts",
813 					    "uart2_0_tx_rx", "uart2_0_rts_cts",
814 					    "uart2_1_tx_rx", "uart2_1_rts_cts",
815 					    "uart2_2_tx_rx", "uart2_2_rts_cts",
816 					    "uart2_3_tx_rx",
817 					    "uart3_0_tx_rx",
818 					    "uart3_1_tx_rx", "uart3_1_rts_cts",
819 					    "uart4_0_tx_rx",
820 					    "uart4_1_tx_rx", "uart4_1_rts_cts",
821 					    "uart4_2_tx_rx",
822 					    "uart4_2_rts_cts",};
823 static const char *mt7622_wdt_groups[] = { "watchdog", };
824 
825 static const struct function_desc mt7622_functions[] = {
826 	{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
827 	{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
828 	{"eth",	mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
829 	{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
830 	{"i2s",	mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
831 	{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
832 	{"led",	mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
833 	{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
834 	{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
835 	{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
836 	{"pwm",	mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
837 	{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
838 	{"spi",	mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
839 	{"tdm",	mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
840 	{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
841 	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
842 };
843 
844 static const struct mtk_eint_hw mt7622_eint_hw = {
845 	.port_mask = 7,
846 	.ports     = 7,
847 	.ap_num    = ARRAY_SIZE(mt7622_pins),
848 	.db_cnt    = 20,
849 };
850 
851 static const struct mtk_pin_soc mt7622_data = {
852 	.reg_cal = mt7622_reg_cals,
853 	.pins = mt7622_pins,
854 	.npins = ARRAY_SIZE(mt7622_pins),
855 	.grps = mt7622_groups,
856 	.ngrps = ARRAY_SIZE(mt7622_groups),
857 	.funcs = mt7622_functions,
858 	.nfuncs = ARRAY_SIZE(mt7622_functions),
859 	.eint_hw = &mt7622_eint_hw,
860 	.gpio_m	= 1,
861 	.ies_present = false,
862 	.base_names = mtk_default_register_base_names,
863 	.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
864 	.bias_disable_set = mtk_pinconf_bias_disable_set,
865 	.bias_disable_get = mtk_pinconf_bias_disable_get,
866 	.bias_set = mtk_pinconf_bias_set,
867 	.bias_get = mtk_pinconf_bias_get,
868 	.drive_set = mtk_pinconf_drive_set,
869 	.drive_get = mtk_pinconf_drive_get,
870 };
871 
872 static const struct of_device_id mt7622_pinctrl_of_match[] = {
873 	{ .compatible = "mediatek,mt7622-pinctrl", },
874 	{ }
875 };
876 
877 static int mt7622_pinctrl_probe(struct platform_device *pdev)
878 {
879 	return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
880 }
881 
882 static struct platform_driver mt7622_pinctrl_driver = {
883 	.driver = {
884 		.name = "mt7622-pinctrl",
885 		.of_match_table = mt7622_pinctrl_of_match,
886 	},
887 	.probe = mt7622_pinctrl_probe,
888 };
889 
890 static int __init mt7622_pinctrl_init(void)
891 {
892 	return platform_driver_register(&mt7622_pinctrl_driver);
893 }
894 arch_initcall(mt7622_pinctrl_init);
895