1 /* 2 * MediaTek MT7622 Pinctrl Driver 3 * 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/gpio.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/io.h> 19 #include <linux/init.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_device.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/regmap.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinmux.h" 33 34 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME 35 #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } 36 #define PINCTRL_PIN_GROUP(name, id) \ 37 { \ 38 name, \ 39 id##_pins, \ 40 ARRAY_SIZE(id##_pins), \ 41 id##_funcs, \ 42 } 43 44 #define MTK_GPIO_MODE 1 45 #define MTK_INPUT 0 46 #define MTK_OUTPUT 1 47 #define MTK_DISABLE 0 48 #define MTK_ENABLE 1 49 50 /* Custom pinconf parameters */ 51 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) 52 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) 53 54 /* List these attributes which could be modified for the pin */ 55 enum { 56 PINCTRL_PIN_REG_MODE, 57 PINCTRL_PIN_REG_DIR, 58 PINCTRL_PIN_REG_DI, 59 PINCTRL_PIN_REG_DO, 60 PINCTRL_PIN_REG_SR, 61 PINCTRL_PIN_REG_SMT, 62 PINCTRL_PIN_REG_PD, 63 PINCTRL_PIN_REG_PU, 64 PINCTRL_PIN_REG_E4, 65 PINCTRL_PIN_REG_E8, 66 PINCTRL_PIN_REG_TDSEL, 67 PINCTRL_PIN_REG_RDSEL, 68 PINCTRL_PIN_REG_MAX, 69 }; 70 71 /* struct mtk_pin_field - the structure that holds the information of the field 72 * used to describe the attribute for the pin 73 * @offset: the register offset relative to the base address 74 * @mask: the mask used to filter out the field from the register 75 * @bitpos: the start bit relative to the register 76 * @next: the indication that the field would be extended to the 77 next register 78 */ 79 struct mtk_pin_field { 80 u32 offset; 81 u32 mask; 82 u8 bitpos; 83 u8 next; 84 }; 85 86 /* struct mtk_pin_field_calc - the structure that holds the range providing 87 * the guide used to look up the relevant field 88 * @s_pin: the start pin within the range 89 * @e_pin: the end pin within the range 90 * @s_addr: the start address for the range 91 * @x_addrs: the address distance between two consecutive registers 92 * within the range 93 * @s_bit: the start bit for the first register within the range 94 * @x_bits: the bit distance between two consecutive pins within 95 * the range 96 */ 97 struct mtk_pin_field_calc { 98 u16 s_pin; 99 u16 e_pin; 100 u32 s_addr; 101 u8 x_addrs; 102 u8 s_bit; 103 u8 x_bits; 104 }; 105 106 /* struct mtk_pin_reg_calc - the structure that holds all ranges used to 107 * determine which register the pin would make use of 108 * for certain pin attribute. 109 * @range: the start address for the range 110 * @nranges: the number of items in the range 111 */ 112 struct mtk_pin_reg_calc { 113 const struct mtk_pin_field_calc *range; 114 unsigned int nranges; 115 }; 116 117 /* struct mtk_pin_soc - the structure that holds SoC-specific data */ 118 struct mtk_pin_soc { 119 const struct mtk_pin_reg_calc *reg_cal; 120 const struct pinctrl_pin_desc *pins; 121 unsigned int npins; 122 const struct group_desc *grps; 123 unsigned int ngrps; 124 const struct function_desc *funcs; 125 unsigned int nfuncs; 126 }; 127 128 struct mtk_pinctrl { 129 struct pinctrl_dev *pctrl; 130 void __iomem *base; 131 struct device *dev; 132 struct gpio_chip chip; 133 const struct mtk_pin_soc *soc; 134 }; 135 136 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { 137 {0, 0, 0x320, 0x10, 16, 4}, 138 {1, 4, 0x3a0, 0x10, 16, 4}, 139 {5, 5, 0x320, 0x10, 0, 4}, 140 {6, 6, 0x300, 0x10, 4, 4}, 141 {7, 7, 0x300, 0x10, 4, 4}, 142 {8, 9, 0x350, 0x10, 20, 4}, 143 {10, 10, 0x300, 0x10, 8, 4}, 144 {11, 11, 0x300, 0x10, 8, 4}, 145 {12, 12, 0x300, 0x10, 8, 4}, 146 {13, 13, 0x300, 0x10, 8, 4}, 147 {14, 15, 0x320, 0x10, 4, 4}, 148 {16, 17, 0x320, 0x10, 20, 4}, 149 {18, 21, 0x310, 0x10, 16, 4}, 150 {22, 22, 0x380, 0x10, 16, 4}, 151 {23, 23, 0x300, 0x10, 24, 4}, 152 {24, 24, 0x300, 0x10, 24, 4}, 153 {25, 25, 0x300, 0x10, 12, 4}, 154 {25, 25, 0x300, 0x10, 12, 4}, 155 {26, 26, 0x300, 0x10, 12, 4}, 156 {27, 27, 0x300, 0x10, 12, 4}, 157 {28, 28, 0x300, 0x10, 12, 4}, 158 {29, 29, 0x300, 0x10, 12, 4}, 159 {30, 30, 0x300, 0x10, 12, 4}, 160 {31, 31, 0x300, 0x10, 12, 4}, 161 {32, 32, 0x300, 0x10, 12, 4}, 162 {33, 33, 0x300, 0x10, 12, 4}, 163 {34, 34, 0x300, 0x10, 12, 4}, 164 {35, 35, 0x300, 0x10, 12, 4}, 165 {36, 36, 0x300, 0x10, 12, 4}, 166 {37, 37, 0x300, 0x10, 20, 4}, 167 {38, 38, 0x300, 0x10, 20, 4}, 168 {39, 39, 0x300, 0x10, 20, 4}, 169 {40, 40, 0x300, 0x10, 20, 4}, 170 {41, 41, 0x300, 0x10, 20, 4}, 171 {42, 42, 0x300, 0x10, 20, 4}, 172 {43, 43, 0x300, 0x10, 20, 4}, 173 {44, 44, 0x300, 0x10, 20, 4}, 174 {45, 46, 0x300, 0x10, 20, 4}, 175 {47, 47, 0x300, 0x10, 20, 4}, 176 {48, 48, 0x300, 0x10, 20, 4}, 177 {49, 49, 0x300, 0x10, 20, 4}, 178 {50, 50, 0x300, 0x10, 20, 4}, 179 {51, 70, 0x330, 0x10, 4, 4}, 180 {71, 71, 0x300, 0x10, 16, 4}, 181 {72, 72, 0x300, 0x10, 16, 4}, 182 {73, 76, 0x310, 0x10, 0, 4}, 183 {77, 77, 0x320, 0x10, 28, 4}, 184 {78, 78, 0x320, 0x10, 12, 4}, 185 {79, 82, 0x3a0, 0x10, 0, 4}, 186 {83, 83, 0x350, 0x10, 28, 4}, 187 {84, 84, 0x330, 0x10, 0, 4}, 188 {85, 90, 0x360, 0x10, 4, 4}, 189 {91, 94, 0x390, 0x10, 16, 4}, 190 {95, 97, 0x380, 0x10, 20, 4}, 191 {98, 101, 0x390, 0x10, 0, 4}, 192 {102, 102, 0x360, 0x10, 0, 4}, 193 }; 194 195 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { 196 {0, 102, 0x0, 0x10, 0, 1}, 197 }; 198 199 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { 200 {0, 102, 0x200, 0x10, 0, 1}, 201 }; 202 203 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { 204 {0, 102, 0x100, 0x10, 0, 1}, 205 }; 206 207 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = { 208 {0, 31, 0x910, 0x10, 0, 1}, 209 {32, 50, 0xa10, 0x10, 0, 1}, 210 {51, 70, 0x810, 0x10, 0, 1}, 211 {71, 72, 0xb10, 0x10, 0, 1}, 212 {73, 86, 0xb10, 0x10, 4, 1}, 213 {87, 90, 0xc10, 0x10, 0, 1}, 214 {91, 102, 0xb10, 0x10, 18, 1}, 215 }; 216 217 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { 218 {0, 31, 0x920, 0x10, 0, 1}, 219 {32, 50, 0xa20, 0x10, 0, 1}, 220 {51, 70, 0x820, 0x10, 0, 1}, 221 {71, 72, 0xb20, 0x10, 0, 1}, 222 {73, 86, 0xb20, 0x10, 4, 1}, 223 {87, 90, 0xc20, 0x10, 0, 1}, 224 {91, 102, 0xb20, 0x10, 18, 1}, 225 }; 226 227 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { 228 {0, 31, 0x930, 0x10, 0, 1}, 229 {32, 50, 0xa30, 0x10, 0, 1}, 230 {51, 70, 0x830, 0x10, 0, 1}, 231 {71, 72, 0xb30, 0x10, 0, 1}, 232 {73, 86, 0xb30, 0x10, 4, 1}, 233 {87, 90, 0xc30, 0x10, 0, 1}, 234 {91, 102, 0xb30, 0x10, 18, 1}, 235 }; 236 237 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { 238 {0, 31, 0x940, 0x10, 0, 1}, 239 {32, 50, 0xa40, 0x10, 0, 1}, 240 {51, 70, 0x840, 0x10, 0, 1}, 241 {71, 72, 0xb40, 0x10, 0, 1}, 242 {73, 86, 0xb40, 0x10, 4, 1}, 243 {87, 90, 0xc40, 0x10, 0, 1}, 244 {91, 102, 0xb40, 0x10, 18, 1}, 245 }; 246 247 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { 248 {0, 31, 0x960, 0x10, 0, 1}, 249 {32, 50, 0xa60, 0x10, 0, 1}, 250 {51, 70, 0x860, 0x10, 0, 1}, 251 {71, 72, 0xb60, 0x10, 0, 1}, 252 {73, 86, 0xb60, 0x10, 4, 1}, 253 {87, 90, 0xc60, 0x10, 0, 1}, 254 {91, 102, 0xb60, 0x10, 18, 1}, 255 }; 256 257 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { 258 {0, 31, 0x970, 0x10, 0, 1}, 259 {32, 50, 0xa70, 0x10, 0, 1}, 260 {51, 70, 0x870, 0x10, 0, 1}, 261 {71, 72, 0xb70, 0x10, 0, 1}, 262 {73, 86, 0xb70, 0x10, 4, 1}, 263 {87, 90, 0xc70, 0x10, 0, 1}, 264 {91, 102, 0xb70, 0x10, 18, 1}, 265 }; 266 267 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = { 268 {0, 31, 0x980, 0x4, 0, 4}, 269 {32, 50, 0xa80, 0x4, 0, 4}, 270 {51, 70, 0x880, 0x4, 0, 4}, 271 {71, 72, 0xb80, 0x4, 0, 4}, 272 {73, 86, 0xb80, 0x4, 16, 4}, 273 {87, 90, 0xc80, 0x4, 0, 4}, 274 {91, 102, 0xb88, 0x4, 8, 4}, 275 }; 276 277 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = { 278 {0, 31, 0x990, 0x4, 0, 6}, 279 {32, 50, 0xa90, 0x4, 0, 6}, 280 {51, 58, 0x890, 0x4, 0, 6}, 281 {59, 60, 0x894, 0x4, 28, 6}, 282 {61, 62, 0x894, 0x4, 16, 6}, 283 {63, 66, 0x898, 0x4, 8, 6}, 284 {67, 68, 0x89c, 0x4, 12, 6}, 285 {69, 70, 0x89c, 0x4, 0, 6}, 286 {71, 72, 0xb90, 0x4, 0, 6}, 287 {73, 86, 0xb90, 0x4, 24, 6}, 288 {87, 90, 0xc90, 0x4, 0, 6}, 289 {91, 102, 0xb9c, 0x4, 12, 6}, 290 }; 291 292 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { 293 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range), 294 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range), 295 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range), 296 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range), 297 [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range), 298 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range), 299 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range), 300 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range), 301 [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range), 302 [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range), 303 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range), 304 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range), 305 }; 306 307 static const struct pinctrl_pin_desc mt7622_pins[] = { 308 PINCTRL_PIN(0, "GPIO_A"), 309 PINCTRL_PIN(1, "I2S1_IN"), 310 PINCTRL_PIN(2, "I2S1_OUT"), 311 PINCTRL_PIN(3, "I2S_BCLK"), 312 PINCTRL_PIN(4, "I2S_WS"), 313 PINCTRL_PIN(5, "I2S_MCLK"), 314 PINCTRL_PIN(6, "TXD0"), 315 PINCTRL_PIN(7, "RXD0"), 316 PINCTRL_PIN(8, "SPI_WP"), 317 PINCTRL_PIN(9, "SPI_HOLD"), 318 PINCTRL_PIN(10, "SPI_CLK"), 319 PINCTRL_PIN(11, "SPI_MOSI"), 320 PINCTRL_PIN(12, "SPI_MISO"), 321 PINCTRL_PIN(13, "SPI_CS"), 322 PINCTRL_PIN(14, "I2C_SDA"), 323 PINCTRL_PIN(15, "I2C_SCL"), 324 PINCTRL_PIN(16, "I2S2_IN"), 325 PINCTRL_PIN(17, "I2S3_IN"), 326 PINCTRL_PIN(18, "I2S4_IN"), 327 PINCTRL_PIN(19, "I2S2_OUT"), 328 PINCTRL_PIN(20, "I2S3_OUT"), 329 PINCTRL_PIN(21, "I2S4_OUT"), 330 PINCTRL_PIN(22, "GPIO_B"), 331 PINCTRL_PIN(23, "MDC"), 332 PINCTRL_PIN(24, "MDIO"), 333 PINCTRL_PIN(25, "G2_TXD0"), 334 PINCTRL_PIN(26, "G2_TXD1"), 335 PINCTRL_PIN(27, "G2_TXD2"), 336 PINCTRL_PIN(28, "G2_TXD3"), 337 PINCTRL_PIN(29, "G2_TXEN"), 338 PINCTRL_PIN(30, "G2_TXC"), 339 PINCTRL_PIN(31, "G2_RXD0"), 340 PINCTRL_PIN(32, "G2_RXD1"), 341 PINCTRL_PIN(33, "G2_RXD2"), 342 PINCTRL_PIN(34, "G2_RXD3"), 343 PINCTRL_PIN(35, "G2_RXDV"), 344 PINCTRL_PIN(36, "G2_RXC"), 345 PINCTRL_PIN(37, "NCEB"), 346 PINCTRL_PIN(38, "NWEB"), 347 PINCTRL_PIN(39, "NREB"), 348 PINCTRL_PIN(40, "NDL4"), 349 PINCTRL_PIN(41, "NDL5"), 350 PINCTRL_PIN(42, "NDL6"), 351 PINCTRL_PIN(43, "NDL7"), 352 PINCTRL_PIN(44, "NRB"), 353 PINCTRL_PIN(45, "NCLE"), 354 PINCTRL_PIN(46, "NALE"), 355 PINCTRL_PIN(47, "NDL0"), 356 PINCTRL_PIN(48, "NDL1"), 357 PINCTRL_PIN(49, "NDL2"), 358 PINCTRL_PIN(50, "NDL3"), 359 PINCTRL_PIN(51, "MDI_TP_P0"), 360 PINCTRL_PIN(52, "MDI_TN_P0"), 361 PINCTRL_PIN(53, "MDI_RP_P0"), 362 PINCTRL_PIN(54, "MDI_RN_P0"), 363 PINCTRL_PIN(55, "MDI_TP_P1"), 364 PINCTRL_PIN(56, "MDI_TN_P1"), 365 PINCTRL_PIN(57, "MDI_RP_P1"), 366 PINCTRL_PIN(58, "MDI_RN_P1"), 367 PINCTRL_PIN(59, "MDI_RP_P2"), 368 PINCTRL_PIN(60, "MDI_RN_P2"), 369 PINCTRL_PIN(61, "MDI_TP_P2"), 370 PINCTRL_PIN(62, "MDI_TN_P2"), 371 PINCTRL_PIN(63, "MDI_TP_P3"), 372 PINCTRL_PIN(64, "MDI_TN_P3"), 373 PINCTRL_PIN(65, "MDI_RP_P3"), 374 PINCTRL_PIN(66, "MDI_RN_P3"), 375 PINCTRL_PIN(67, "MDI_RP_P4"), 376 PINCTRL_PIN(68, "MDI_RN_P4"), 377 PINCTRL_PIN(69, "MDI_TP_P4"), 378 PINCTRL_PIN(70, "MDI_TN_P4"), 379 PINCTRL_PIN(71, "PMIC_SCL"), 380 PINCTRL_PIN(72, "PMIC_SDA"), 381 PINCTRL_PIN(73, "SPIC1_CLK"), 382 PINCTRL_PIN(74, "SPIC1_MOSI"), 383 PINCTRL_PIN(75, "SPIC1_MISO"), 384 PINCTRL_PIN(76, "SPIC1_CS"), 385 PINCTRL_PIN(77, "GPIO_D"), 386 PINCTRL_PIN(78, "WATCHDOG"), 387 PINCTRL_PIN(79, "RTS3_N"), 388 PINCTRL_PIN(80, "CTS3_N"), 389 PINCTRL_PIN(81, "TXD3"), 390 PINCTRL_PIN(82, "RXD3"), 391 PINCTRL_PIN(83, "PERST0_N"), 392 PINCTRL_PIN(84, "PERST1_N"), 393 PINCTRL_PIN(85, "WLED_N"), 394 PINCTRL_PIN(86, "EPHY_LED0_N"), 395 PINCTRL_PIN(87, "AUXIN0"), 396 PINCTRL_PIN(88, "AUXIN1"), 397 PINCTRL_PIN(89, "AUXIN2"), 398 PINCTRL_PIN(90, "AUXIN3"), 399 PINCTRL_PIN(91, "TXD4"), 400 PINCTRL_PIN(92, "RXD4"), 401 PINCTRL_PIN(93, "RTS4_N"), 402 PINCTRL_PIN(94, "CTS4_N"), 403 PINCTRL_PIN(95, "PWM1"), 404 PINCTRL_PIN(96, "PWM2"), 405 PINCTRL_PIN(97, "PWM3"), 406 PINCTRL_PIN(98, "PWM4"), 407 PINCTRL_PIN(99, "PWM5"), 408 PINCTRL_PIN(100, "PWM6"), 409 PINCTRL_PIN(101, "PWM7"), 410 PINCTRL_PIN(102, "GPIO_E"), 411 }; 412 413 /* List all groups consisting of these pins dedicated to the enablement of 414 * certain hardware block and the corresponding mode for all of the pins. The 415 * hardware probably has multiple combinations of these pinouts. 416 */ 417 418 /* EMMC */ 419 static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; 420 static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 421 422 static int mt7622_emmc_rst_pins[] = { 37, }; 423 static int mt7622_emmc_rst_funcs[] = { 1, }; 424 425 /* LED for EPHY */ 426 static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; 427 static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; 428 static int mt7622_ephy0_led_pins[] = { 86, }; 429 static int mt7622_ephy0_led_funcs[] = { 0, }; 430 static int mt7622_ephy1_led_pins[] = { 91, }; 431 static int mt7622_ephy1_led_funcs[] = { 2, }; 432 static int mt7622_ephy2_led_pins[] = { 92, }; 433 static int mt7622_ephy2_led_funcs[] = { 2, }; 434 static int mt7622_ephy3_led_pins[] = { 93, }; 435 static int mt7622_ephy3_led_funcs[] = { 2, }; 436 static int mt7622_ephy4_led_pins[] = { 94, }; 437 static int mt7622_ephy4_led_funcs[] = { 2, }; 438 439 /* Embedded Switch */ 440 static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 441 62, 63, 64, 65, 66, 67, 68, 69, 70, }; 442 static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 443 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 444 static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; 445 static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 446 static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, 447 68, 69, 70, }; 448 static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 449 0, 0, 0, }; 450 /* RGMII via ESW */ 451 static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 452 67, 68, 69, 70, }; 453 static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 454 0, }; 455 456 /* RGMII via GMAC1 */ 457 static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 458 67, 68, 69, 70, }; 459 static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 460 2, }; 461 462 /* RGMII via GMAC2 */ 463 static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, 464 33, 34, 35, 36, }; 465 static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 466 0, }; 467 468 /* I2C */ 469 static int mt7622_i2c0_pins[] = { 14, 15, }; 470 static int mt7622_i2c0_funcs[] = { 0, 0, }; 471 static int mt7622_i2c1_0_pins[] = { 55, 56, }; 472 static int mt7622_i2c1_0_funcs[] = { 0, 0, }; 473 static int mt7622_i2c1_1_pins[] = { 73, 74, }; 474 static int mt7622_i2c1_1_funcs[] = { 3, 3, }; 475 static int mt7622_i2c1_2_pins[] = { 87, 88, }; 476 static int mt7622_i2c1_2_funcs[] = { 0, 0, }; 477 static int mt7622_i2c2_0_pins[] = { 57, 58, }; 478 static int mt7622_i2c2_0_funcs[] = { 0, 0, }; 479 static int mt7622_i2c2_1_pins[] = { 75, 76, }; 480 static int mt7622_i2c2_1_funcs[] = { 3, 3, }; 481 static int mt7622_i2c2_2_pins[] = { 89, 90, }; 482 static int mt7622_i2c2_2_funcs[] = { 0, 0, }; 483 484 /* I2S */ 485 static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; 486 static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; 487 static int mt7622_i2s1_in_data_pins[] = { 1, }; 488 static int mt7622_i2s1_in_data_funcs[] = { 0, }; 489 static int mt7622_i2s2_in_data_pins[] = { 16, }; 490 static int mt7622_i2s2_in_data_funcs[] = { 0, }; 491 static int mt7622_i2s3_in_data_pins[] = { 17, }; 492 static int mt7622_i2s3_in_data_funcs[] = { 0, }; 493 static int mt7622_i2s4_in_data_pins[] = { 18, }; 494 static int mt7622_i2s4_in_data_funcs[] = { 0, }; 495 static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; 496 static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; 497 static int mt7622_i2s1_out_data_pins[] = { 2, }; 498 static int mt7622_i2s1_out_data_funcs[] = { 0, }; 499 static int mt7622_i2s2_out_data_pins[] = { 19, }; 500 static int mt7622_i2s2_out_data_funcs[] = { 0, }; 501 static int mt7622_i2s3_out_data_pins[] = { 20, }; 502 static int mt7622_i2s3_out_data_funcs[] = { 0, }; 503 static int mt7622_i2s4_out_data_pins[] = { 21, }; 504 static int mt7622_i2s4_out_data_funcs[] = { 0, }; 505 506 /* IR */ 507 static int mt7622_ir_0_tx_pins[] = { 16, }; 508 static int mt7622_ir_0_tx_funcs[] = { 4, }; 509 static int mt7622_ir_1_tx_pins[] = { 59, }; 510 static int mt7622_ir_1_tx_funcs[] = { 5, }; 511 static int mt7622_ir_2_tx_pins[] = { 99, }; 512 static int mt7622_ir_2_tx_funcs[] = { 3, }; 513 static int mt7622_ir_0_rx_pins[] = { 17, }; 514 static int mt7622_ir_0_rx_funcs[] = { 4, }; 515 static int mt7622_ir_1_rx_pins[] = { 60, }; 516 static int mt7622_ir_1_rx_funcs[] = { 5, }; 517 static int mt7622_ir_2_rx_pins[] = { 100, }; 518 static int mt7622_ir_2_rx_funcs[] = { 3, }; 519 520 /* MDIO */ 521 static int mt7622_mdc_mdio_pins[] = { 23, 24, }; 522 static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; 523 524 /* PCIE */ 525 static int mt7622_pcie0_0_waken_pins[] = { 14, }; 526 static int mt7622_pcie0_0_waken_funcs[] = { 2, }; 527 static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; 528 static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; 529 static int mt7622_pcie0_1_waken_pins[] = { 79, }; 530 static int mt7622_pcie0_1_waken_funcs[] = { 4, }; 531 static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; 532 static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; 533 static int mt7622_pcie1_0_waken_pins[] = { 14, }; 534 static int mt7622_pcie1_0_waken_funcs[] = { 3, }; 535 static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; 536 static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; 537 538 static int mt7622_pcie0_pad_perst_pins[] = { 83, }; 539 static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; 540 static int mt7622_pcie1_pad_perst_pins[] = { 84, }; 541 static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; 542 543 /* PMIC bus */ 544 static int mt7622_pmic_bus_pins[] = { 71, 72, }; 545 static int mt7622_pmic_bus_funcs[] = { 0, 0, }; 546 547 /* Parallel NAND */ 548 static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 549 48, 49, 50, }; 550 static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 551 0, }; 552 553 /* PWM */ 554 static int mt7622_pwm_ch1_0_pins[] = { 51, }; 555 static int mt7622_pwm_ch1_0_funcs[] = { 3, }; 556 static int mt7622_pwm_ch1_1_pins[] = { 73, }; 557 static int mt7622_pwm_ch1_1_funcs[] = { 4, }; 558 static int mt7622_pwm_ch1_2_pins[] = { 95, }; 559 static int mt7622_pwm_ch1_2_funcs[] = { 0, }; 560 static int mt7622_pwm_ch2_0_pins[] = { 52, }; 561 static int mt7622_pwm_ch2_0_funcs[] = { 3, }; 562 static int mt7622_pwm_ch2_1_pins[] = { 74, }; 563 static int mt7622_pwm_ch2_1_funcs[] = { 4, }; 564 static int mt7622_pwm_ch2_2_pins[] = { 96, }; 565 static int mt7622_pwm_ch2_2_funcs[] = { 0, }; 566 static int mt7622_pwm_ch3_0_pins[] = { 53, }; 567 static int mt7622_pwm_ch3_0_funcs[] = { 3, }; 568 static int mt7622_pwm_ch3_1_pins[] = { 75, }; 569 static int mt7622_pwm_ch3_1_funcs[] = { 4, }; 570 static int mt7622_pwm_ch3_2_pins[] = { 97, }; 571 static int mt7622_pwm_ch3_2_funcs[] = { 0, }; 572 static int mt7622_pwm_ch4_0_pins[] = { 54, }; 573 static int mt7622_pwm_ch4_0_funcs[] = { 3, }; 574 static int mt7622_pwm_ch4_1_pins[] = { 67, }; 575 static int mt7622_pwm_ch4_1_funcs[] = { 3, }; 576 static int mt7622_pwm_ch4_2_pins[] = { 76, }; 577 static int mt7622_pwm_ch4_2_funcs[] = { 4, }; 578 static int mt7622_pwm_ch4_3_pins[] = { 98, }; 579 static int mt7622_pwm_ch4_3_funcs[] = { 0, }; 580 static int mt7622_pwm_ch5_0_pins[] = { 68, }; 581 static int mt7622_pwm_ch5_0_funcs[] = { 3, }; 582 static int mt7622_pwm_ch5_1_pins[] = { 77, }; 583 static int mt7622_pwm_ch5_1_funcs[] = { 4, }; 584 static int mt7622_pwm_ch5_2_pins[] = { 99, }; 585 static int mt7622_pwm_ch5_2_funcs[] = { 0, }; 586 static int mt7622_pwm_ch6_0_pins[] = { 69, }; 587 static int mt7622_pwm_ch6_0_funcs[] = { 3, }; 588 static int mt7622_pwm_ch6_1_pins[] = { 78, }; 589 static int mt7622_pwm_ch6_1_funcs[] = { 4, }; 590 static int mt7622_pwm_ch6_2_pins[] = { 81, }; 591 static int mt7622_pwm_ch6_2_funcs[] = { 4, }; 592 static int mt7622_pwm_ch6_3_pins[] = { 100, }; 593 static int mt7622_pwm_ch6_3_funcs[] = { 0, }; 594 static int mt7622_pwm_ch7_0_pins[] = { 70, }; 595 static int mt7622_pwm_ch7_0_funcs[] = { 3, }; 596 static int mt7622_pwm_ch7_1_pins[] = { 82, }; 597 static int mt7622_pwm_ch7_1_funcs[] = { 4, }; 598 static int mt7622_pwm_ch7_2_pins[] = { 101, }; 599 static int mt7622_pwm_ch7_2_funcs[] = { 0, }; 600 601 /* SD */ 602 static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; 603 static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; 604 static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; 605 static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; 606 607 /* Serial NAND */ 608 static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; 609 static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; 610 611 /* SPI NOR */ 612 static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; 613 static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; 614 615 /* SPIC */ 616 static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; 617 static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; 618 static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; 619 static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; 620 static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; 621 static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; 622 static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; 623 static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; 624 static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; 625 static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; 626 static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; 627 static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; 628 629 /* TDM */ 630 static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; 631 static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; 632 static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; 633 static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; 634 static int mt7622_tdm_0_out_data_pins[] = { 20, }; 635 static int mt7622_tdm_0_out_data_funcs[] = { 3, }; 636 static int mt7622_tdm_0_in_data_pins[] = { 21, }; 637 static int mt7622_tdm_0_in_data_funcs[] = { 3, }; 638 static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; 639 static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; 640 static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; 641 static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; 642 static int mt7622_tdm_1_out_data_pins[] = { 55, }; 643 static int mt7622_tdm_1_out_data_funcs[] = { 3, }; 644 static int mt7622_tdm_1_in_data_pins[] = { 56, }; 645 static int mt7622_tdm_1_in_data_funcs[] = { 3, }; 646 647 /* UART */ 648 static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; 649 static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; 650 static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; 651 static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; 652 static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; 653 static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; 654 static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; 655 static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; 656 static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; 657 static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; 658 static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; 659 static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; 660 static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; 661 static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; 662 static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; 663 static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; 664 static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; 665 static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; 666 static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; 667 static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; 668 static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; 669 static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; 670 static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; 671 static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; 672 static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; 673 static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; 674 static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; 675 static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; 676 static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; 677 static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; 678 static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; 679 static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; 680 static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; 681 static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; 682 static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; 683 static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; 684 static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; 685 static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; 686 static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; 687 static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; 688 689 /* Watchdog */ 690 static int mt7622_watchdog_pins[] = { 78, }; 691 static int mt7622_watchdog_funcs[] = { 0, }; 692 693 /* WLAN LED */ 694 static int mt7622_wled_pins[] = { 85, }; 695 static int mt7622_wled_funcs[] = { 0, }; 696 697 static const struct group_desc mt7622_groups[] = { 698 PINCTRL_PIN_GROUP("emmc", mt7622_emmc), 699 PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), 700 PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), 701 PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led), 702 PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led), 703 PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led), 704 PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led), 705 PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led), 706 PINCTRL_PIN_GROUP("esw", mt7622_esw), 707 PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1), 708 PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4), 709 PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw), 710 PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1), 711 PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2), 712 PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0), 713 PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0), 714 PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1), 715 PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2), 716 PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0), 717 PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1), 718 PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2), 719 PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws), 720 PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws), 721 PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data), 722 PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data), 723 PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data), 724 PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data), 725 PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data), 726 PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data), 727 PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data), 728 PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data), 729 PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx), 730 PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx), 731 PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx), 732 PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx), 733 PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx), 734 PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx), 735 PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio), 736 PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken), 737 PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq), 738 PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken), 739 PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq), 740 PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken), 741 PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq), 742 PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst), 743 PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst), 744 PINCTRL_PIN_GROUP("par_nand", mt7622_pnand), 745 PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus), 746 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0), 747 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1), 748 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2), 749 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0), 750 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1), 751 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2), 752 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0), 753 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1), 754 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2), 755 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0), 756 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1), 757 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2), 758 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3), 759 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0), 760 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1), 761 PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2), 762 PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0), 763 PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), 764 PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), 765 PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), 766 PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), 767 PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), 768 PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), 769 PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), 770 PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), 771 PINCTRL_PIN_GROUP("snfi", mt7622_snfi), 772 PINCTRL_PIN_GROUP("spi_nor", mt7622_spi), 773 PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0), 774 PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1), 775 PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0), 776 PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1), 777 PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0), 778 PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold), 779 PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws", 780 mt7622_tdm_0_out_mclk_bclk_ws), 781 PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws", 782 mt7622_tdm_0_in_mclk_bclk_ws), 783 PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data), 784 PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data), 785 PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws", 786 mt7622_tdm_1_out_mclk_bclk_ws), 787 PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws", 788 mt7622_tdm_1_in_mclk_bclk_ws), 789 PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data), 790 PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data), 791 PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx), 792 PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx), 793 PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts), 794 PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx), 795 PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts), 796 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx), 797 PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts), 798 PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx), 799 PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts), 800 PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx), 801 PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts), 802 PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx), 803 PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx), 804 PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx), 805 PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts), 806 PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx), 807 PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx), 808 PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts), 809 PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx), 810 PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts), 811 PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog), 812 PINCTRL_PIN_GROUP("wled", mt7622_wled), 813 }; 814 815 /* Joint those groups owning the same capability in user point of view which 816 * allows that people tend to use through the device tree. 817 */ 818 static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; 819 static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", 820 "esw_p2_p3_p4", "mdc_mdio", 821 "rgmii_via_gmac1", 822 "rgmii_via_gmac2", 823 "rgmii_via_esw", }; 824 static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", 825 "i2c1_2", "i2c2_0", "i2c2_1", 826 "i2c2_2", }; 827 static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws", 828 "i2s_in_mclk_bclk_ws", 829 "i2s1_in_data", "i2s2_in_data", 830 "i2s3_in_data", "i2s4_in_data", 831 "i2s1_out_data", "i2s2_out_data", 832 "i2s3_out_data", "i2s4_out_data", }; 833 static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx", 834 "ir_0_rx", "ir_1_rx", "ir_2_rx"}; 835 static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led", 836 "ephy1_led", "ephy2_led", 837 "ephy3_led", "ephy4_led", 838 "wled", }; 839 static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"}; 840 static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq", 841 "pcie0_1_waken", "pcie0_1_clkreq", 842 "pcie1_0_waken", "pcie1_0_clkreq", 843 "pcie0_pad_perst", 844 "pcie1_pad_perst", }; 845 static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", }; 846 static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", 847 "pwm_ch1_2", "pwm_ch2_0", 848 "pwm_ch2_1", "pwm_ch2_2", 849 "pwm_ch3_0", "pwm_ch3_1", 850 "pwm_ch3_2", "pwm_ch4_0", 851 "pwm_ch4_1", "pwm_ch4_2", 852 "pwm_ch4_3", "pwm_ch5_0", 853 "pwm_ch5_1", "pwm_ch5_2", 854 "pwm_ch6_0", "pwm_ch6_1", 855 "pwm_ch6_2", "pwm_ch6_3", 856 "pwm_ch7_0", "pwm_ch7_1", 857 "pwm_ch7_2", }; 858 static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", }; 859 static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0", 860 "spic1_1", "spic2_0", 861 "spic2_0_wp_hold", }; 862 static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws", 863 "tdm_0_in_mclk_bclk_ws", 864 "tdm_0_out_data", 865 "tdm_0_in_data", 866 "tdm_1_out_mclk_bclk_ws", 867 "tdm_1_in_mclk_bclk_ws", 868 "tdm_1_out_data", 869 "tdm_1_in_data", }; 870 871 static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx", 872 "uart1_0_tx_rx", "uart1_0_rts_cts", 873 "uart1_1_tx_rx", "uart1_1_rts_cts", 874 "uart2_0_tx_rx", "uart2_0_rts_cts", 875 "uart2_1_tx_rx", "uart2_1_rts_cts", 876 "uart2_2_tx_rx", "uart2_2_rts_cts", 877 "uart2_3_tx_rx", 878 "uart3_0_tx_rx", 879 "uart3_1_tx_rx", "uart3_1_rts_cts", 880 "uart4_0_tx_rx", 881 "uart4_1_tx_rx", "uart4_1_rts_cts", 882 "uart4_2_tx_rx", 883 "uart4_2_rts_cts",}; 884 static const char *mt7622_wdt_groups[] = { "watchdog", }; 885 886 static const struct function_desc mt7622_functions[] = { 887 {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, 888 {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, 889 {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, 890 {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)}, 891 {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)}, 892 {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)}, 893 {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)}, 894 {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)}, 895 {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)}, 896 {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)}, 897 {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)}, 898 {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)}, 899 {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)}, 900 {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)}, 901 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, 902 }; 903 904 static const struct pinconf_generic_params mtk_custom_bindings[] = { 905 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, 906 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, 907 }; 908 909 #ifdef CONFIG_DEBUG_FS 910 static const struct pin_config_item mtk_conf_items[] = { 911 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), 912 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), 913 }; 914 #endif 915 916 static const struct mtk_pin_soc mt7622_data = { 917 .reg_cal = mt7622_reg_cals, 918 .pins = mt7622_pins, 919 .npins = ARRAY_SIZE(mt7622_pins), 920 .grps = mt7622_groups, 921 .ngrps = ARRAY_SIZE(mt7622_groups), 922 .funcs = mt7622_functions, 923 .nfuncs = ARRAY_SIZE(mt7622_functions), 924 }; 925 926 static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val) 927 { 928 writel_relaxed(val, pctl->base + reg); 929 } 930 931 static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg) 932 { 933 return readl_relaxed(pctl->base + reg); 934 } 935 936 static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set) 937 { 938 u32 val; 939 940 val = mtk_r32(pctl, reg); 941 val &= ~mask; 942 val |= set; 943 mtk_w32(pctl, reg, val); 944 } 945 946 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin, 947 const struct mtk_pin_reg_calc *rc, 948 struct mtk_pin_field *pfd) 949 { 950 const struct mtk_pin_field_calc *c, *e; 951 u32 bits; 952 953 c = rc->range; 954 e = c + rc->nranges; 955 956 while (c < e) { 957 if (pin >= c->s_pin && pin <= c->e_pin) 958 break; 959 c++; 960 } 961 962 if (c >= e) { 963 dev_err(hw->dev, "Out of range for pin = %d\n", pin); 964 return -EINVAL; 965 } 966 967 /* Caculated bits as the overall offset the pin is located at */ 968 bits = c->s_bit + (pin - c->s_pin) * (c->x_bits); 969 970 /* Fill pfd from bits and 32-bit register applied is assumed */ 971 pfd->offset = c->s_addr + c->x_addrs * (bits / 32); 972 pfd->bitpos = bits % 32; 973 pfd->mask = (1 << c->x_bits) - 1; 974 975 /* pfd->next is used for indicating that bit wrapping-around happens 976 * which requires the manipulation for bit 0 starting in the next 977 * register to form the complete field read/write. 978 */ 979 pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0; 980 981 return 0; 982 } 983 984 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin, 985 int field, struct mtk_pin_field *pfd) 986 { 987 const struct mtk_pin_reg_calc *rc; 988 989 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { 990 dev_err(hw->dev, "Invalid Field %d\n", field); 991 return -EINVAL; 992 } 993 994 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { 995 rc = &hw->soc->reg_cal[field]; 996 } else { 997 dev_err(hw->dev, "Undefined range for field %d\n", field); 998 return -EINVAL; 999 } 1000 1001 return mtk_hw_pin_field_lookup(hw, pin, rc, pfd); 1002 } 1003 1004 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) 1005 { 1006 *l = 32 - pf->bitpos; 1007 *h = get_count_order(pf->mask) - *l; 1008 } 1009 1010 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, 1011 struct mtk_pin_field *pf, int value) 1012 { 1013 int nbits_l, nbits_h; 1014 1015 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 1016 1017 mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos, 1018 (value & pf->mask) << pf->bitpos); 1019 1020 mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1, 1021 (value & pf->mask) >> nbits_l); 1022 } 1023 1024 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, 1025 struct mtk_pin_field *pf, int *value) 1026 { 1027 int nbits_l, nbits_h, h, l; 1028 1029 mtk_hw_bits_part(pf, &nbits_h, &nbits_l); 1030 1031 l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1); 1032 h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1); 1033 1034 *value = (h << nbits_l) | l; 1035 } 1036 1037 static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field, 1038 int value) 1039 { 1040 struct mtk_pin_field pf; 1041 int err; 1042 1043 err = mtk_hw_pin_field_get(hw, pin, field, &pf); 1044 if (err) 1045 return err; 1046 1047 if (!pf.next) 1048 mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos, 1049 (value & pf.mask) << pf.bitpos); 1050 else 1051 mtk_hw_write_cross_field(hw, &pf, value); 1052 1053 return 0; 1054 } 1055 1056 static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field, 1057 int *value) 1058 { 1059 struct mtk_pin_field pf; 1060 int err; 1061 1062 err = mtk_hw_pin_field_get(hw, pin, field, &pf); 1063 if (err) 1064 return err; 1065 1066 if (!pf.next) 1067 *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask; 1068 else 1069 mtk_hw_read_cross_field(hw, &pf, value); 1070 1071 return 0; 1072 } 1073 1074 static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, 1075 unsigned int selector, unsigned int group) 1076 { 1077 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 1078 struct function_desc *func; 1079 struct group_desc *grp; 1080 int i; 1081 1082 func = pinmux_generic_get_function(pctldev, selector); 1083 if (!func) 1084 return -EINVAL; 1085 1086 grp = pinctrl_generic_get_group(pctldev, group); 1087 if (!grp) 1088 return -EINVAL; 1089 1090 dev_dbg(pctldev->dev, "enable function %s group %s\n", 1091 func->name, grp->name); 1092 1093 for (i = 0; i < grp->num_pins; i++) { 1094 int *pin_modes = grp->data; 1095 1096 mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE, 1097 pin_modes[i]); 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, 1104 struct pinctrl_gpio_range *range, 1105 unsigned int pin) 1106 { 1107 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 1108 1109 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE); 1110 } 1111 1112 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 1113 struct pinctrl_gpio_range *range, 1114 unsigned int pin, bool input) 1115 { 1116 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 1117 1118 /* hardware would take 0 as input direction */ 1119 return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input); 1120 } 1121 1122 static int mtk_pinconf_get(struct pinctrl_dev *pctldev, 1123 unsigned int pin, unsigned long *config) 1124 { 1125 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 1126 u32 param = pinconf_to_config_param(*config); 1127 int val, val2, err, reg, ret = 1; 1128 1129 switch (param) { 1130 case PIN_CONFIG_BIAS_DISABLE: 1131 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val); 1132 if (err) 1133 return err; 1134 1135 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2); 1136 if (err) 1137 return err; 1138 1139 if (val || val2) 1140 return -EINVAL; 1141 1142 break; 1143 case PIN_CONFIG_BIAS_PULL_UP: 1144 case PIN_CONFIG_BIAS_PULL_DOWN: 1145 case PIN_CONFIG_SLEW_RATE: 1146 reg = (param == PIN_CONFIG_BIAS_PULL_UP) ? 1147 PINCTRL_PIN_REG_PU : 1148 (param == PIN_CONFIG_BIAS_PULL_DOWN) ? 1149 PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR; 1150 1151 err = mtk_hw_get_value(hw, pin, reg, &val); 1152 if (err) 1153 return err; 1154 1155 if (!val) 1156 return -EINVAL; 1157 1158 break; 1159 case PIN_CONFIG_INPUT_ENABLE: 1160 case PIN_CONFIG_OUTPUT_ENABLE: 1161 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); 1162 if (err) 1163 return err; 1164 1165 /* HW takes input mode as zero; output mode as non-zero */ 1166 if ((val && param == PIN_CONFIG_INPUT_ENABLE) || 1167 (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) 1168 return -EINVAL; 1169 1170 break; 1171 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1172 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); 1173 if (err) 1174 return err; 1175 1176 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2); 1177 if (err) 1178 return err; 1179 1180 if (val || !val2) 1181 return -EINVAL; 1182 1183 break; 1184 case PIN_CONFIG_DRIVE_STRENGTH: 1185 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val); 1186 if (err) 1187 return err; 1188 1189 err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2); 1190 if (err) 1191 return err; 1192 1193 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) 1194 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) 1195 */ 1196 ret = ((val2 << 1) + val + 1) * 4; 1197 1198 break; 1199 case MTK_PIN_CONFIG_TDSEL: 1200 case MTK_PIN_CONFIG_RDSEL: 1201 reg = (param == MTK_PIN_CONFIG_TDSEL) ? 1202 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; 1203 1204 err = mtk_hw_get_value(hw, pin, reg, &val); 1205 if (err) 1206 return err; 1207 1208 ret = val; 1209 1210 break; 1211 default: 1212 return -ENOTSUPP; 1213 } 1214 1215 *config = pinconf_to_config_packed(param, ret); 1216 1217 return 0; 1218 } 1219 1220 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1221 unsigned long *configs, unsigned int num_configs) 1222 { 1223 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); 1224 u32 reg, param, arg; 1225 int cfg, err = 0; 1226 1227 for (cfg = 0; cfg < num_configs; cfg++) { 1228 param = pinconf_to_config_param(configs[cfg]); 1229 arg = pinconf_to_config_argument(configs[cfg]); 1230 1231 switch (param) { 1232 case PIN_CONFIG_BIAS_DISABLE: 1233 case PIN_CONFIG_BIAS_PULL_UP: 1234 case PIN_CONFIG_BIAS_PULL_DOWN: 1235 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1236 (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2; 1237 1238 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU, 1239 arg & 1); 1240 if (err) 1241 goto err; 1242 1243 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD, 1244 !!(arg & 2)); 1245 if (err) 1246 goto err; 1247 break; 1248 case PIN_CONFIG_OUTPUT_ENABLE: 1249 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, 1250 MTK_DISABLE); 1251 if (err) 1252 goto err; 1253 case PIN_CONFIG_INPUT_ENABLE: 1254 case PIN_CONFIG_SLEW_RATE: 1255 reg = (param == PIN_CONFIG_SLEW_RATE) ? 1256 PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR; 1257 1258 arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 : 1259 (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg; 1260 err = mtk_hw_set_value(hw, pin, reg, arg); 1261 if (err) 1262 goto err; 1263 1264 break; 1265 case PIN_CONFIG_OUTPUT: 1266 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, 1267 MTK_OUTPUT); 1268 if (err) 1269 goto err; 1270 1271 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO, 1272 arg); 1273 if (err) 1274 goto err; 1275 break; 1276 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1277 /* arg = 1: Input mode & SMT enable ; 1278 * arg = 0: Output mode & SMT disable 1279 */ 1280 arg = arg ? 2 : 1; 1281 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, 1282 arg & 1); 1283 if (err) 1284 goto err; 1285 1286 err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, 1287 !!(arg & 2)); 1288 if (err) 1289 goto err; 1290 break; 1291 case PIN_CONFIG_DRIVE_STRENGTH: 1292 /* 4mA when (e8, e4) = (0, 0); 1293 * 8mA when (e8, e4) = (0, 1); 1294 * 12mA when (e8, e4) = (1, 0); 1295 * 16mA when (e8, e4) = (1, 1) 1296 */ 1297 if (!(arg % 4) && (arg >= 4 && arg <= 16)) { 1298 arg = arg / 4 - 1; 1299 err = mtk_hw_set_value(hw, pin, 1300 PINCTRL_PIN_REG_E4, 1301 arg & 0x1); 1302 if (err) 1303 goto err; 1304 1305 err = mtk_hw_set_value(hw, pin, 1306 PINCTRL_PIN_REG_E8, 1307 (arg & 0x2) >> 1); 1308 if (err) 1309 goto err; 1310 } else { 1311 err = -ENOTSUPP; 1312 } 1313 break; 1314 case MTK_PIN_CONFIG_TDSEL: 1315 case MTK_PIN_CONFIG_RDSEL: 1316 reg = (param == MTK_PIN_CONFIG_TDSEL) ? 1317 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; 1318 1319 err = mtk_hw_set_value(hw, pin, reg, arg); 1320 if (err) 1321 goto err; 1322 break; 1323 default: 1324 err = -ENOTSUPP; 1325 } 1326 } 1327 err: 1328 return err; 1329 } 1330 1331 static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, 1332 unsigned int group, unsigned long *config) 1333 { 1334 const unsigned int *pins; 1335 unsigned int i, npins, old = 0; 1336 int ret; 1337 1338 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1339 if (ret) 1340 return ret; 1341 1342 for (i = 0; i < npins; i++) { 1343 if (mtk_pinconf_get(pctldev, pins[i], config)) 1344 return -ENOTSUPP; 1345 1346 /* configs do not match between two pins */ 1347 if (i && old != *config) 1348 return -ENOTSUPP; 1349 1350 old = *config; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev, 1357 unsigned int group, unsigned long *configs, 1358 unsigned int num_configs) 1359 { 1360 const unsigned int *pins; 1361 unsigned int i, npins; 1362 int ret; 1363 1364 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1365 if (ret) 1366 return ret; 1367 1368 for (i = 0; i < npins; i++) { 1369 ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs); 1370 if (ret) 1371 return ret; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static const struct pinctrl_ops mtk_pctlops = { 1378 .get_groups_count = pinctrl_generic_get_group_count, 1379 .get_group_name = pinctrl_generic_get_group_name, 1380 .get_group_pins = pinctrl_generic_get_group_pins, 1381 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1382 .dt_free_map = pinconf_generic_dt_free_map, 1383 }; 1384 1385 static const struct pinmux_ops mtk_pmxops = { 1386 .get_functions_count = pinmux_generic_get_function_count, 1387 .get_function_name = pinmux_generic_get_function_name, 1388 .get_function_groups = pinmux_generic_get_function_groups, 1389 .set_mux = mtk_pinmux_set_mux, 1390 .gpio_request_enable = mtk_pinmux_gpio_request_enable, 1391 .gpio_set_direction = mtk_pinmux_gpio_set_direction, 1392 .strict = true, 1393 }; 1394 1395 static const struct pinconf_ops mtk_confops = { 1396 .is_generic = true, 1397 .pin_config_get = mtk_pinconf_get, 1398 .pin_config_set = mtk_pinconf_set, 1399 .pin_config_group_get = mtk_pinconf_group_get, 1400 .pin_config_group_set = mtk_pinconf_group_set, 1401 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1402 }; 1403 1404 static struct pinctrl_desc mtk_desc = { 1405 .name = PINCTRL_PINCTRL_DEV, 1406 .pctlops = &mtk_pctlops, 1407 .pmxops = &mtk_pmxops, 1408 .confops = &mtk_confops, 1409 .owner = THIS_MODULE, 1410 }; 1411 1412 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) 1413 { 1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); 1415 int value, err; 1416 1417 err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); 1418 if (err) 1419 return err; 1420 1421 return !!value; 1422 } 1423 1424 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 1425 { 1426 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); 1427 1428 mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value); 1429 } 1430 1431 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 1432 { 1433 return pinctrl_gpio_direction_input(chip->base + gpio); 1434 } 1435 1436 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 1437 int value) 1438 { 1439 mtk_gpio_set(chip, gpio, value); 1440 1441 return pinctrl_gpio_direction_output(chip->base + gpio); 1442 } 1443 1444 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) 1445 { 1446 struct gpio_chip *chip = &hw->chip; 1447 int ret; 1448 1449 chip->label = PINCTRL_PINCTRL_DEV; 1450 chip->parent = hw->dev; 1451 chip->request = gpiochip_generic_request; 1452 chip->free = gpiochip_generic_free; 1453 chip->direction_input = mtk_gpio_direction_input; 1454 chip->direction_output = mtk_gpio_direction_output; 1455 chip->get = mtk_gpio_get; 1456 chip->set = mtk_gpio_set; 1457 chip->base = -1; 1458 chip->ngpio = hw->soc->npins; 1459 chip->of_node = np; 1460 chip->of_gpio_n_cells = 2; 1461 1462 ret = gpiochip_add_data(chip, hw); 1463 if (ret < 0) 1464 return ret; 1465 1466 ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, 1467 chip->ngpio); 1468 if (ret < 0) { 1469 gpiochip_remove(chip); 1470 return ret; 1471 } 1472 1473 return 0; 1474 } 1475 1476 static int mtk_build_groups(struct mtk_pinctrl *hw) 1477 { 1478 int err, i; 1479 1480 for (i = 0; i < hw->soc->ngrps; i++) { 1481 const struct group_desc *group = hw->soc->grps + i; 1482 1483 err = pinctrl_generic_add_group(hw->pctrl, group->name, 1484 group->pins, group->num_pins, 1485 group->data); 1486 if (err) { 1487 dev_err(hw->dev, "Failed to register group %s\n", 1488 group->name); 1489 return err; 1490 } 1491 } 1492 1493 return 0; 1494 } 1495 1496 static int mtk_build_functions(struct mtk_pinctrl *hw) 1497 { 1498 int i, err; 1499 1500 for (i = 0; i < hw->soc->nfuncs ; i++) { 1501 const struct function_desc *func = hw->soc->funcs + i; 1502 1503 err = pinmux_generic_add_function(hw->pctrl, func->name, 1504 func->group_names, 1505 func->num_group_names, 1506 func->data); 1507 if (err) { 1508 dev_err(hw->dev, "Failed to register function %s\n", 1509 func->name); 1510 return err; 1511 } 1512 } 1513 1514 return 0; 1515 } 1516 1517 static const struct of_device_id mtk_pinctrl_of_match[] = { 1518 { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data}, 1519 { } 1520 }; 1521 1522 static int mtk_pinctrl_probe(struct platform_device *pdev) 1523 { 1524 struct resource *res; 1525 struct mtk_pinctrl *hw; 1526 const struct of_device_id *of_id = 1527 of_match_device(mtk_pinctrl_of_match, &pdev->dev); 1528 int err; 1529 1530 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); 1531 if (!hw) 1532 return -ENOMEM; 1533 1534 hw->soc = of_id->data; 1535 1536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1537 if (!res) { 1538 dev_err(&pdev->dev, "missing IO resource\n"); 1539 return -ENXIO; 1540 } 1541 1542 hw->dev = &pdev->dev; 1543 hw->base = devm_ioremap_resource(&pdev->dev, res); 1544 if (IS_ERR(hw->base)) 1545 return PTR_ERR(hw->base); 1546 1547 /* Setup pins descriptions per SoC types */ 1548 mtk_desc.pins = hw->soc->pins; 1549 mtk_desc.npins = hw->soc->npins; 1550 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); 1551 mtk_desc.custom_params = mtk_custom_bindings; 1552 #ifdef CONFIG_DEBUG_FS 1553 mtk_desc.custom_conf_items = mtk_conf_items; 1554 #endif 1555 1556 hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw); 1557 if (IS_ERR(hw->pctrl)) 1558 return PTR_ERR(hw->pctrl); 1559 1560 /* Setup groups descriptions per SoC types */ 1561 err = mtk_build_groups(hw); 1562 if (err) { 1563 dev_err(&pdev->dev, "Failed to build groups\n"); 1564 return 0; 1565 } 1566 1567 /* Setup functions descriptions per SoC types */ 1568 err = mtk_build_functions(hw); 1569 if (err) { 1570 dev_err(&pdev->dev, "Failed to build functions\n"); 1571 return err; 1572 } 1573 1574 err = mtk_build_gpiochip(hw, pdev->dev.of_node); 1575 if (err) { 1576 dev_err(&pdev->dev, "Failed to add gpio_chip\n"); 1577 return err; 1578 } 1579 1580 platform_set_drvdata(pdev, hw); 1581 1582 return 0; 1583 } 1584 1585 static struct platform_driver mtk_pinctrl_driver = { 1586 .driver = { 1587 .name = "mtk-pinctrl", 1588 .of_match_table = mtk_pinctrl_of_match, 1589 }, 1590 .probe = mtk_pinctrl_probe, 1591 }; 1592 1593 static int __init mtk_pinctrl_init(void) 1594 { 1595 return platform_driver_register(&mtk_pinctrl_driver); 1596 } 1597 arch_initcall(mtk_pinctrl_init); 1598