1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2014-2018 MediaTek Inc. 3 4 /* 5 * Library for MediaTek External Interrupt Support 6 * 7 * Author: Maoguang Meng <maoguang.meng@mediatek.com> 8 * Sean Wang <sean.wang@mediatek.com> 9 * 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/gpio.h> 15 #include <linux/io.h> 16 #include <linux/irqchip/chained_irq.h> 17 #include <linux/irqdomain.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 21 #include "mtk-eint.h" 22 23 #define MTK_EINT_EDGE_SENSITIVE 0 24 #define MTK_EINT_LEVEL_SENSITIVE 1 25 #define MTK_EINT_DBNC_SET_DBNC_BITS 4 26 #define MTK_EINT_DBNC_RST_BIT (0x1 << 1) 27 #define MTK_EINT_DBNC_SET_EN (0x1 << 0) 28 29 static const struct mtk_eint_regs mtk_generic_eint_regs = { 30 .stat = 0x000, 31 .ack = 0x040, 32 .mask = 0x080, 33 .mask_set = 0x0c0, 34 .mask_clr = 0x100, 35 .sens = 0x140, 36 .sens_set = 0x180, 37 .sens_clr = 0x1c0, 38 .soft = 0x200, 39 .soft_set = 0x240, 40 .soft_clr = 0x280, 41 .pol = 0x300, 42 .pol_set = 0x340, 43 .pol_clr = 0x380, 44 .dom_en = 0x400, 45 .dbnc_ctrl = 0x500, 46 .dbnc_set = 0x600, 47 .dbnc_clr = 0x700, 48 }; 49 50 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, 51 unsigned int eint_num, 52 unsigned int offset) 53 { 54 unsigned int eint_base = 0; 55 void __iomem *reg; 56 57 if (eint_num >= eint->hw->ap_num) 58 eint_base = eint->hw->ap_num; 59 60 reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; 61 62 return reg; 63 } 64 65 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint, 66 unsigned int eint_num) 67 { 68 unsigned int sens; 69 unsigned int bit = BIT(eint_num % 32); 70 void __iomem *reg = mtk_eint_get_offset(eint, eint_num, 71 eint->regs->sens); 72 73 if (readl(reg) & bit) 74 sens = MTK_EINT_LEVEL_SENSITIVE; 75 else 76 sens = MTK_EINT_EDGE_SENSITIVE; 77 78 if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE) 79 return 1; 80 else 81 return 0; 82 } 83 84 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) 85 { 86 int start_level, curr_level; 87 unsigned int reg_offset; 88 u32 mask = BIT(hwirq & 0x1f); 89 u32 port = (hwirq >> 5) & eint->hw->port_mask; 90 void __iomem *reg = eint->base + (port << 2); 91 92 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); 93 94 do { 95 start_level = curr_level; 96 if (start_level) 97 reg_offset = eint->regs->pol_clr; 98 else 99 reg_offset = eint->regs->pol_set; 100 writel(mask, reg + reg_offset); 101 102 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, 103 hwirq); 104 } while (start_level != curr_level); 105 106 return start_level; 107 } 108 109 static void mtk_eint_mask(struct irq_data *d) 110 { 111 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 112 u32 mask = BIT(d->hwirq & 0x1f); 113 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 114 eint->regs->mask_set); 115 116 writel(mask, reg); 117 } 118 119 static void mtk_eint_unmask(struct irq_data *d) 120 { 121 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 122 u32 mask = BIT(d->hwirq & 0x1f); 123 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 124 eint->regs->mask_clr); 125 126 writel(mask, reg); 127 128 if (eint->dual_edge[d->hwirq]) 129 mtk_eint_flip_edge(eint, d->hwirq); 130 } 131 132 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint, 133 unsigned int eint_num) 134 { 135 unsigned int bit = BIT(eint_num % 32); 136 void __iomem *reg = mtk_eint_get_offset(eint, eint_num, 137 eint->regs->mask); 138 139 return !!(readl(reg) & bit); 140 } 141 142 static void mtk_eint_ack(struct irq_data *d) 143 { 144 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 145 u32 mask = BIT(d->hwirq & 0x1f); 146 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 147 eint->regs->ack); 148 149 writel(mask, reg); 150 } 151 152 static int mtk_eint_set_type(struct irq_data *d, unsigned int type) 153 { 154 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 155 u32 mask = BIT(d->hwirq & 0x1f); 156 void __iomem *reg; 157 158 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || 159 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { 160 dev_err(eint->dev, 161 "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", 162 d->irq, d->hwirq, type); 163 return -EINVAL; 164 } 165 166 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 167 eint->dual_edge[d->hwirq] = 1; 168 else 169 eint->dual_edge[d->hwirq] = 0; 170 171 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { 172 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); 173 writel(mask, reg); 174 } else { 175 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set); 176 writel(mask, reg); 177 } 178 179 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 180 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); 181 writel(mask, reg); 182 } else { 183 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set); 184 writel(mask, reg); 185 } 186 187 if (eint->dual_edge[d->hwirq]) 188 mtk_eint_flip_edge(eint, d->hwirq); 189 190 return 0; 191 } 192 193 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) 194 { 195 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 196 int shift = d->hwirq & 0x1f; 197 int reg = d->hwirq >> 5; 198 199 if (on) 200 eint->wake_mask[reg] |= BIT(shift); 201 else 202 eint->wake_mask[reg] &= ~BIT(shift); 203 204 return 0; 205 } 206 207 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint, 208 void __iomem *base, u32 *buf) 209 { 210 int port; 211 void __iomem *reg; 212 213 for (port = 0; port < eint->hw->ports; port++) { 214 reg = base + (port << 2); 215 writel_relaxed(~buf[port], reg + eint->regs->mask_set); 216 writel_relaxed(buf[port], reg + eint->regs->mask_clr); 217 } 218 } 219 220 static void mtk_eint_chip_read_mask(const struct mtk_eint *eint, 221 void __iomem *base, u32 *buf) 222 { 223 int port; 224 void __iomem *reg; 225 226 for (port = 0; port < eint->hw->ports; port++) { 227 reg = base + eint->regs->mask + (port << 2); 228 buf[port] = ~readl_relaxed(reg); 229 /* Mask is 0 when irq is enabled, and 1 when disabled. */ 230 } 231 } 232 233 static int mtk_eint_irq_request_resources(struct irq_data *d) 234 { 235 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 236 struct gpio_chip *gpio_c; 237 unsigned int gpio_n; 238 int err; 239 240 err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, 241 &gpio_n, &gpio_c); 242 if (err < 0) { 243 dev_err(eint->dev, "Can not find pin\n"); 244 return err; 245 } 246 247 err = gpiochip_lock_as_irq(gpio_c, gpio_n); 248 if (err < 0) { 249 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n", 250 irqd_to_hwirq(d)); 251 return err; 252 } 253 254 err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq); 255 if (err < 0) { 256 dev_err(eint->dev, "Can not eint mode\n"); 257 return err; 258 } 259 260 return 0; 261 } 262 263 static void mtk_eint_irq_release_resources(struct irq_data *d) 264 { 265 struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 266 struct gpio_chip *gpio_c; 267 unsigned int gpio_n; 268 269 eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n, 270 &gpio_c); 271 272 gpiochip_unlock_as_irq(gpio_c, gpio_n); 273 } 274 275 static struct irq_chip mtk_eint_irq_chip = { 276 .name = "mt-eint", 277 .irq_disable = mtk_eint_mask, 278 .irq_mask = mtk_eint_mask, 279 .irq_unmask = mtk_eint_unmask, 280 .irq_ack = mtk_eint_ack, 281 .irq_set_type = mtk_eint_set_type, 282 .irq_set_wake = mtk_eint_irq_set_wake, 283 .irq_request_resources = mtk_eint_irq_request_resources, 284 .irq_release_resources = mtk_eint_irq_release_resources, 285 }; 286 287 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint) 288 { 289 void __iomem *reg = eint->base + eint->regs->dom_en; 290 unsigned int i; 291 292 for (i = 0; i < eint->hw->ap_num; i += 32) { 293 writel(0xffffffff, reg); 294 reg += 4; 295 } 296 297 return 0; 298 } 299 300 static inline void 301 mtk_eint_debounce_process(struct mtk_eint *eint, int index) 302 { 303 unsigned int rst, ctrl_offset; 304 unsigned int bit, dbnc; 305 306 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; 307 dbnc = readl(eint->base + ctrl_offset); 308 bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8); 309 if ((bit & dbnc) > 0) { 310 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; 311 rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8); 312 writel(rst, eint->base + ctrl_offset); 313 } 314 } 315 316 static void mtk_eint_irq_handler(struct irq_desc *desc) 317 { 318 struct irq_chip *chip = irq_desc_get_chip(desc); 319 struct mtk_eint *eint = irq_desc_get_handler_data(desc); 320 unsigned int status, eint_num; 321 int offset, index, virq; 322 void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat); 323 int dual_edge, start_level, curr_level; 324 325 chained_irq_enter(chip, desc); 326 for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32, 327 reg += 4) { 328 status = readl(reg); 329 while (status) { 330 offset = __ffs(status); 331 index = eint_num + offset; 332 virq = irq_find_mapping(eint->domain, index); 333 status &= ~BIT(offset); 334 335 dual_edge = eint->dual_edge[index]; 336 if (dual_edge) { 337 /* 338 * Clear soft-irq in case we raised it last 339 * time. 340 */ 341 writel(BIT(offset), reg - eint->regs->stat + 342 eint->regs->soft_clr); 343 344 start_level = 345 eint->gpio_xlate->get_gpio_state(eint->pctl, 346 index); 347 } 348 349 generic_handle_irq(virq); 350 351 if (dual_edge) { 352 curr_level = mtk_eint_flip_edge(eint, index); 353 354 /* 355 * If level changed, we might lost one edge 356 * interrupt, raised it through soft-irq. 357 */ 358 if (start_level != curr_level) 359 writel(BIT(offset), reg - 360 eint->regs->stat + 361 eint->regs->soft_set); 362 } 363 364 if (index < eint->hw->db_cnt) 365 mtk_eint_debounce_process(eint, index); 366 } 367 } 368 chained_irq_exit(chip, desc); 369 } 370 371 int mtk_eint_do_suspend(struct mtk_eint *eint) 372 { 373 mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask); 374 mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); 375 376 return 0; 377 } 378 379 int mtk_eint_do_resume(struct mtk_eint *eint) 380 { 381 mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); 382 383 return 0; 384 } 385 386 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, 387 unsigned int debounce) 388 { 389 int virq, eint_offset; 390 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, 391 dbnc; 392 static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 393 64000, 128000, 256000}; 394 struct irq_data *d; 395 396 virq = irq_find_mapping(eint->domain, eint_num); 397 eint_offset = (eint_num % 4) * 8; 398 d = irq_get_irq_data(virq); 399 400 set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set; 401 clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr; 402 403 if (!mtk_eint_can_en_debounce(eint, eint_num)) 404 return -EINVAL; 405 406 dbnc = ARRAY_SIZE(debounce_time); 407 for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { 408 if (debounce <= debounce_time[i]) { 409 dbnc = i; 410 break; 411 } 412 } 413 414 if (!mtk_eint_get_mask(eint, eint_num)) { 415 mtk_eint_mask(d); 416 unmask = 1; 417 } else { 418 unmask = 0; 419 } 420 421 clr_bit = 0xff << eint_offset; 422 writel(clr_bit, eint->base + clr_offset); 423 424 bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) << 425 eint_offset; 426 rst = MTK_EINT_DBNC_RST_BIT << eint_offset; 427 writel(rst | bit, eint->base + set_offset); 428 429 /* 430 * Delay a while (more than 2T) to wait for hw debounce counter reset 431 * work correctly. 432 */ 433 udelay(1); 434 if (unmask == 1) 435 mtk_eint_unmask(d); 436 437 return 0; 438 } 439 440 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) 441 { 442 int irq; 443 444 irq = irq_find_mapping(eint->domain, eint_n); 445 if (!irq) 446 return -EINVAL; 447 448 return irq; 449 } 450 451 int mtk_eint_do_init(struct mtk_eint *eint) 452 { 453 int i; 454 455 /* If clients don't assign a specific regs, let's use generic one */ 456 if (!eint->regs) 457 eint->regs = &mtk_generic_eint_regs; 458 459 eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports, 460 sizeof(*eint->wake_mask), GFP_KERNEL); 461 if (!eint->wake_mask) 462 return -ENOMEM; 463 464 eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports, 465 sizeof(*eint->cur_mask), GFP_KERNEL); 466 if (!eint->cur_mask) 467 return -ENOMEM; 468 469 eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num, 470 sizeof(int), GFP_KERNEL); 471 if (!eint->dual_edge) 472 return -ENOMEM; 473 474 eint->domain = irq_domain_add_linear(eint->dev->of_node, 475 eint->hw->ap_num, 476 &irq_domain_simple_ops, NULL); 477 if (!eint->domain) 478 return -ENOMEM; 479 480 mtk_eint_hw_init(eint); 481 for (i = 0; i < eint->hw->ap_num; i++) { 482 int virq = irq_create_mapping(eint->domain, i); 483 484 irq_set_chip_and_handler(virq, &mtk_eint_irq_chip, 485 handle_level_irq); 486 irq_set_chip_data(virq, eint); 487 } 488 489 irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, 490 eint); 491 492 return 0; 493 } 494