1e46df235SSean Wang // SPDX-License-Identifier: GPL-2.0 2e46df235SSean Wang // Copyright (c) 2014-2018 MediaTek Inc. 3e46df235SSean Wang 4e46df235SSean Wang /* 5e46df235SSean Wang * Library for MediaTek External Interrupt Support 6e46df235SSean Wang * 7e46df235SSean Wang * Author: Maoguang Meng <maoguang.meng@mediatek.com> 8e46df235SSean Wang * Sean Wang <sean.wang@mediatek.com> 9e46df235SSean Wang * 10e46df235SSean Wang */ 11e46df235SSean Wang 12e46df235SSean Wang #include <linux/delay.h> 13e46df235SSean Wang #include <linux/err.h> 141c5fb66aSLinus Walleij #include <linux/gpio/driver.h> 15e46df235SSean Wang #include <linux/io.h> 16a8cfcf15SArnd Bergmann #include <linux/irqchip/chained_irq.h> 17e46df235SSean Wang #include <linux/irqdomain.h> 18e46df235SSean Wang #include <linux/of_irq.h> 19e46df235SSean Wang #include <linux/platform_device.h> 20e46df235SSean Wang 21e46df235SSean Wang #include "mtk-eint.h" 22e46df235SSean Wang 23e46df235SSean Wang #define MTK_EINT_EDGE_SENSITIVE 0 24e46df235SSean Wang #define MTK_EINT_LEVEL_SENSITIVE 1 25e46df235SSean Wang #define MTK_EINT_DBNC_SET_DBNC_BITS 4 26e46df235SSean Wang #define MTK_EINT_DBNC_RST_BIT (0x1 << 1) 27e46df235SSean Wang #define MTK_EINT_DBNC_SET_EN (0x1 << 0) 28e46df235SSean Wang 29e46df235SSean Wang static const struct mtk_eint_regs mtk_generic_eint_regs = { 30e46df235SSean Wang .stat = 0x000, 31e46df235SSean Wang .ack = 0x040, 32e46df235SSean Wang .mask = 0x080, 33e46df235SSean Wang .mask_set = 0x0c0, 34e46df235SSean Wang .mask_clr = 0x100, 35e46df235SSean Wang .sens = 0x140, 36e46df235SSean Wang .sens_set = 0x180, 37e46df235SSean Wang .sens_clr = 0x1c0, 38e46df235SSean Wang .soft = 0x200, 39e46df235SSean Wang .soft_set = 0x240, 40e46df235SSean Wang .soft_clr = 0x280, 41e46df235SSean Wang .pol = 0x300, 42e46df235SSean Wang .pol_set = 0x340, 43e46df235SSean Wang .pol_clr = 0x380, 44e46df235SSean Wang .dom_en = 0x400, 45e46df235SSean Wang .dbnc_ctrl = 0x500, 46e46df235SSean Wang .dbnc_set = 0x600, 47e46df235SSean Wang .dbnc_clr = 0x700, 48e46df235SSean Wang }; 49e46df235SSean Wang 50e46df235SSean Wang static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, 51e46df235SSean Wang unsigned int eint_num, 52e46df235SSean Wang unsigned int offset) 53e46df235SSean Wang { 54e46df235SSean Wang unsigned int eint_base = 0; 55e46df235SSean Wang void __iomem *reg; 56e46df235SSean Wang 57e46df235SSean Wang if (eint_num >= eint->hw->ap_num) 58e46df235SSean Wang eint_base = eint->hw->ap_num; 59e46df235SSean Wang 60e46df235SSean Wang reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; 61e46df235SSean Wang 62e46df235SSean Wang return reg; 63e46df235SSean Wang } 64e46df235SSean Wang 65e46df235SSean Wang static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint, 66e46df235SSean Wang unsigned int eint_num) 67e46df235SSean Wang { 68e46df235SSean Wang unsigned int sens; 69e46df235SSean Wang unsigned int bit = BIT(eint_num % 32); 70e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, eint_num, 71e46df235SSean Wang eint->regs->sens); 72e46df235SSean Wang 73e46df235SSean Wang if (readl(reg) & bit) 74e46df235SSean Wang sens = MTK_EINT_LEVEL_SENSITIVE; 75e46df235SSean Wang else 76e46df235SSean Wang sens = MTK_EINT_EDGE_SENSITIVE; 77e46df235SSean Wang 78e46df235SSean Wang if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE) 79e46df235SSean Wang return 1; 80e46df235SSean Wang else 81e46df235SSean Wang return 0; 82e46df235SSean Wang } 83e46df235SSean Wang 84e46df235SSean Wang static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) 85e46df235SSean Wang { 86e46df235SSean Wang int start_level, curr_level; 87e46df235SSean Wang unsigned int reg_offset; 88e46df235SSean Wang u32 mask = BIT(hwirq & 0x1f); 89e46df235SSean Wang u32 port = (hwirq >> 5) & eint->hw->port_mask; 90e46df235SSean Wang void __iomem *reg = eint->base + (port << 2); 91e46df235SSean Wang 92e46df235SSean Wang curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); 93e46df235SSean Wang 94e46df235SSean Wang do { 95e46df235SSean Wang start_level = curr_level; 96e46df235SSean Wang if (start_level) 97e46df235SSean Wang reg_offset = eint->regs->pol_clr; 98e46df235SSean Wang else 99e46df235SSean Wang reg_offset = eint->regs->pol_set; 100e46df235SSean Wang writel(mask, reg + reg_offset); 101e46df235SSean Wang 102e46df235SSean Wang curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, 103e46df235SSean Wang hwirq); 104e46df235SSean Wang } while (start_level != curr_level); 105e46df235SSean Wang 106e46df235SSean Wang return start_level; 107e46df235SSean Wang } 108e46df235SSean Wang 109e46df235SSean Wang static void mtk_eint_mask(struct irq_data *d) 110e46df235SSean Wang { 111e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 112e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f); 113e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 114e46df235SSean Wang eint->regs->mask_set); 115e46df235SSean Wang 116e46df235SSean Wang writel(mask, reg); 117e46df235SSean Wang } 118e46df235SSean Wang 119e46df235SSean Wang static void mtk_eint_unmask(struct irq_data *d) 120e46df235SSean Wang { 121e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 122e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f); 123e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 124e46df235SSean Wang eint->regs->mask_clr); 125e46df235SSean Wang 126e46df235SSean Wang writel(mask, reg); 127e46df235SSean Wang 128e46df235SSean Wang if (eint->dual_edge[d->hwirq]) 129e46df235SSean Wang mtk_eint_flip_edge(eint, d->hwirq); 130e46df235SSean Wang } 131e46df235SSean Wang 132e46df235SSean Wang static unsigned int mtk_eint_get_mask(struct mtk_eint *eint, 133e46df235SSean Wang unsigned int eint_num) 134e46df235SSean Wang { 135e46df235SSean Wang unsigned int bit = BIT(eint_num % 32); 136e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, eint_num, 137e46df235SSean Wang eint->regs->mask); 138e46df235SSean Wang 139e46df235SSean Wang return !!(readl(reg) & bit); 140e46df235SSean Wang } 141e46df235SSean Wang 142e46df235SSean Wang static void mtk_eint_ack(struct irq_data *d) 143e46df235SSean Wang { 144e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 145e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f); 146e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, 147e46df235SSean Wang eint->regs->ack); 148e46df235SSean Wang 149e46df235SSean Wang writel(mask, reg); 150e46df235SSean Wang } 151e46df235SSean Wang 152e46df235SSean Wang static int mtk_eint_set_type(struct irq_data *d, unsigned int type) 153e46df235SSean Wang { 154e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 155e46df235SSean Wang u32 mask = BIT(d->hwirq & 0x1f); 156e46df235SSean Wang void __iomem *reg; 157e46df235SSean Wang 158e46df235SSean Wang if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || 159e46df235SSean Wang ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { 160e46df235SSean Wang dev_err(eint->dev, 161e46df235SSean Wang "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", 162e46df235SSean Wang d->irq, d->hwirq, type); 163e46df235SSean Wang return -EINVAL; 164e46df235SSean Wang } 165e46df235SSean Wang 166e46df235SSean Wang if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 167e46df235SSean Wang eint->dual_edge[d->hwirq] = 1; 168e46df235SSean Wang else 169e46df235SSean Wang eint->dual_edge[d->hwirq] = 0; 170e46df235SSean Wang 171e46df235SSean Wang if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { 172e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); 173e46df235SSean Wang writel(mask, reg); 174e46df235SSean Wang } else { 175e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set); 176e46df235SSean Wang writel(mask, reg); 177e46df235SSean Wang } 178e46df235SSean Wang 179e46df235SSean Wang if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 180e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); 181e46df235SSean Wang writel(mask, reg); 182e46df235SSean Wang } else { 183e46df235SSean Wang reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set); 184e46df235SSean Wang writel(mask, reg); 185e46df235SSean Wang } 186e46df235SSean Wang 187e46df235SSean Wang if (eint->dual_edge[d->hwirq]) 188e46df235SSean Wang mtk_eint_flip_edge(eint, d->hwirq); 189e46df235SSean Wang 190e46df235SSean Wang return 0; 191e46df235SSean Wang } 192e46df235SSean Wang 193e46df235SSean Wang static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) 194e46df235SSean Wang { 195e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 196e46df235SSean Wang int shift = d->hwirq & 0x1f; 197e46df235SSean Wang int reg = d->hwirq >> 5; 198e46df235SSean Wang 199e46df235SSean Wang if (on) 200e46df235SSean Wang eint->wake_mask[reg] |= BIT(shift); 201e46df235SSean Wang else 202e46df235SSean Wang eint->wake_mask[reg] &= ~BIT(shift); 203e46df235SSean Wang 204e46df235SSean Wang return 0; 205e46df235SSean Wang } 206e46df235SSean Wang 207e46df235SSean Wang static void mtk_eint_chip_write_mask(const struct mtk_eint *eint, 208e46df235SSean Wang void __iomem *base, u32 *buf) 209e46df235SSean Wang { 210e46df235SSean Wang int port; 211e46df235SSean Wang void __iomem *reg; 212e46df235SSean Wang 213e46df235SSean Wang for (port = 0; port < eint->hw->ports; port++) { 214e46df235SSean Wang reg = base + (port << 2); 215e46df235SSean Wang writel_relaxed(~buf[port], reg + eint->regs->mask_set); 216e46df235SSean Wang writel_relaxed(buf[port], reg + eint->regs->mask_clr); 217e46df235SSean Wang } 218e46df235SSean Wang } 219e46df235SSean Wang 220e46df235SSean Wang static void mtk_eint_chip_read_mask(const struct mtk_eint *eint, 221e46df235SSean Wang void __iomem *base, u32 *buf) 222e46df235SSean Wang { 223e46df235SSean Wang int port; 224e46df235SSean Wang void __iomem *reg; 225e46df235SSean Wang 226e46df235SSean Wang for (port = 0; port < eint->hw->ports; port++) { 227e46df235SSean Wang reg = base + eint->regs->mask + (port << 2); 228e46df235SSean Wang buf[port] = ~readl_relaxed(reg); 229e46df235SSean Wang /* Mask is 0 when irq is enabled, and 1 when disabled. */ 230e46df235SSean Wang } 231e46df235SSean Wang } 232e46df235SSean Wang 233e46df235SSean Wang static int mtk_eint_irq_request_resources(struct irq_data *d) 234e46df235SSean Wang { 235e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 236e46df235SSean Wang struct gpio_chip *gpio_c; 237e46df235SSean Wang unsigned int gpio_n; 238e46df235SSean Wang int err; 239e46df235SSean Wang 240e46df235SSean Wang err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, 241e46df235SSean Wang &gpio_n, &gpio_c); 242e46df235SSean Wang if (err < 0) { 243e46df235SSean Wang dev_err(eint->dev, "Can not find pin\n"); 244e46df235SSean Wang return err; 245e46df235SSean Wang } 246e46df235SSean Wang 247e46df235SSean Wang err = gpiochip_lock_as_irq(gpio_c, gpio_n); 248e46df235SSean Wang if (err < 0) { 249e46df235SSean Wang dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n", 250e46df235SSean Wang irqd_to_hwirq(d)); 251e46df235SSean Wang return err; 252e46df235SSean Wang } 253e46df235SSean Wang 254e46df235SSean Wang err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq); 255e46df235SSean Wang if (err < 0) { 256e46df235SSean Wang dev_err(eint->dev, "Can not eint mode\n"); 257e46df235SSean Wang return err; 258e46df235SSean Wang } 259e46df235SSean Wang 260e46df235SSean Wang return 0; 261e46df235SSean Wang } 262e46df235SSean Wang 263e46df235SSean Wang static void mtk_eint_irq_release_resources(struct irq_data *d) 264e46df235SSean Wang { 265e46df235SSean Wang struct mtk_eint *eint = irq_data_get_irq_chip_data(d); 266e46df235SSean Wang struct gpio_chip *gpio_c; 267e46df235SSean Wang unsigned int gpio_n; 268e46df235SSean Wang 269e46df235SSean Wang eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n, 270e46df235SSean Wang &gpio_c); 271e46df235SSean Wang 272e46df235SSean Wang gpiochip_unlock_as_irq(gpio_c, gpio_n); 273e46df235SSean Wang } 274e46df235SSean Wang 275e46df235SSean Wang static struct irq_chip mtk_eint_irq_chip = { 276e46df235SSean Wang .name = "mt-eint", 277e46df235SSean Wang .irq_disable = mtk_eint_mask, 278e46df235SSean Wang .irq_mask = mtk_eint_mask, 279e46df235SSean Wang .irq_unmask = mtk_eint_unmask, 280e46df235SSean Wang .irq_ack = mtk_eint_ack, 281e46df235SSean Wang .irq_set_type = mtk_eint_set_type, 282e46df235SSean Wang .irq_set_wake = mtk_eint_irq_set_wake, 283e46df235SSean Wang .irq_request_resources = mtk_eint_irq_request_resources, 284e46df235SSean Wang .irq_release_resources = mtk_eint_irq_release_resources, 285e46df235SSean Wang }; 286e46df235SSean Wang 287e46df235SSean Wang static unsigned int mtk_eint_hw_init(struct mtk_eint *eint) 288e46df235SSean Wang { 289e46df235SSean Wang void __iomem *reg = eint->base + eint->regs->dom_en; 290e46df235SSean Wang unsigned int i; 291e46df235SSean Wang 292e46df235SSean Wang for (i = 0; i < eint->hw->ap_num; i += 32) { 293e46df235SSean Wang writel(0xffffffff, reg); 294e46df235SSean Wang reg += 4; 295e46df235SSean Wang } 296e46df235SSean Wang 297e46df235SSean Wang return 0; 298e46df235SSean Wang } 299e46df235SSean Wang 300e46df235SSean Wang static inline void 301e46df235SSean Wang mtk_eint_debounce_process(struct mtk_eint *eint, int index) 302e46df235SSean Wang { 303e46df235SSean Wang unsigned int rst, ctrl_offset; 304e46df235SSean Wang unsigned int bit, dbnc; 305e46df235SSean Wang 306e46df235SSean Wang ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; 307e46df235SSean Wang dbnc = readl(eint->base + ctrl_offset); 308e46df235SSean Wang bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8); 309e46df235SSean Wang if ((bit & dbnc) > 0) { 310e46df235SSean Wang ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; 311e46df235SSean Wang rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8); 312e46df235SSean Wang writel(rst, eint->base + ctrl_offset); 313e46df235SSean Wang } 314e46df235SSean Wang } 315e46df235SSean Wang 316e46df235SSean Wang static void mtk_eint_irq_handler(struct irq_desc *desc) 317e46df235SSean Wang { 318e46df235SSean Wang struct irq_chip *chip = irq_desc_get_chip(desc); 319e46df235SSean Wang struct mtk_eint *eint = irq_desc_get_handler_data(desc); 320e46df235SSean Wang unsigned int status, eint_num; 321e46df235SSean Wang int offset, index, virq; 322e46df235SSean Wang void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat); 323e46df235SSean Wang int dual_edge, start_level, curr_level; 324e46df235SSean Wang 325e46df235SSean Wang chained_irq_enter(chip, desc); 326e46df235SSean Wang for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32, 327e46df235SSean Wang reg += 4) { 328e46df235SSean Wang status = readl(reg); 329e46df235SSean Wang while (status) { 330e46df235SSean Wang offset = __ffs(status); 331e46df235SSean Wang index = eint_num + offset; 332e46df235SSean Wang virq = irq_find_mapping(eint->domain, index); 333e46df235SSean Wang status &= ~BIT(offset); 334e46df235SSean Wang 335e46df235SSean Wang dual_edge = eint->dual_edge[index]; 336e46df235SSean Wang if (dual_edge) { 337e46df235SSean Wang /* 338e46df235SSean Wang * Clear soft-irq in case we raised it last 339e46df235SSean Wang * time. 340e46df235SSean Wang */ 341e46df235SSean Wang writel(BIT(offset), reg - eint->regs->stat + 342e46df235SSean Wang eint->regs->soft_clr); 343e46df235SSean Wang 344e46df235SSean Wang start_level = 345e46df235SSean Wang eint->gpio_xlate->get_gpio_state(eint->pctl, 346e46df235SSean Wang index); 347e46df235SSean Wang } 348e46df235SSean Wang 349e46df235SSean Wang generic_handle_irq(virq); 350e46df235SSean Wang 351e46df235SSean Wang if (dual_edge) { 352e46df235SSean Wang curr_level = mtk_eint_flip_edge(eint, index); 353e46df235SSean Wang 354e46df235SSean Wang /* 355e46df235SSean Wang * If level changed, we might lost one edge 356e46df235SSean Wang * interrupt, raised it through soft-irq. 357e46df235SSean Wang */ 358e46df235SSean Wang if (start_level != curr_level) 359e46df235SSean Wang writel(BIT(offset), reg - 360e46df235SSean Wang eint->regs->stat + 361e46df235SSean Wang eint->regs->soft_set); 362e46df235SSean Wang } 363e46df235SSean Wang 364e46df235SSean Wang if (index < eint->hw->db_cnt) 365e46df235SSean Wang mtk_eint_debounce_process(eint, index); 366e46df235SSean Wang } 367e46df235SSean Wang } 368e46df235SSean Wang chained_irq_exit(chip, desc); 369e46df235SSean Wang } 370e46df235SSean Wang 371e46df235SSean Wang int mtk_eint_do_suspend(struct mtk_eint *eint) 372e46df235SSean Wang { 373e46df235SSean Wang mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask); 374e46df235SSean Wang mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); 375e46df235SSean Wang 376e46df235SSean Wang return 0; 377e46df235SSean Wang } 378e46df235SSean Wang 379e46df235SSean Wang int mtk_eint_do_resume(struct mtk_eint *eint) 380e46df235SSean Wang { 381e46df235SSean Wang mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); 382e46df235SSean Wang 383e46df235SSean Wang return 0; 384e46df235SSean Wang } 385e46df235SSean Wang 386e46df235SSean Wang int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, 387e46df235SSean Wang unsigned int debounce) 388e46df235SSean Wang { 389e46df235SSean Wang int virq, eint_offset; 390e46df235SSean Wang unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, 391e46df235SSean Wang dbnc; 392e46df235SSean Wang static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 393e46df235SSean Wang 64000, 128000, 256000}; 394e46df235SSean Wang struct irq_data *d; 395e46df235SSean Wang 396e46df235SSean Wang virq = irq_find_mapping(eint->domain, eint_num); 397e46df235SSean Wang eint_offset = (eint_num % 4) * 8; 398e46df235SSean Wang d = irq_get_irq_data(virq); 399e46df235SSean Wang 400e46df235SSean Wang set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set; 401e46df235SSean Wang clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr; 402e46df235SSean Wang 403e46df235SSean Wang if (!mtk_eint_can_en_debounce(eint, eint_num)) 404e46df235SSean Wang return -EINVAL; 405e46df235SSean Wang 406e46df235SSean Wang dbnc = ARRAY_SIZE(debounce_time); 407e46df235SSean Wang for (i = 0; i < ARRAY_SIZE(debounce_time); i++) { 408e46df235SSean Wang if (debounce <= debounce_time[i]) { 409e46df235SSean Wang dbnc = i; 410e46df235SSean Wang break; 411e46df235SSean Wang } 412e46df235SSean Wang } 413e46df235SSean Wang 414e46df235SSean Wang if (!mtk_eint_get_mask(eint, eint_num)) { 415e46df235SSean Wang mtk_eint_mask(d); 416e46df235SSean Wang unmask = 1; 417e46df235SSean Wang } else { 418e46df235SSean Wang unmask = 0; 419e46df235SSean Wang } 420e46df235SSean Wang 421e46df235SSean Wang clr_bit = 0xff << eint_offset; 422e46df235SSean Wang writel(clr_bit, eint->base + clr_offset); 423e46df235SSean Wang 424e46df235SSean Wang bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) << 425e46df235SSean Wang eint_offset; 426e46df235SSean Wang rst = MTK_EINT_DBNC_RST_BIT << eint_offset; 427e46df235SSean Wang writel(rst | bit, eint->base + set_offset); 428e46df235SSean Wang 429e46df235SSean Wang /* 430e46df235SSean Wang * Delay a while (more than 2T) to wait for hw debounce counter reset 431e46df235SSean Wang * work correctly. 432e46df235SSean Wang */ 433e46df235SSean Wang udelay(1); 434e46df235SSean Wang if (unmask == 1) 435e46df235SSean Wang mtk_eint_unmask(d); 436e46df235SSean Wang 437e46df235SSean Wang return 0; 438e46df235SSean Wang } 439e46df235SSean Wang 440e46df235SSean Wang int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) 441e46df235SSean Wang { 442e46df235SSean Wang int irq; 443e46df235SSean Wang 444e46df235SSean Wang irq = irq_find_mapping(eint->domain, eint_n); 445e46df235SSean Wang if (!irq) 446e46df235SSean Wang return -EINVAL; 447e46df235SSean Wang 448e46df235SSean Wang return irq; 449e46df235SSean Wang } 450e46df235SSean Wang 451e46df235SSean Wang int mtk_eint_do_init(struct mtk_eint *eint) 452e46df235SSean Wang { 453e46df235SSean Wang int i; 454e46df235SSean Wang 455e46df235SSean Wang /* If clients don't assign a specific regs, let's use generic one */ 456e46df235SSean Wang if (!eint->regs) 457e46df235SSean Wang eint->regs = &mtk_generic_eint_regs; 458e46df235SSean Wang 459e46df235SSean Wang eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports, 460e46df235SSean Wang sizeof(*eint->wake_mask), GFP_KERNEL); 461e46df235SSean Wang if (!eint->wake_mask) 462e46df235SSean Wang return -ENOMEM; 463e46df235SSean Wang 464e46df235SSean Wang eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports, 465e46df235SSean Wang sizeof(*eint->cur_mask), GFP_KERNEL); 466e46df235SSean Wang if (!eint->cur_mask) 467e46df235SSean Wang return -ENOMEM; 468e46df235SSean Wang 469e46df235SSean Wang eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num, 470e46df235SSean Wang sizeof(int), GFP_KERNEL); 471e46df235SSean Wang if (!eint->dual_edge) 472e46df235SSean Wang return -ENOMEM; 473e46df235SSean Wang 474e46df235SSean Wang eint->domain = irq_domain_add_linear(eint->dev->of_node, 475e46df235SSean Wang eint->hw->ap_num, 476e46df235SSean Wang &irq_domain_simple_ops, NULL); 477e46df235SSean Wang if (!eint->domain) 478e46df235SSean Wang return -ENOMEM; 479e46df235SSean Wang 480e46df235SSean Wang mtk_eint_hw_init(eint); 481e46df235SSean Wang for (i = 0; i < eint->hw->ap_num; i++) { 482e46df235SSean Wang int virq = irq_create_mapping(eint->domain, i); 483e46df235SSean Wang 484e46df235SSean Wang irq_set_chip_and_handler(virq, &mtk_eint_irq_chip, 485e46df235SSean Wang handle_level_irq); 486e46df235SSean Wang irq_set_chip_data(virq, eint); 487e46df235SSean Wang } 488e46df235SSean Wang 489e46df235SSean Wang irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, 490e46df235SSean Wang eint); 491e46df235SSean Wang 492e46df235SSean Wang return 0; 493e46df235SSean Wang } 494