1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Tiger Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-intel.h" 17 18 #define TGL_PAD_OWN 0x020 19 #define TGL_PADCFGLOCK 0x080 20 #define TGL_HOSTSW_OWN 0x0b0 21 #define TGL_GPI_IS 0x100 22 #define TGL_GPI_IE 0x120 23 24 #define TGL_GPP(r, s, e) \ 25 { \ 26 .reg_num = (r), \ 27 .base = (s), \ 28 .size = ((e) - (s) + 1), \ 29 } 30 31 #define TGL_COMMUNITY(s, e, g) \ 32 { \ 33 .padown_offset = TGL_PAD_OWN, \ 34 .padcfglock_offset = TGL_PADCFGLOCK, \ 35 .hostown_offset = TGL_HOSTSW_OWN, \ 36 .is_offset = TGL_GPI_IS, \ 37 .ie_offset = TGL_GPI_IE, \ 38 .pin_base = (s), \ 39 .npins = ((e) - (s) + 1), \ 40 .gpps = (g), \ 41 .ngpps = ARRAY_SIZE(g), \ 42 } 43 44 /* Tiger Lake-LP */ 45 static const struct pinctrl_pin_desc tgllp_community0_pins[] = { 46 /* GPP_B */ 47 PINCTRL_PIN(0, "CORE_VID_0"), 48 PINCTRL_PIN(1, "CORE_VID_1"), 49 PINCTRL_PIN(2, "VRALERTB"), 50 PINCTRL_PIN(3, "CPU_GP_2"), 51 PINCTRL_PIN(4, "CPU_GP_3"), 52 PINCTRL_PIN(5, "ISH_I2C0_SDA"), 53 PINCTRL_PIN(6, "ISH_I2C0_SCL"), 54 PINCTRL_PIN(7, "ISH_I2C1_SDA"), 55 PINCTRL_PIN(8, "ISH_I2C1_SCL"), 56 PINCTRL_PIN(9, "I2C5_SDA"), 57 PINCTRL_PIN(10, "I2C5_SCL"), 58 PINCTRL_PIN(11, "PMCALERTB"), 59 PINCTRL_PIN(12, "SLP_S0B"), 60 PINCTRL_PIN(13, "PLTRSTB"), 61 PINCTRL_PIN(14, "SPKR"), 62 PINCTRL_PIN(15, "GSPI0_CS0B"), 63 PINCTRL_PIN(16, "GSPI0_CLK"), 64 PINCTRL_PIN(17, "GSPI0_MISO"), 65 PINCTRL_PIN(18, "GSPI0_MOSI"), 66 PINCTRL_PIN(19, "GSPI1_CS0B"), 67 PINCTRL_PIN(20, "GSPI1_CLK"), 68 PINCTRL_PIN(21, "GSPI1_MISO"), 69 PINCTRL_PIN(22, "GSPI1_MOSI"), 70 PINCTRL_PIN(23, "SML1ALERTB"), 71 PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), 72 PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), 73 /* GPP_T */ 74 PINCTRL_PIN(26, "I2C6_SDA"), 75 PINCTRL_PIN(27, "I2C6_SCL"), 76 PINCTRL_PIN(28, "I2C7_SDA"), 77 PINCTRL_PIN(29, "I2C7_SCL"), 78 PINCTRL_PIN(30, "UART4_RXD"), 79 PINCTRL_PIN(31, "UART4_TXD"), 80 PINCTRL_PIN(32, "UART4_RTSB"), 81 PINCTRL_PIN(33, "UART4_CTSB"), 82 PINCTRL_PIN(34, "UART5_RXD"), 83 PINCTRL_PIN(35, "UART5_TXD"), 84 PINCTRL_PIN(36, "UART5_RTSB"), 85 PINCTRL_PIN(37, "UART5_CTSB"), 86 PINCTRL_PIN(38, "UART6_RXD"), 87 PINCTRL_PIN(39, "UART6_TXD"), 88 PINCTRL_PIN(40, "UART6_RTSB"), 89 PINCTRL_PIN(41, "UART6_CTSB"), 90 /* GPP_A */ 91 PINCTRL_PIN(42, "ESPI_IO_0"), 92 PINCTRL_PIN(43, "ESPI_IO_1"), 93 PINCTRL_PIN(44, "ESPI_IO_2"), 94 PINCTRL_PIN(45, "ESPI_IO_3"), 95 PINCTRL_PIN(46, "ESPI_CSB"), 96 PINCTRL_PIN(47, "ESPI_CLK"), 97 PINCTRL_PIN(48, "ESPI_RESETB"), 98 PINCTRL_PIN(49, "I2S2_SCLK"), 99 PINCTRL_PIN(50, "I2S2_SFRM"), 100 PINCTRL_PIN(51, "I2S2_TXD"), 101 PINCTRL_PIN(52, "I2S2_RXD"), 102 PINCTRL_PIN(53, "PMC_I2C_SDA"), 103 PINCTRL_PIN(54, "SATAXPCIE_1"), 104 PINCTRL_PIN(55, "PMC_I2C_SCL"), 105 PINCTRL_PIN(56, "USB2_OCB_1"), 106 PINCTRL_PIN(57, "USB2_OCB_2"), 107 PINCTRL_PIN(58, "USB2_OCB_3"), 108 PINCTRL_PIN(59, "DDSP_HPD_C"), 109 PINCTRL_PIN(60, "DDSP_HPD_B"), 110 PINCTRL_PIN(61, "DDSP_HPD_1"), 111 PINCTRL_PIN(62, "DDSP_HPD_2"), 112 PINCTRL_PIN(63, "GPPC_A_21"), 113 PINCTRL_PIN(64, "GPPC_A_22"), 114 PINCTRL_PIN(65, "I2S1_SCLK"), 115 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), 116 }; 117 118 static const struct intel_padgroup tgllp_community0_gpps[] = { 119 TGL_GPP(0, 0, 25), /* GPP_B */ 120 TGL_GPP(1, 26, 41), /* GPP_T */ 121 TGL_GPP(2, 42, 66), /* GPP_A */ 122 }; 123 124 static const struct intel_community tgllp_community0[] = { 125 TGL_COMMUNITY(0, 66, tgllp_community0_gpps), 126 }; 127 128 static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = { 129 .uid = "0", 130 .pins = tgllp_community0_pins, 131 .npins = ARRAY_SIZE(tgllp_community0_pins), 132 .communities = tgllp_community0, 133 .ncommunities = ARRAY_SIZE(tgllp_community0), 134 }; 135 136 static const struct pinctrl_pin_desc tgllp_community1_pins[] = { 137 /* GPP_S */ 138 PINCTRL_PIN(0, "SNDW0_CLK"), 139 PINCTRL_PIN(1, "SNDW0_DATA"), 140 PINCTRL_PIN(2, "SNDW1_CLK"), 141 PINCTRL_PIN(3, "SNDW1_DATA"), 142 PINCTRL_PIN(4, "SNDW2_CLK"), 143 PINCTRL_PIN(5, "SNDW2_DATA"), 144 PINCTRL_PIN(6, "SNDW3_CLK"), 145 PINCTRL_PIN(7, "SNDW3_DATA"), 146 /* GPP_H */ 147 PINCTRL_PIN(8, "GPPC_H_0"), 148 PINCTRL_PIN(9, "GPPC_H_1"), 149 PINCTRL_PIN(10, "GPPC_H_2"), 150 PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"), 151 PINCTRL_PIN(12, "I2C2_SDA"), 152 PINCTRL_PIN(13, "I2C2_SCL"), 153 PINCTRL_PIN(14, "I2C3_SDA"), 154 PINCTRL_PIN(15, "I2C3_SCL"), 155 PINCTRL_PIN(16, "I2C4_SDA"), 156 PINCTRL_PIN(17, "I2C4_SCL"), 157 PINCTRL_PIN(18, "SRCCLKREQB_4"), 158 PINCTRL_PIN(19, "SRCCLKREQB_5"), 159 PINCTRL_PIN(20, "M2_SKT2_CFG_0"), 160 PINCTRL_PIN(21, "M2_SKT2_CFG_1"), 161 PINCTRL_PIN(22, "M2_SKT2_CFG_2"), 162 PINCTRL_PIN(23, "M2_SKT2_CFG_3"), 163 PINCTRL_PIN(24, "DDPB_CTRLCLK"), 164 PINCTRL_PIN(25, "DDPB_CTRLDATA"), 165 PINCTRL_PIN(26, "CPU_C10_GATEB"), 166 PINCTRL_PIN(27, "TIME_SYNC_0"), 167 PINCTRL_PIN(28, "IMGCLKOUT_1"), 168 PINCTRL_PIN(29, "IMGCLKOUT_2"), 169 PINCTRL_PIN(30, "IMGCLKOUT_3"), 170 PINCTRL_PIN(31, "IMGCLKOUT_4"), 171 /* GPP_D */ 172 PINCTRL_PIN(32, "ISH_GP_0"), 173 PINCTRL_PIN(33, "ISH_GP_1"), 174 PINCTRL_PIN(34, "ISH_GP_2"), 175 PINCTRL_PIN(35, "ISH_GP_3"), 176 PINCTRL_PIN(36, "IMGCLKOUT_0"), 177 PINCTRL_PIN(37, "SRCCLKREQB_0"), 178 PINCTRL_PIN(38, "SRCCLKREQB_1"), 179 PINCTRL_PIN(39, "SRCCLKREQB_2"), 180 PINCTRL_PIN(40, "SRCCLKREQB_3"), 181 PINCTRL_PIN(41, "ISH_SPI_CSB"), 182 PINCTRL_PIN(42, "ISH_SPI_CLK"), 183 PINCTRL_PIN(43, "ISH_SPI_MISO"), 184 PINCTRL_PIN(44, "ISH_SPI_MOSI"), 185 PINCTRL_PIN(45, "ISH_UART0_RXD"), 186 PINCTRL_PIN(46, "ISH_UART0_TXD"), 187 PINCTRL_PIN(47, "ISH_UART0_RTSB"), 188 PINCTRL_PIN(48, "ISH_UART0_CTSB"), 189 PINCTRL_PIN(49, "ISH_GP_4"), 190 PINCTRL_PIN(50, "ISH_GP_5"), 191 PINCTRL_PIN(51, "I2S_MCLK1_OUT"), 192 PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"), 193 /* GPP_U */ 194 PINCTRL_PIN(53, "UART3_RXD"), 195 PINCTRL_PIN(54, "UART3_TXD"), 196 PINCTRL_PIN(55, "UART3_RTSB"), 197 PINCTRL_PIN(56, "UART3_CTSB"), 198 PINCTRL_PIN(57, "GSPI3_CS0B"), 199 PINCTRL_PIN(58, "GSPI3_CLK"), 200 PINCTRL_PIN(59, "GSPI3_MISO"), 201 PINCTRL_PIN(60, "GSPI3_MOSI"), 202 PINCTRL_PIN(61, "GSPI4_CS0B"), 203 PINCTRL_PIN(62, "GSPI4_CLK"), 204 PINCTRL_PIN(63, "GSPI4_MISO"), 205 PINCTRL_PIN(64, "GSPI4_MOSI"), 206 PINCTRL_PIN(65, "GSPI5_CS0B"), 207 PINCTRL_PIN(66, "GSPI5_CLK"), 208 PINCTRL_PIN(67, "GSPI5_MISO"), 209 PINCTRL_PIN(68, "GSPI5_MOSI"), 210 PINCTRL_PIN(69, "GSPI6_CS0B"), 211 PINCTRL_PIN(70, "GSPI6_CLK"), 212 PINCTRL_PIN(71, "GSPI6_MISO"), 213 PINCTRL_PIN(72, "GSPI6_MOSI"), 214 PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"), 215 PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"), 216 PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"), 217 PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"), 218 /* vGPIO */ 219 PINCTRL_PIN(77, "CNV_BTEN"), 220 PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"), 221 PINCTRL_PIN(79, "CNV_BT_IF_SELECT"), 222 PINCTRL_PIN(80, "vCNV_BT_UART_TXD"), 223 PINCTRL_PIN(81, "vCNV_BT_UART_RXD"), 224 PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"), 225 PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"), 226 PINCTRL_PIN(84, "vCNV_MFUART1_TXD"), 227 PINCTRL_PIN(85, "vCNV_MFUART1_RXD"), 228 PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"), 229 PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"), 230 PINCTRL_PIN(88, "vUART0_TXD"), 231 PINCTRL_PIN(89, "vUART0_RXD"), 232 PINCTRL_PIN(90, "vUART0_CTS_B"), 233 PINCTRL_PIN(91, "vUART0_RTS_B"), 234 PINCTRL_PIN(92, "vISH_UART0_TXD"), 235 PINCTRL_PIN(93, "vISH_UART0_RXD"), 236 PINCTRL_PIN(94, "vISH_UART0_CTS_B"), 237 PINCTRL_PIN(95, "vISH_UART0_RTS_B"), 238 PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"), 239 PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"), 240 PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"), 241 PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"), 242 PINCTRL_PIN(100, "vI2S2_SCLK"), 243 PINCTRL_PIN(101, "vI2S2_SFRM"), 244 PINCTRL_PIN(102, "vI2S2_TXD"), 245 PINCTRL_PIN(103, "vI2S2_RXD"), 246 }; 247 248 static const struct intel_padgroup tgllp_community1_gpps[] = { 249 TGL_GPP(0, 0, 7), /* GPP_S */ 250 TGL_GPP(1, 8, 31), /* GPP_H */ 251 TGL_GPP(2, 32, 52), /* GPP_D */ 252 TGL_GPP(3, 53, 76), /* GPP_U */ 253 TGL_GPP(4, 77, 103), /* vGPIO */ 254 }; 255 256 static const struct intel_community tgllp_community1[] = { 257 TGL_COMMUNITY(0, 103, tgllp_community1_gpps), 258 }; 259 260 static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = { 261 .uid = "1", 262 .pins = tgllp_community1_pins, 263 .npins = ARRAY_SIZE(tgllp_community1_pins), 264 .communities = tgllp_community1, 265 .ncommunities = ARRAY_SIZE(tgllp_community1), 266 }; 267 268 static const struct pinctrl_pin_desc tgllp_community4_pins[] = { 269 /* GPP_C */ 270 PINCTRL_PIN(0, "SMBCLK"), 271 PINCTRL_PIN(1, "SMBDATA"), 272 PINCTRL_PIN(2, "SMBALERTB"), 273 PINCTRL_PIN(3, "SML0CLK"), 274 PINCTRL_PIN(4, "SML0DATA"), 275 PINCTRL_PIN(5, "SML0ALERTB"), 276 PINCTRL_PIN(6, "SML1CLK"), 277 PINCTRL_PIN(7, "SML1DATA"), 278 PINCTRL_PIN(8, "UART0_RXD"), 279 PINCTRL_PIN(9, "UART0_TXD"), 280 PINCTRL_PIN(10, "UART0_RTSB"), 281 PINCTRL_PIN(11, "UART0_CTSB"), 282 PINCTRL_PIN(12, "UART1_RXD"), 283 PINCTRL_PIN(13, "UART1_TXD"), 284 PINCTRL_PIN(14, "UART1_RTSB"), 285 PINCTRL_PIN(15, "UART1_CTSB"), 286 PINCTRL_PIN(16, "I2C0_SDA"), 287 PINCTRL_PIN(17, "I2C0_SCL"), 288 PINCTRL_PIN(18, "I2C1_SDA"), 289 PINCTRL_PIN(19, "I2C1_SCL"), 290 PINCTRL_PIN(20, "UART2_RXD"), 291 PINCTRL_PIN(21, "UART2_TXD"), 292 PINCTRL_PIN(22, "UART2_RTSB"), 293 PINCTRL_PIN(23, "UART2_CTSB"), 294 /* GPP_F */ 295 PINCTRL_PIN(24, "CNV_BRI_DT"), 296 PINCTRL_PIN(25, "CNV_BRI_RSP"), 297 PINCTRL_PIN(26, "CNV_RGI_DT"), 298 PINCTRL_PIN(27, "CNV_RGI_RSP"), 299 PINCTRL_PIN(28, "CNV_RF_RESET_B"), 300 PINCTRL_PIN(29, "GPPC_F_5"), 301 PINCTRL_PIN(30, "CNV_PA_BLANKING"), 302 PINCTRL_PIN(31, "GPPC_F_7"), 303 PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), 304 PINCTRL_PIN(33, "BOOTMPC"), 305 PINCTRL_PIN(34, "GPPC_F_10"), 306 PINCTRL_PIN(35, "GPPC_F_11"), 307 PINCTRL_PIN(36, "GSXDOUT"), 308 PINCTRL_PIN(37, "GSXSLOAD"), 309 PINCTRL_PIN(38, "GSXDIN"), 310 PINCTRL_PIN(39, "GSXSRESETB"), 311 PINCTRL_PIN(40, "GSXCLK"), 312 PINCTRL_PIN(41, "GMII_MDC"), 313 PINCTRL_PIN(42, "GMII_MDIO"), 314 PINCTRL_PIN(43, "SRCCLKREQB_6"), 315 PINCTRL_PIN(44, "EXT_PWR_GATEB"), 316 PINCTRL_PIN(45, "EXT_PWR_GATE2B"), 317 PINCTRL_PIN(46, "VNN_CTRL"), 318 PINCTRL_PIN(47, "V1P05_CTRL"), 319 PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), 320 /* HVCMOS */ 321 PINCTRL_PIN(49, "L_BKLTEN"), 322 PINCTRL_PIN(50, "L_BKLTCTL"), 323 PINCTRL_PIN(51, "L_VDDEN"), 324 PINCTRL_PIN(52, "SYS_PWROK"), 325 PINCTRL_PIN(53, "SYS_RESETB"), 326 PINCTRL_PIN(54, "MLK_RSTB"), 327 /* GPP_E */ 328 PINCTRL_PIN(55, "SATAXPCIE_0"), 329 PINCTRL_PIN(56, "SPI1_IO_2"), 330 PINCTRL_PIN(57, "SPI1_IO_3"), 331 PINCTRL_PIN(58, "CPU_GP_0"), 332 PINCTRL_PIN(59, "SATA_DEVSLP_0"), 333 PINCTRL_PIN(60, "SATA_DEVSLP_1"), 334 PINCTRL_PIN(61, "GPPC_E_6"), 335 PINCTRL_PIN(62, "CPU_GP_1"), 336 PINCTRL_PIN(63, "SPI1_CS1B"), 337 PINCTRL_PIN(64, "USB2_OCB_0"), 338 PINCTRL_PIN(65, "SPI1_CSB"), 339 PINCTRL_PIN(66, "SPI1_CLK"), 340 PINCTRL_PIN(67, "SPI1_MISO_IO_1"), 341 PINCTRL_PIN(68, "SPI1_MOSI_IO_0"), 342 PINCTRL_PIN(69, "DDSP_HPD_A"), 343 PINCTRL_PIN(70, "ISH_GP_6"), 344 PINCTRL_PIN(71, "ISH_GP_7"), 345 PINCTRL_PIN(72, "GPPC_E_17"), 346 PINCTRL_PIN(73, "DDP1_CTRLCLK"), 347 PINCTRL_PIN(74, "DDP1_CTRLDATA"), 348 PINCTRL_PIN(75, "DDP2_CTRLCLK"), 349 PINCTRL_PIN(76, "DDP2_CTRLDATA"), 350 PINCTRL_PIN(77, "DDPA_CTRLCLK"), 351 PINCTRL_PIN(78, "DDPA_CTRLDATA"), 352 PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), 353 /* JTAG */ 354 PINCTRL_PIN(80, "JTAG_TDO"), 355 PINCTRL_PIN(81, "JTAGX"), 356 PINCTRL_PIN(82, "PRDYB"), 357 PINCTRL_PIN(83, "PREQB"), 358 PINCTRL_PIN(84, "CPU_TRSTB"), 359 PINCTRL_PIN(85, "JTAG_TDI"), 360 PINCTRL_PIN(86, "JTAG_TMS"), 361 PINCTRL_PIN(87, "JTAG_TCK"), 362 PINCTRL_PIN(88, "DBG_PMODE"), 363 }; 364 365 static const struct intel_padgroup tgllp_community4_gpps[] = { 366 TGL_GPP(0, 0, 23), /* GPP_C */ 367 TGL_GPP(1, 24, 48), /* GPP_F */ 368 TGL_GPP(2, 49, 54), /* HVCMOS */ 369 TGL_GPP(3, 55, 79), /* GPP_E */ 370 TGL_GPP(4, 80, 88), /* JTAG */ 371 }; 372 373 static const struct intel_community tgllp_community4[] = { 374 TGL_COMMUNITY(0, 88, tgllp_community4_gpps), 375 }; 376 377 static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = { 378 .uid = "4", 379 .pins = tgllp_community4_pins, 380 .npins = ARRAY_SIZE(tgllp_community4_pins), 381 .communities = tgllp_community4, 382 .ncommunities = ARRAY_SIZE(tgllp_community4), 383 }; 384 385 static const struct pinctrl_pin_desc tgllp_community5_pins[] = { 386 /* GPP_R */ 387 PINCTRL_PIN(0, "HDA_BCLK"), 388 PINCTRL_PIN(1, "HDA_SYNC"), 389 PINCTRL_PIN(2, "HDA_SDO"), 390 PINCTRL_PIN(3, "HDA_SDI_0"), 391 PINCTRL_PIN(4, "HDA_RSTB"), 392 PINCTRL_PIN(5, "HDA_SDI_1"), 393 PINCTRL_PIN(6, "GPP_R_6"), 394 PINCTRL_PIN(7, "GPP_R_7"), 395 /* SPI */ 396 PINCTRL_PIN(8, "SPI0_IO_2"), 397 PINCTRL_PIN(9, "SPI0_IO_3"), 398 PINCTRL_PIN(10, "SPI0_MOSI_IO_0"), 399 PINCTRL_PIN(11, "SPI0_MISO_IO_1"), 400 PINCTRL_PIN(12, "SPI0_TPM_CSB"), 401 PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"), 402 PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"), 403 PINCTRL_PIN(15, "SPI0_CLK"), 404 PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"), 405 }; 406 407 static const struct intel_padgroup tgllp_community5_gpps[] = { 408 TGL_GPP(0, 0, 7), /* GPP_R */ 409 TGL_GPP(1, 8, 16), /* SPI */ 410 }; 411 412 static const struct intel_community tgllp_community5[] = { 413 TGL_COMMUNITY(0, 16, tgllp_community5_gpps), 414 }; 415 416 static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = { 417 .uid = "5", 418 .pins = tgllp_community5_pins, 419 .npins = ARRAY_SIZE(tgllp_community5_pins), 420 .communities = tgllp_community5, 421 .ncommunities = ARRAY_SIZE(tgllp_community5), 422 }; 423 424 static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = { 425 &tgllp_community0_soc_data, 426 &tgllp_community1_soc_data, 427 &tgllp_community4_soc_data, 428 &tgllp_community5_soc_data, 429 NULL 430 }; 431 432 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { 433 { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array }, 434 { } 435 }; 436 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); 437 438 static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops); 439 440 static struct platform_driver tgl_pinctrl_driver = { 441 .probe = intel_pinctrl_probe_by_uid, 442 .driver = { 443 .name = "tigerlake-pinctrl", 444 .acpi_match_table = tgl_pinctrl_acpi_match, 445 .pm = &tgl_pinctrl_pm_ops, 446 }, 447 }; 448 449 module_platform_driver(tgl_pinctrl_driver); 450 451 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 452 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 453 MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); 454 MODULE_LICENSE("GPL v2"); 455