1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Sunrisepoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-intel.h" 17 18 #define SPT_H_PAD_OWN 0x020 19 #define SPT_H_PADCFGLOCK 0x090 20 #define SPT_H_HOSTSW_OWN 0x0d0 21 #define SPT_H_GPI_IS 0x100 22 #define SPT_H_GPI_IE 0x120 23 24 #define SPT_LP_PAD_OWN 0x020 25 #define SPT_LP_PADCFGLOCK 0x0a0 26 #define SPT_LP_HOSTSW_OWN 0x0d0 27 #define SPT_LP_GPI_IS 0x100 28 #define SPT_LP_GPI_IE 0x120 29 30 #define SPT_H_GPP(r, s, e, g) \ 31 { \ 32 .reg_num = (r), \ 33 .base = (s), \ 34 .size = ((e) - (s) + 1), \ 35 .gpio_base = (g), \ 36 } 37 38 #define SPT_H_COMMUNITY(b, s, e, g) \ 39 INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H) 40 41 #define SPT_LP_COMMUNITY(b, s, e) \ 42 INTEL_COMMUNITY_SIZE(b, s, e, 24, 4, SPT_LP) 43 44 /* Sunrisepoint-LP */ 45 static const struct pinctrl_pin_desc sptlp_pins[] = { 46 /* GPP_A */ 47 PINCTRL_PIN(0, "RCINB"), 48 PINCTRL_PIN(1, "LAD_0"), 49 PINCTRL_PIN(2, "LAD_1"), 50 PINCTRL_PIN(3, "LAD_2"), 51 PINCTRL_PIN(4, "LAD_3"), 52 PINCTRL_PIN(5, "LFRAMEB"), 53 PINCTRL_PIN(6, "SERIQ"), 54 PINCTRL_PIN(7, "PIRQAB"), 55 PINCTRL_PIN(8, "CLKRUNB"), 56 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 57 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 58 PINCTRL_PIN(11, "PMEB"), 59 PINCTRL_PIN(12, "BM_BUSYB"), 60 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 61 PINCTRL_PIN(14, "SUS_STATB"), 62 PINCTRL_PIN(15, "SUSACKB"), 63 PINCTRL_PIN(16, "SD_1P8_SEL"), 64 PINCTRL_PIN(17, "SD_PWR_EN_B"), 65 PINCTRL_PIN(18, "ISH_GP_0"), 66 PINCTRL_PIN(19, "ISH_GP_1"), 67 PINCTRL_PIN(20, "ISH_GP_2"), 68 PINCTRL_PIN(21, "ISH_GP_3"), 69 PINCTRL_PIN(22, "ISH_GP_4"), 70 PINCTRL_PIN(23, "ISH_GP_5"), 71 /* GPP_B */ 72 PINCTRL_PIN(24, "CORE_VID_0"), 73 PINCTRL_PIN(25, "CORE_VID_1"), 74 PINCTRL_PIN(26, "VRALERTB"), 75 PINCTRL_PIN(27, "CPU_GP_2"), 76 PINCTRL_PIN(28, "CPU_GP_3"), 77 PINCTRL_PIN(29, "SRCCLKREQB_0"), 78 PINCTRL_PIN(30, "SRCCLKREQB_1"), 79 PINCTRL_PIN(31, "SRCCLKREQB_2"), 80 PINCTRL_PIN(32, "SRCCLKREQB_3"), 81 PINCTRL_PIN(33, "SRCCLKREQB_4"), 82 PINCTRL_PIN(34, "SRCCLKREQB_5"), 83 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 84 PINCTRL_PIN(36, "SLP_S0B"), 85 PINCTRL_PIN(37, "PLTRSTB"), 86 PINCTRL_PIN(38, "SPKR"), 87 PINCTRL_PIN(39, "GSPI0_CSB"), 88 PINCTRL_PIN(40, "GSPI0_CLK"), 89 PINCTRL_PIN(41, "GSPI0_MISO"), 90 PINCTRL_PIN(42, "GSPI0_MOSI"), 91 PINCTRL_PIN(43, "GSPI1_CSB"), 92 PINCTRL_PIN(44, "GSPI1_CLK"), 93 PINCTRL_PIN(45, "GSPI1_MISO"), 94 PINCTRL_PIN(46, "GSPI1_MOSI"), 95 PINCTRL_PIN(47, "SML1ALERTB"), 96 /* GPP_C */ 97 PINCTRL_PIN(48, "SMBCLK"), 98 PINCTRL_PIN(49, "SMBDATA"), 99 PINCTRL_PIN(50, "SMBALERTB"), 100 PINCTRL_PIN(51, "SML0CLK"), 101 PINCTRL_PIN(52, "SML0DATA"), 102 PINCTRL_PIN(53, "SML0ALERTB"), 103 PINCTRL_PIN(54, "SML1CLK"), 104 PINCTRL_PIN(55, "SML1DATA"), 105 PINCTRL_PIN(56, "UART0_RXD"), 106 PINCTRL_PIN(57, "UART0_TXD"), 107 PINCTRL_PIN(58, "UART0_RTSB"), 108 PINCTRL_PIN(59, "UART0_CTSB"), 109 PINCTRL_PIN(60, "UART1_RXD"), 110 PINCTRL_PIN(61, "UART1_TXD"), 111 PINCTRL_PIN(62, "UART1_RTSB"), 112 PINCTRL_PIN(63, "UART1_CTSB"), 113 PINCTRL_PIN(64, "I2C0_SDA"), 114 PINCTRL_PIN(65, "I2C0_SCL"), 115 PINCTRL_PIN(66, "I2C1_SDA"), 116 PINCTRL_PIN(67, "I2C1_SCL"), 117 PINCTRL_PIN(68, "UART2_RXD"), 118 PINCTRL_PIN(69, "UART2_TXD"), 119 PINCTRL_PIN(70, "UART2_RTSB"), 120 PINCTRL_PIN(71, "UART2_CTSB"), 121 /* GPP_D */ 122 PINCTRL_PIN(72, "SPI1_CSB"), 123 PINCTRL_PIN(73, "SPI1_CLK"), 124 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 125 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 126 PINCTRL_PIN(76, "FLASHTRIG"), 127 PINCTRL_PIN(77, "ISH_I2C0_SDA"), 128 PINCTRL_PIN(78, "ISH_I2C0_SCL"), 129 PINCTRL_PIN(79, "ISH_I2C1_SDA"), 130 PINCTRL_PIN(80, "ISH_I2C1_SCL"), 131 PINCTRL_PIN(81, "ISH_SPI_CSB"), 132 PINCTRL_PIN(82, "ISH_SPI_CLK"), 133 PINCTRL_PIN(83, "ISH_SPI_MISO"), 134 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 135 PINCTRL_PIN(85, "ISH_UART0_RXD"), 136 PINCTRL_PIN(86, "ISH_UART0_TXD"), 137 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 138 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 139 PINCTRL_PIN(89, "DMIC_CLK_1"), 140 PINCTRL_PIN(90, "DMIC_DATA_1"), 141 PINCTRL_PIN(91, "DMIC_CLK_0"), 142 PINCTRL_PIN(92, "DMIC_DATA_0"), 143 PINCTRL_PIN(93, "SPI1_IO_2"), 144 PINCTRL_PIN(94, "SPI1_IO_3"), 145 PINCTRL_PIN(95, "SSP_MCLK"), 146 /* GPP_E */ 147 PINCTRL_PIN(96, "SATAXPCIE_0"), 148 PINCTRL_PIN(97, "SATAXPCIE_1"), 149 PINCTRL_PIN(98, "SATAXPCIE_2"), 150 PINCTRL_PIN(99, "CPU_GP_0"), 151 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 152 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 153 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 154 PINCTRL_PIN(103, "CPU_GP_1"), 155 PINCTRL_PIN(104, "SATA_LEDB"), 156 PINCTRL_PIN(105, "USB2_OCB_0"), 157 PINCTRL_PIN(106, "USB2_OCB_1"), 158 PINCTRL_PIN(107, "USB2_OCB_2"), 159 PINCTRL_PIN(108, "USB2_OCB_3"), 160 PINCTRL_PIN(109, "DDSP_HPD_0"), 161 PINCTRL_PIN(110, "DDSP_HPD_1"), 162 PINCTRL_PIN(111, "DDSP_HPD_2"), 163 PINCTRL_PIN(112, "DDSP_HPD_3"), 164 PINCTRL_PIN(113, "EDP_HPD"), 165 PINCTRL_PIN(114, "DDPB_CTRLCLK"), 166 PINCTRL_PIN(115, "DDPB_CTRLDATA"), 167 PINCTRL_PIN(116, "DDPC_CTRLCLK"), 168 PINCTRL_PIN(117, "DDPC_CTRLDATA"), 169 PINCTRL_PIN(118, "DDPD_CTRLCLK"), 170 PINCTRL_PIN(119, "DDPD_CTRLDATA"), 171 /* GPP_F */ 172 PINCTRL_PIN(120, "SSP2_SCLK"), 173 PINCTRL_PIN(121, "SSP2_SFRM"), 174 PINCTRL_PIN(122, "SSP2_TXD"), 175 PINCTRL_PIN(123, "SSP2_RXD"), 176 PINCTRL_PIN(124, "I2C2_SDA"), 177 PINCTRL_PIN(125, "I2C2_SCL"), 178 PINCTRL_PIN(126, "I2C3_SDA"), 179 PINCTRL_PIN(127, "I2C3_SCL"), 180 PINCTRL_PIN(128, "I2C4_SDA"), 181 PINCTRL_PIN(129, "I2C4_SCL"), 182 PINCTRL_PIN(130, "I2C5_SDA"), 183 PINCTRL_PIN(131, "I2C5_SCL"), 184 PINCTRL_PIN(132, "EMMC_CMD"), 185 PINCTRL_PIN(133, "EMMC_DATA_0"), 186 PINCTRL_PIN(134, "EMMC_DATA_1"), 187 PINCTRL_PIN(135, "EMMC_DATA_2"), 188 PINCTRL_PIN(136, "EMMC_DATA_3"), 189 PINCTRL_PIN(137, "EMMC_DATA_4"), 190 PINCTRL_PIN(138, "EMMC_DATA_5"), 191 PINCTRL_PIN(139, "EMMC_DATA_6"), 192 PINCTRL_PIN(140, "EMMC_DATA_7"), 193 PINCTRL_PIN(141, "EMMC_RCLK"), 194 PINCTRL_PIN(142, "EMMC_CLK"), 195 PINCTRL_PIN(143, "GPP_F_23"), 196 /* GPP_G */ 197 PINCTRL_PIN(144, "SD_CMD"), 198 PINCTRL_PIN(145, "SD_DATA_0"), 199 PINCTRL_PIN(146, "SD_DATA_1"), 200 PINCTRL_PIN(147, "SD_DATA_2"), 201 PINCTRL_PIN(148, "SD_DATA_3"), 202 PINCTRL_PIN(149, "SD_CDB"), 203 PINCTRL_PIN(150, "SD_CLK"), 204 PINCTRL_PIN(151, "SD_WP"), 205 }; 206 207 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 }; 208 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 }; 209 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 }; 210 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 }; 211 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 }; 212 static const unsigned sptlp_i2c0_pins[] = { 64, 65 }; 213 static const unsigned sptlp_i2c1_pins[] = { 66, 67 }; 214 static const unsigned sptlp_i2c2_pins[] = { 124, 125 }; 215 static const unsigned sptlp_i2c3_pins[] = { 126, 127 }; 216 static const unsigned sptlp_i2c4_pins[] = { 128, 129 }; 217 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 }; 218 static const unsigned sptlp_i2c5_pins[] = { 130, 131 }; 219 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 }; 220 static const unsigned sptlp_emmc_pins[] = { 221 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 222 }; 223 static const unsigned sptlp_sd_pins[] = { 224 144, 145, 146, 147, 148, 149, 150, 151, 225 }; 226 227 static const struct intel_pingroup sptlp_groups[] = { 228 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1), 229 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1), 230 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1), 231 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1), 232 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1), 233 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1), 234 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1), 235 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1), 236 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1), 237 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1), 238 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3), 239 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1), 240 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1), 241 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1), 242 PIN_GROUP("sd_grp", sptlp_sd_pins, 1), 243 }; 244 245 static const char * const sptlp_spi0_groups[] = { "spi0_grp" }; 246 static const char * const sptlp_spi1_groups[] = { "spi0_grp" }; 247 static const char * const sptlp_uart0_groups[] = { "uart0_grp" }; 248 static const char * const sptlp_uart1_groups[] = { "uart1_grp" }; 249 static const char * const sptlp_uart2_groups[] = { "uart2_grp" }; 250 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" }; 251 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" }; 252 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" }; 253 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" }; 254 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" }; 255 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" }; 256 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" }; 257 static const char * const sptlp_emmc_groups[] = { "emmc_grp" }; 258 static const char * const sptlp_sd_groups[] = { "sd_grp" }; 259 260 static const struct intel_function sptlp_functions[] = { 261 FUNCTION("spi0", sptlp_spi0_groups), 262 FUNCTION("spi1", sptlp_spi1_groups), 263 FUNCTION("uart0", sptlp_uart0_groups), 264 FUNCTION("uart1", sptlp_uart1_groups), 265 FUNCTION("uart2", sptlp_uart2_groups), 266 FUNCTION("i2c0", sptlp_i2c0_groups), 267 FUNCTION("i2c1", sptlp_i2c1_groups), 268 FUNCTION("i2c2", sptlp_i2c2_groups), 269 FUNCTION("i2c3", sptlp_i2c3_groups), 270 FUNCTION("i2c4", sptlp_i2c4_groups), 271 FUNCTION("i2c5", sptlp_i2c5_groups), 272 FUNCTION("ssp2", sptlp_ssp2_groups), 273 FUNCTION("emmc", sptlp_emmc_groups), 274 FUNCTION("sd", sptlp_sd_groups), 275 }; 276 277 static const struct intel_community sptlp_communities[] = { 278 SPT_LP_COMMUNITY(0, 0, 47), 279 SPT_LP_COMMUNITY(1, 48, 119), 280 SPT_LP_COMMUNITY(2, 120, 151), 281 }; 282 283 static const struct intel_pinctrl_soc_data sptlp_soc_data = { 284 .pins = sptlp_pins, 285 .npins = ARRAY_SIZE(sptlp_pins), 286 .groups = sptlp_groups, 287 .ngroups = ARRAY_SIZE(sptlp_groups), 288 .functions = sptlp_functions, 289 .nfunctions = ARRAY_SIZE(sptlp_functions), 290 .communities = sptlp_communities, 291 .ncommunities = ARRAY_SIZE(sptlp_communities), 292 }; 293 294 /* Sunrisepoint-H */ 295 static const struct pinctrl_pin_desc spth_pins[] = { 296 /* GPP_A */ 297 PINCTRL_PIN(0, "RCINB"), 298 PINCTRL_PIN(1, "LAD_0"), 299 PINCTRL_PIN(2, "LAD_1"), 300 PINCTRL_PIN(3, "LAD_2"), 301 PINCTRL_PIN(4, "LAD_3"), 302 PINCTRL_PIN(5, "LFRAMEB"), 303 PINCTRL_PIN(6, "SERIQ"), 304 PINCTRL_PIN(7, "PIRQAB"), 305 PINCTRL_PIN(8, "CLKRUNB"), 306 PINCTRL_PIN(9, "CLKOUT_LPC_0"), 307 PINCTRL_PIN(10, "CLKOUT_LPC_1"), 308 PINCTRL_PIN(11, "PMEB"), 309 PINCTRL_PIN(12, "BM_BUSYB"), 310 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"), 311 PINCTRL_PIN(14, "SUS_STATB"), 312 PINCTRL_PIN(15, "SUSACKB"), 313 PINCTRL_PIN(16, "CLKOUT_48"), 314 PINCTRL_PIN(17, "ISH_GP_7"), 315 PINCTRL_PIN(18, "ISH_GP_0"), 316 PINCTRL_PIN(19, "ISH_GP_1"), 317 PINCTRL_PIN(20, "ISH_GP_2"), 318 PINCTRL_PIN(21, "ISH_GP_3"), 319 PINCTRL_PIN(22, "ISH_GP_4"), 320 PINCTRL_PIN(23, "ISH_GP_5"), 321 /* GPP_B */ 322 PINCTRL_PIN(24, "CORE_VID_0"), 323 PINCTRL_PIN(25, "CORE_VID_1"), 324 PINCTRL_PIN(26, "VRALERTB"), 325 PINCTRL_PIN(27, "CPU_GP_2"), 326 PINCTRL_PIN(28, "CPU_GP_3"), 327 PINCTRL_PIN(29, "SRCCLKREQB_0"), 328 PINCTRL_PIN(30, "SRCCLKREQB_1"), 329 PINCTRL_PIN(31, "SRCCLKREQB_2"), 330 PINCTRL_PIN(32, "SRCCLKREQB_3"), 331 PINCTRL_PIN(33, "SRCCLKREQB_4"), 332 PINCTRL_PIN(34, "SRCCLKREQB_5"), 333 PINCTRL_PIN(35, "EXT_PWR_GATEB"), 334 PINCTRL_PIN(36, "SLP_S0B"), 335 PINCTRL_PIN(37, "PLTRSTB"), 336 PINCTRL_PIN(38, "SPKR"), 337 PINCTRL_PIN(39, "GSPI0_CSB"), 338 PINCTRL_PIN(40, "GSPI0_CLK"), 339 PINCTRL_PIN(41, "GSPI0_MISO"), 340 PINCTRL_PIN(42, "GSPI0_MOSI"), 341 PINCTRL_PIN(43, "GSPI1_CSB"), 342 PINCTRL_PIN(44, "GSPI1_CLK"), 343 PINCTRL_PIN(45, "GSPI1_MISO"), 344 PINCTRL_PIN(46, "GSPI1_MOSI"), 345 PINCTRL_PIN(47, "SML1ALERTB"), 346 /* GPP_C */ 347 PINCTRL_PIN(48, "SMBCLK"), 348 PINCTRL_PIN(49, "SMBDATA"), 349 PINCTRL_PIN(50, "SMBALERTB"), 350 PINCTRL_PIN(51, "SML0CLK"), 351 PINCTRL_PIN(52, "SML0DATA"), 352 PINCTRL_PIN(53, "SML0ALERTB"), 353 PINCTRL_PIN(54, "SML1CLK"), 354 PINCTRL_PIN(55, "SML1DATA"), 355 PINCTRL_PIN(56, "UART0_RXD"), 356 PINCTRL_PIN(57, "UART0_TXD"), 357 PINCTRL_PIN(58, "UART0_RTSB"), 358 PINCTRL_PIN(59, "UART0_CTSB"), 359 PINCTRL_PIN(60, "UART1_RXD"), 360 PINCTRL_PIN(61, "UART1_TXD"), 361 PINCTRL_PIN(62, "UART1_RTSB"), 362 PINCTRL_PIN(63, "UART1_CTSB"), 363 PINCTRL_PIN(64, "I2C0_SDA"), 364 PINCTRL_PIN(65, "I2C0_SCL"), 365 PINCTRL_PIN(66, "I2C1_SDA"), 366 PINCTRL_PIN(67, "I2C1_SCL"), 367 PINCTRL_PIN(68, "UART2_RXD"), 368 PINCTRL_PIN(69, "UART2_TXD"), 369 PINCTRL_PIN(70, "UART2_RTSB"), 370 PINCTRL_PIN(71, "UART2_CTSB"), 371 /* GPP_D */ 372 PINCTRL_PIN(72, "SPI1_CSB"), 373 PINCTRL_PIN(73, "SPI1_CLK"), 374 PINCTRL_PIN(74, "SPI1_MISO_IO_1"), 375 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"), 376 PINCTRL_PIN(76, "ISH_I2C2_SDA"), 377 PINCTRL_PIN(77, "SSP0_SFRM"), 378 PINCTRL_PIN(78, "SSP0_TXD"), 379 PINCTRL_PIN(79, "SSP0_RXD"), 380 PINCTRL_PIN(80, "SSP0_SCLK"), 381 PINCTRL_PIN(81, "ISH_SPI_CSB"), 382 PINCTRL_PIN(82, "ISH_SPI_CLK"), 383 PINCTRL_PIN(83, "ISH_SPI_MISO"), 384 PINCTRL_PIN(84, "ISH_SPI_MOSI"), 385 PINCTRL_PIN(85, "ISH_UART0_RXD"), 386 PINCTRL_PIN(86, "ISH_UART0_TXD"), 387 PINCTRL_PIN(87, "ISH_UART0_RTSB"), 388 PINCTRL_PIN(88, "ISH_UART0_CTSB"), 389 PINCTRL_PIN(89, "DMIC_CLK_1"), 390 PINCTRL_PIN(90, "DMIC_DATA_1"), 391 PINCTRL_PIN(91, "DMIC_CLK_0"), 392 PINCTRL_PIN(92, "DMIC_DATA_0"), 393 PINCTRL_PIN(93, "SPI1_IO_2"), 394 PINCTRL_PIN(94, "SPI1_IO_3"), 395 PINCTRL_PIN(95, "ISH_I2C2_SCL"), 396 /* GPP_E */ 397 PINCTRL_PIN(96, "SATAXPCIE_0"), 398 PINCTRL_PIN(97, "SATAXPCIE_1"), 399 PINCTRL_PIN(98, "SATAXPCIE_2"), 400 PINCTRL_PIN(99, "CPU_GP_0"), 401 PINCTRL_PIN(100, "SATA_DEVSLP_0"), 402 PINCTRL_PIN(101, "SATA_DEVSLP_1"), 403 PINCTRL_PIN(102, "SATA_DEVSLP_2"), 404 PINCTRL_PIN(103, "CPU_GP_1"), 405 PINCTRL_PIN(104, "SATA_LEDB"), 406 PINCTRL_PIN(105, "USB2_OCB_0"), 407 PINCTRL_PIN(106, "USB2_OCB_1"), 408 PINCTRL_PIN(107, "USB2_OCB_2"), 409 PINCTRL_PIN(108, "USB2_OCB_3"), 410 /* GPP_F */ 411 PINCTRL_PIN(109, "SATAXPCIE_3"), 412 PINCTRL_PIN(110, "SATAXPCIE_4"), 413 PINCTRL_PIN(111, "SATAXPCIE_5"), 414 PINCTRL_PIN(112, "SATAXPCIE_6"), 415 PINCTRL_PIN(113, "SATAXPCIE_7"), 416 PINCTRL_PIN(114, "SATA_DEVSLP_3"), 417 PINCTRL_PIN(115, "SATA_DEVSLP_4"), 418 PINCTRL_PIN(116, "SATA_DEVSLP_5"), 419 PINCTRL_PIN(117, "SATA_DEVSLP_6"), 420 PINCTRL_PIN(118, "SATA_DEVSLP_7"), 421 PINCTRL_PIN(119, "SATA_SCLOCK"), 422 PINCTRL_PIN(120, "SATA_SLOAD"), 423 PINCTRL_PIN(121, "SATA_SDATAOUT1"), 424 PINCTRL_PIN(122, "SATA_SDATAOUT0"), 425 PINCTRL_PIN(123, "GPP_F_14"), 426 PINCTRL_PIN(124, "USB_OCB_4"), 427 PINCTRL_PIN(125, "USB_OCB_5"), 428 PINCTRL_PIN(126, "USB_OCB_6"), 429 PINCTRL_PIN(127, "USB_OCB_7"), 430 PINCTRL_PIN(128, "L_VDDEN"), 431 PINCTRL_PIN(129, "L_BKLTEN"), 432 PINCTRL_PIN(130, "L_BKLTCTL"), 433 PINCTRL_PIN(131, "GPP_F_22"), 434 PINCTRL_PIN(132, "GPP_F_23"), 435 /* GPP_G */ 436 PINCTRL_PIN(133, "FAN_TACH_0"), 437 PINCTRL_PIN(134, "FAN_TACH_1"), 438 PINCTRL_PIN(135, "FAN_TACH_2"), 439 PINCTRL_PIN(136, "FAN_TACH_3"), 440 PINCTRL_PIN(137, "FAN_TACH_4"), 441 PINCTRL_PIN(138, "FAN_TACH_5"), 442 PINCTRL_PIN(139, "FAN_TACH_6"), 443 PINCTRL_PIN(140, "FAN_TACH_7"), 444 PINCTRL_PIN(141, "FAN_PWM_0"), 445 PINCTRL_PIN(142, "FAN_PWM_1"), 446 PINCTRL_PIN(143, "FAN_PWM_2"), 447 PINCTRL_PIN(144, "FAN_PWM_3"), 448 PINCTRL_PIN(145, "GSXDOUT"), 449 PINCTRL_PIN(146, "GSXSLOAD"), 450 PINCTRL_PIN(147, "GSXDIN"), 451 PINCTRL_PIN(148, "GSXRESETB"), 452 PINCTRL_PIN(149, "GSXCLK"), 453 PINCTRL_PIN(150, "ADR_COMPLETE"), 454 PINCTRL_PIN(151, "NMIB"), 455 PINCTRL_PIN(152, "SMIB"), 456 PINCTRL_PIN(153, "GPP_G_20"), 457 PINCTRL_PIN(154, "GPP_G_21"), 458 PINCTRL_PIN(155, "GPP_G_22"), 459 PINCTRL_PIN(156, "GPP_G_23"), 460 /* GPP_H */ 461 PINCTRL_PIN(157, "SRCCLKREQB_6"), 462 PINCTRL_PIN(158, "SRCCLKREQB_7"), 463 PINCTRL_PIN(159, "SRCCLKREQB_8"), 464 PINCTRL_PIN(160, "SRCCLKREQB_9"), 465 PINCTRL_PIN(161, "SRCCLKREQB_10"), 466 PINCTRL_PIN(162, "SRCCLKREQB_11"), 467 PINCTRL_PIN(163, "SRCCLKREQB_12"), 468 PINCTRL_PIN(164, "SRCCLKREQB_13"), 469 PINCTRL_PIN(165, "SRCCLKREQB_14"), 470 PINCTRL_PIN(166, "SRCCLKREQB_15"), 471 PINCTRL_PIN(167, "SML2CLK"), 472 PINCTRL_PIN(168, "SML2DATA"), 473 PINCTRL_PIN(169, "SML2ALERTB"), 474 PINCTRL_PIN(170, "SML3CLK"), 475 PINCTRL_PIN(171, "SML3DATA"), 476 PINCTRL_PIN(172, "SML3ALERTB"), 477 PINCTRL_PIN(173, "SML4CLK"), 478 PINCTRL_PIN(174, "SML4DATA"), 479 PINCTRL_PIN(175, "SML4ALERTB"), 480 PINCTRL_PIN(176, "ISH_I2C0_SDA"), 481 PINCTRL_PIN(177, "ISH_I2C0_SCL"), 482 PINCTRL_PIN(178, "ISH_I2C1_SDA"), 483 PINCTRL_PIN(179, "ISH_I2C1_SCL"), 484 PINCTRL_PIN(180, "GPP_H_23"), 485 /* GPP_I */ 486 PINCTRL_PIN(181, "DDSP_HDP_0"), 487 PINCTRL_PIN(182, "DDSP_HDP_1"), 488 PINCTRL_PIN(183, "DDSP_HDP_2"), 489 PINCTRL_PIN(184, "DDSP_HDP_3"), 490 PINCTRL_PIN(185, "EDP_HPD"), 491 PINCTRL_PIN(186, "DDPB_CTRLCLK"), 492 PINCTRL_PIN(187, "DDPB_CTRLDATA"), 493 PINCTRL_PIN(188, "DDPC_CTRLCLK"), 494 PINCTRL_PIN(189, "DDPC_CTRLDATA"), 495 PINCTRL_PIN(190, "DDPD_CTRLCLK"), 496 PINCTRL_PIN(191, "DDPD_CTRLDATA"), 497 }; 498 499 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 }; 500 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 }; 501 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 }; 502 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 }; 503 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 }; 504 static const unsigned spth_i2c0_pins[] = { 64, 65 }; 505 static const unsigned spth_i2c1_pins[] = { 66, 67 }; 506 static const unsigned spth_i2c2_pins[] = { 76, 95 }; 507 508 static const struct intel_pingroup spth_groups[] = { 509 PIN_GROUP("spi0_grp", spth_spi0_pins, 1), 510 PIN_GROUP("spi1_grp", spth_spi1_pins, 1), 511 PIN_GROUP("uart0_grp", spth_uart0_pins, 1), 512 PIN_GROUP("uart1_grp", spth_uart1_pins, 1), 513 PIN_GROUP("uart2_grp", spth_uart2_pins, 1), 514 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1), 515 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1), 516 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2), 517 }; 518 519 static const char * const spth_spi0_groups[] = { "spi0_grp" }; 520 static const char * const spth_spi1_groups[] = { "spi0_grp" }; 521 static const char * const spth_uart0_groups[] = { "uart0_grp" }; 522 static const char * const spth_uart1_groups[] = { "uart1_grp" }; 523 static const char * const spth_uart2_groups[] = { "uart2_grp" }; 524 static const char * const spth_i2c0_groups[] = { "i2c0_grp" }; 525 static const char * const spth_i2c1_groups[] = { "i2c1_grp" }; 526 static const char * const spth_i2c2_groups[] = { "i2c2_grp" }; 527 528 static const struct intel_function spth_functions[] = { 529 FUNCTION("spi0", spth_spi0_groups), 530 FUNCTION("spi1", spth_spi1_groups), 531 FUNCTION("uart0", spth_uart0_groups), 532 FUNCTION("uart1", spth_uart1_groups), 533 FUNCTION("uart2", spth_uart2_groups), 534 FUNCTION("i2c0", spth_i2c0_groups), 535 FUNCTION("i2c1", spth_i2c1_groups), 536 FUNCTION("i2c2", spth_i2c2_groups), 537 }; 538 539 static const struct intel_padgroup spth_community0_gpps[] = { 540 SPT_H_GPP(0, 0, 23, 0), /* GPP_A */ 541 SPT_H_GPP(1, 24, 47, 24), /* GPP_B */ 542 }; 543 544 static const struct intel_padgroup spth_community1_gpps[] = { 545 SPT_H_GPP(0, 48, 71, 48), /* GPP_C */ 546 SPT_H_GPP(1, 72, 95, 72), /* GPP_D */ 547 SPT_H_GPP(2, 96, 108, 96), /* GPP_E */ 548 SPT_H_GPP(3, 109, 132, 120), /* GPP_F */ 549 SPT_H_GPP(4, 133, 156, 144), /* GPP_G */ 550 SPT_H_GPP(5, 157, 180, 168), /* GPP_H */ 551 }; 552 553 static const struct intel_padgroup spth_community3_gpps[] = { 554 SPT_H_GPP(0, 181, 191, 192), /* GPP_I */ 555 }; 556 557 static const struct intel_community spth_communities[] = { 558 SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps), 559 SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps), 560 SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps), 561 }; 562 563 static const struct intel_pinctrl_soc_data spth_soc_data = { 564 .pins = spth_pins, 565 .npins = ARRAY_SIZE(spth_pins), 566 .groups = spth_groups, 567 .ngroups = ARRAY_SIZE(spth_groups), 568 .functions = spth_functions, 569 .nfunctions = ARRAY_SIZE(spth_functions), 570 .communities = spth_communities, 571 .ncommunities = ARRAY_SIZE(spth_communities), 572 }; 573 574 static const struct acpi_device_id spt_pinctrl_acpi_match[] = { 575 { "INT344B", (kernel_ulong_t)&sptlp_soc_data }, 576 { "INT3451", (kernel_ulong_t)&spth_soc_data }, 577 { "INT345D", (kernel_ulong_t)&spth_soc_data }, 578 { } 579 }; 580 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match); 581 582 static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops); 583 584 static struct platform_driver spt_pinctrl_driver = { 585 .probe = intel_pinctrl_probe_by_hid, 586 .driver = { 587 .name = "sunrisepoint-pinctrl", 588 .acpi_match_table = spt_pinctrl_acpi_match, 589 .pm = &spt_pinctrl_pm_ops, 590 }, 591 }; 592 593 static int __init spt_pinctrl_init(void) 594 { 595 return platform_driver_register(&spt_pinctrl_driver); 596 } 597 subsys_initcall(spt_pinctrl_init); 598 599 static void __exit spt_pinctrl_exit(void) 600 { 601 platform_driver_unregister(&spt_pinctrl_driver); 602 } 603 module_exit(spt_pinctrl_exit); 604 605 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 606 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 607 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver"); 608 MODULE_LICENSE("GPL v2"); 609