1 /* 2 * Intel Merrifield SoC pinctrl driver 3 * 4 * Copyright (C) 2016, Intel Corporation 5 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/platform_device.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 23 #include "pinctrl-intel.h" 24 25 #define MRFLD_FAMILY_NR 64 26 #define MRFLD_FAMILY_LEN 0x400 27 28 #define SLEW_OFFSET 0x000 29 #define BUFCFG_OFFSET 0x100 30 #define MISC_OFFSET 0x300 31 32 #define BUFCFG_PINMODE_SHIFT 0 33 #define BUFCFG_PINMODE_MASK GENMASK(2, 0) 34 #define BUFCFG_PINMODE_GPIO 0 35 #define BUFCFG_PUPD_VAL_SHIFT 4 36 #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) 37 #define BUFCFG_PUPD_VAL_2K 0 38 #define BUFCFG_PUPD_VAL_20K 1 39 #define BUFCFG_PUPD_VAL_50K 2 40 #define BUFCFG_PUPD_VAL_910 3 41 #define BUFCFG_PU_EN BIT(8) 42 #define BUFCFG_PD_EN BIT(9) 43 #define BUFCFG_Px_EN_MASK GENMASK(9, 8) 44 #define BUFCFG_SLEWSEL BIT(10) 45 #define BUFCFG_OVINEN BIT(12) 46 #define BUFCFG_OVINEN_EN BIT(13) 47 #define BUFCFG_OVINEN_MASK GENMASK(13, 12) 48 #define BUFCFG_OVOUTEN BIT(14) 49 #define BUFCFG_OVOUTEN_EN BIT(15) 50 #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) 51 #define BUFCFG_INDATAOV_VAL BIT(16) 52 #define BUFCFG_INDATAOV_EN BIT(17) 53 #define BUFCFG_INDATAOV_MASK GENMASK(17, 16) 54 #define BUFCFG_OUTDATAOV_VAL BIT(18) 55 #define BUFCFG_OUTDATAOV_EN BIT(19) 56 #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) 57 #define BUFCFG_OD_EN BIT(21) 58 59 /** 60 * struct mrfld_family - Intel pin family description 61 * @barno: MMIO BAR number where registers for this family reside 62 * @pin_base: Starting pin of pins in this family 63 * @npins: Number of pins in this family 64 * @protected: True if family is protected by access 65 * @regs: family specific common registers 66 */ 67 struct mrfld_family { 68 unsigned int barno; 69 unsigned int pin_base; 70 size_t npins; 71 bool protected; 72 void __iomem *regs; 73 }; 74 75 #define MRFLD_FAMILY(b, s, e) \ 76 { \ 77 .barno = (b), \ 78 .pin_base = (s), \ 79 .npins = (e) - (s) + 1, \ 80 } 81 82 #define MRFLD_FAMILY_PROTECTED(b, s, e) \ 83 { \ 84 .barno = (b), \ 85 .pin_base = (s), \ 86 .npins = (e) - (s) + 1, \ 87 .protected = true, \ 88 } 89 90 static const struct pinctrl_pin_desc mrfld_pins[] = { 91 /* Family 0: OCP2SSC (0 pins) */ 92 /* Family 1: ULPI (13 pins) */ 93 PINCTRL_PIN(0, "ULPI_CLK"), 94 PINCTRL_PIN(1, "ULPI_D0"), 95 PINCTRL_PIN(2, "ULPI_D1"), 96 PINCTRL_PIN(3, "ULPI_D2"), 97 PINCTRL_PIN(4, "ULPI_D3"), 98 PINCTRL_PIN(5, "ULPI_D4"), 99 PINCTRL_PIN(6, "ULPI_D5"), 100 PINCTRL_PIN(7, "ULPI_D6"), 101 PINCTRL_PIN(8, "ULPI_D7"), 102 PINCTRL_PIN(9, "ULPI_DIR"), 103 PINCTRL_PIN(10, "ULPI_NXT"), 104 PINCTRL_PIN(11, "ULPI_REFCLK"), 105 PINCTRL_PIN(12, "ULPI_STP"), 106 /* Family 2: eMMC (24 pins) */ 107 PINCTRL_PIN(13, "EMMC_CLK"), 108 PINCTRL_PIN(14, "EMMC_CMD"), 109 PINCTRL_PIN(15, "EMMC_D0"), 110 PINCTRL_PIN(16, "EMMC_D1"), 111 PINCTRL_PIN(17, "EMMC_D2"), 112 PINCTRL_PIN(18, "EMMC_D3"), 113 PINCTRL_PIN(19, "EMMC_D4"), 114 PINCTRL_PIN(20, "EMMC_D5"), 115 PINCTRL_PIN(21, "EMMC_D6"), 116 PINCTRL_PIN(22, "EMMC_D7"), 117 PINCTRL_PIN(23, "EMMC_RST_N"), 118 PINCTRL_PIN(24, "GP154"), 119 PINCTRL_PIN(25, "GP155"), 120 PINCTRL_PIN(26, "GP156"), 121 PINCTRL_PIN(27, "GP157"), 122 PINCTRL_PIN(28, "GP158"), 123 PINCTRL_PIN(29, "GP159"), 124 PINCTRL_PIN(30, "GP160"), 125 PINCTRL_PIN(31, "GP161"), 126 PINCTRL_PIN(32, "GP162"), 127 PINCTRL_PIN(33, "GP163"), 128 PINCTRL_PIN(34, "GP97"), 129 PINCTRL_PIN(35, "GP14"), 130 PINCTRL_PIN(36, "GP15"), 131 /* Family 3: SDIO (20 pins) */ 132 PINCTRL_PIN(37, "GP77_SD_CD"), 133 PINCTRL_PIN(38, "GP78_SD_CLK"), 134 PINCTRL_PIN(39, "GP79_SD_CMD"), 135 PINCTRL_PIN(40, "GP80_SD_D0"), 136 PINCTRL_PIN(41, "GP81_SD_D1"), 137 PINCTRL_PIN(42, "GP82_SD_D2"), 138 PINCTRL_PIN(43, "GP83_SD_D3"), 139 PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"), 140 PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"), 141 PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"), 142 PINCTRL_PIN(47, "GP88_SD_LS_SEL"), 143 PINCTRL_PIN(48, "GP87_SD_PD"), 144 PINCTRL_PIN(49, "GP89_SD_WP"), 145 PINCTRL_PIN(50, "GP90_SDIO_CLK"), 146 PINCTRL_PIN(51, "GP91_SDIO_CMD"), 147 PINCTRL_PIN(52, "GP92_SDIO_D0"), 148 PINCTRL_PIN(53, "GP93_SDIO_D1"), 149 PINCTRL_PIN(54, "GP94_SDIO_D2"), 150 PINCTRL_PIN(55, "GP95_SDIO_D3"), 151 PINCTRL_PIN(56, "GP96_SDIO_PD"), 152 /* Family 4: HSI (8 pins) */ 153 PINCTRL_PIN(57, "HSI_ACDATA"), 154 PINCTRL_PIN(58, "HSI_ACFLAG"), 155 PINCTRL_PIN(59, "HSI_ACREADY"), 156 PINCTRL_PIN(60, "HSI_ACWAKE"), 157 PINCTRL_PIN(61, "HSI_CADATA"), 158 PINCTRL_PIN(62, "HSI_CAFLAG"), 159 PINCTRL_PIN(63, "HSI_CAREADY"), 160 PINCTRL_PIN(64, "HSI_CAWAKE"), 161 /* Family 5: SSP Audio (14 pins) */ 162 PINCTRL_PIN(65, "GP70"), 163 PINCTRL_PIN(66, "GP71"), 164 PINCTRL_PIN(67, "GP32_I2S_0_CLK"), 165 PINCTRL_PIN(68, "GP33_I2S_0_FS"), 166 PINCTRL_PIN(69, "GP34_I2S_0_RXD"), 167 PINCTRL_PIN(70, "GP35_I2S_0_TXD"), 168 PINCTRL_PIN(71, "GP36_I2S_1_CLK"), 169 PINCTRL_PIN(72, "GP37_I2S_1_FS"), 170 PINCTRL_PIN(73, "GP38_I2S_1_RXD"), 171 PINCTRL_PIN(74, "GP39_I2S_1_TXD"), 172 PINCTRL_PIN(75, "GP40_I2S_2_CLK"), 173 PINCTRL_PIN(76, "GP41_I2S_2_FS"), 174 PINCTRL_PIN(77, "GP42_I2S_2_RXD"), 175 PINCTRL_PIN(78, "GP43_I2S_2_TXD"), 176 /* Family 6: GP SSP (22 pins) */ 177 PINCTRL_PIN(79, "GP120_SPI_3_CLK"), 178 PINCTRL_PIN(80, "GP121_SPI_3_SS"), 179 PINCTRL_PIN(81, "GP122_SPI_3_RXD"), 180 PINCTRL_PIN(82, "GP123_SPI_3_TXD"), 181 PINCTRL_PIN(83, "GP102_SPI_4_CLK"), 182 PINCTRL_PIN(84, "GP103_SPI_4_SS_0"), 183 PINCTRL_PIN(85, "GP104_SPI_4_SS_1"), 184 PINCTRL_PIN(86, "GP105_SPI_4_SS_2"), 185 PINCTRL_PIN(87, "GP106_SPI_4_SS_3"), 186 PINCTRL_PIN(88, "GP107_SPI_4_RXD"), 187 PINCTRL_PIN(89, "GP108_SPI_4_TXD"), 188 PINCTRL_PIN(90, "GP109_SPI_5_CLK"), 189 PINCTRL_PIN(91, "GP110_SPI_5_SS_0"), 190 PINCTRL_PIN(92, "GP111_SPI_5_SS_1"), 191 PINCTRL_PIN(93, "GP112_SPI_5_SS_2"), 192 PINCTRL_PIN(94, "GP113_SPI_5_SS_3"), 193 PINCTRL_PIN(95, "GP114_SPI_5_RXD"), 194 PINCTRL_PIN(96, "GP115_SPI_5_TXD"), 195 PINCTRL_PIN(97, "GP116_SPI_6_CLK"), 196 PINCTRL_PIN(98, "GP117_SPI_6_SS"), 197 PINCTRL_PIN(99, "GP118_SPI_6_RXD"), 198 PINCTRL_PIN(100, "GP119_SPI_6_TXD"), 199 /* Family 7: I2C (14 pins) */ 200 PINCTRL_PIN(101, "GP19_I2C_1_SCL"), 201 PINCTRL_PIN(102, "GP20_I2C_1_SDA"), 202 PINCTRL_PIN(103, "GP21_I2C_2_SCL"), 203 PINCTRL_PIN(104, "GP22_I2C_2_SDA"), 204 PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"), 205 PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"), 206 PINCTRL_PIN(107, "GP23_I2C_4_SCL"), 207 PINCTRL_PIN(108, "GP24_I2C_4_SDA"), 208 PINCTRL_PIN(109, "GP25_I2C_5_SCL"), 209 PINCTRL_PIN(110, "GP26_I2C_5_SDA"), 210 PINCTRL_PIN(111, "GP27_I2C_6_SCL"), 211 PINCTRL_PIN(112, "GP28_I2C_6_SDA"), 212 PINCTRL_PIN(113, "GP29_I2C_7_SCL"), 213 PINCTRL_PIN(114, "GP30_I2C_7_SDA"), 214 /* Family 8: UART (12 pins) */ 215 PINCTRL_PIN(115, "GP124_UART_0_CTS"), 216 PINCTRL_PIN(116, "GP125_UART_0_RTS"), 217 PINCTRL_PIN(117, "GP126_UART_0_RX"), 218 PINCTRL_PIN(118, "GP127_UART_0_TX"), 219 PINCTRL_PIN(119, "GP128_UART_1_CTS"), 220 PINCTRL_PIN(120, "GP129_UART_1_RTS"), 221 PINCTRL_PIN(121, "GP130_UART_1_RX"), 222 PINCTRL_PIN(122, "GP131_UART_1_TX"), 223 PINCTRL_PIN(123, "GP132_UART_2_CTS"), 224 PINCTRL_PIN(124, "GP133_UART_2_RTS"), 225 PINCTRL_PIN(125, "GP134_UART_2_RX"), 226 PINCTRL_PIN(126, "GP135_UART_2_TX"), 227 /* Family 9: GPIO South (19 pins) */ 228 PINCTRL_PIN(127, "GP177"), 229 PINCTRL_PIN(128, "GP178"), 230 PINCTRL_PIN(129, "GP179"), 231 PINCTRL_PIN(130, "GP180"), 232 PINCTRL_PIN(131, "GP181"), 233 PINCTRL_PIN(132, "GP182_PWM2"), 234 PINCTRL_PIN(133, "GP183_PWM3"), 235 PINCTRL_PIN(134, "GP184"), 236 PINCTRL_PIN(135, "GP185"), 237 PINCTRL_PIN(136, "GP186"), 238 PINCTRL_PIN(137, "GP187"), 239 PINCTRL_PIN(138, "GP188"), 240 PINCTRL_PIN(139, "GP189"), 241 PINCTRL_PIN(140, "GP64_FAST_INT0"), 242 PINCTRL_PIN(141, "GP65_FAST_INT1"), 243 PINCTRL_PIN(142, "GP66_FAST_INT2"), 244 PINCTRL_PIN(143, "GP67_FAST_INT3"), 245 PINCTRL_PIN(144, "GP12_PWM0"), 246 PINCTRL_PIN(145, "GP13_PWM1"), 247 /* Family 10: Camera Sideband (12 pins) */ 248 PINCTRL_PIN(146, "GP0"), 249 PINCTRL_PIN(147, "GP1"), 250 PINCTRL_PIN(148, "GP2"), 251 PINCTRL_PIN(149, "GP3"), 252 PINCTRL_PIN(150, "GP4"), 253 PINCTRL_PIN(151, "GP5"), 254 PINCTRL_PIN(152, "GP6"), 255 PINCTRL_PIN(153, "GP7"), 256 PINCTRL_PIN(154, "GP8"), 257 PINCTRL_PIN(155, "GP9"), 258 PINCTRL_PIN(156, "GP10"), 259 PINCTRL_PIN(157, "GP11"), 260 /* Family 11: Clock (22 pins) */ 261 PINCTRL_PIN(158, "GP137"), 262 PINCTRL_PIN(159, "GP138"), 263 PINCTRL_PIN(160, "GP139"), 264 PINCTRL_PIN(161, "GP140"), 265 PINCTRL_PIN(162, "GP141"), 266 PINCTRL_PIN(163, "GP142"), 267 PINCTRL_PIN(164, "GP16_HDMI_HPD"), 268 PINCTRL_PIN(165, "GP68_DSI_A_TE"), 269 PINCTRL_PIN(166, "GP69_DSI_C_TE"), 270 PINCTRL_PIN(167, "OSC_CLK_CTRL0"), 271 PINCTRL_PIN(168, "OSC_CLK_CTRL1"), 272 PINCTRL_PIN(169, "OSC_CLK0"), 273 PINCTRL_PIN(170, "OSC_CLK1"), 274 PINCTRL_PIN(171, "OSC_CLK2"), 275 PINCTRL_PIN(172, "OSC_CLK3"), 276 PINCTRL_PIN(173, "OSC_CLK4"), 277 PINCTRL_PIN(174, "RESETOUT"), 278 PINCTRL_PIN(175, "PMODE"), 279 PINCTRL_PIN(176, "PRDY"), 280 PINCTRL_PIN(177, "PREQ"), 281 PINCTRL_PIN(178, "GP190"), 282 PINCTRL_PIN(179, "GP191"), 283 /* Family 12: MSIC (15 pins) */ 284 PINCTRL_PIN(180, "I2C_0_SCL"), 285 PINCTRL_PIN(181, "I2C_0_SDA"), 286 PINCTRL_PIN(182, "IERR"), 287 PINCTRL_PIN(183, "JTAG_TCK"), 288 PINCTRL_PIN(184, "JTAG_TDI"), 289 PINCTRL_PIN(185, "JTAG_TDO"), 290 PINCTRL_PIN(186, "JTAG_TMS"), 291 PINCTRL_PIN(187, "JTAG_TRST"), 292 PINCTRL_PIN(188, "PROCHOT"), 293 PINCTRL_PIN(189, "RTC_CLK"), 294 PINCTRL_PIN(190, "SVID_ALERT"), 295 PINCTRL_PIN(191, "SVID_CLK"), 296 PINCTRL_PIN(192, "SVID_D"), 297 PINCTRL_PIN(193, "THERMTRIP"), 298 PINCTRL_PIN(194, "STANDBY"), 299 /* Family 13: Keyboard (20 pins) */ 300 PINCTRL_PIN(195, "GP44"), 301 PINCTRL_PIN(196, "GP45"), 302 PINCTRL_PIN(197, "GP46"), 303 PINCTRL_PIN(198, "GP47"), 304 PINCTRL_PIN(199, "GP48"), 305 PINCTRL_PIN(200, "GP49"), 306 PINCTRL_PIN(201, "GP50"), 307 PINCTRL_PIN(202, "GP51"), 308 PINCTRL_PIN(203, "GP52"), 309 PINCTRL_PIN(204, "GP53"), 310 PINCTRL_PIN(205, "GP54"), 311 PINCTRL_PIN(206, "GP55"), 312 PINCTRL_PIN(207, "GP56"), 313 PINCTRL_PIN(208, "GP57"), 314 PINCTRL_PIN(209, "GP58"), 315 PINCTRL_PIN(210, "GP59"), 316 PINCTRL_PIN(211, "GP60"), 317 PINCTRL_PIN(212, "GP61"), 318 PINCTRL_PIN(213, "GP62"), 319 PINCTRL_PIN(214, "GP63"), 320 /* Family 14: GPIO North (13 pins) */ 321 PINCTRL_PIN(215, "GP164"), 322 PINCTRL_PIN(216, "GP165"), 323 PINCTRL_PIN(217, "GP166"), 324 PINCTRL_PIN(218, "GP167"), 325 PINCTRL_PIN(219, "GP168_MJTAG_TCK"), 326 PINCTRL_PIN(220, "GP169_MJTAG_TDI"), 327 PINCTRL_PIN(221, "GP170_MJTAG_TDO"), 328 PINCTRL_PIN(222, "GP171_MJTAG_TMS"), 329 PINCTRL_PIN(223, "GP172_MJTAG_TRST"), 330 PINCTRL_PIN(224, "GP173"), 331 PINCTRL_PIN(225, "GP174"), 332 PINCTRL_PIN(226, "GP175"), 333 PINCTRL_PIN(227, "GP176"), 334 /* Family 15: PTI (5 pins) */ 335 PINCTRL_PIN(228, "GP72_PTI_CLK"), 336 PINCTRL_PIN(229, "GP73_PTI_D0"), 337 PINCTRL_PIN(230, "GP74_PTI_D1"), 338 PINCTRL_PIN(231, "GP75_PTI_D2"), 339 PINCTRL_PIN(232, "GP76_PTI_D3"), 340 /* Family 16: USB3 (0 pins) */ 341 /* Family 17: HSIC (0 pins) */ 342 /* Family 18: Broadcast (0 pins) */ 343 }; 344 345 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 }; 346 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 }; 347 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 }; 348 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 }; 349 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 }; 350 static const unsigned int mrfld_pwm0_pins[] = { 144 }; 351 static const unsigned int mrfld_pwm1_pins[] = { 145 }; 352 static const unsigned int mrfld_pwm2_pins[] = { 132 }; 353 static const unsigned int mrfld_pwm3_pins[] = { 133 }; 354 355 static const struct intel_pingroup mrfld_groups[] = { 356 PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1), 357 PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1), 358 PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1), 359 PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1), 360 PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1), 361 PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1), 362 PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1), 363 PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1), 364 PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1), 365 }; 366 367 static const char * const mrfld_sdio_groups[] = { "sdio_grp" }; 368 static const char * const mrfld_spi5_groups[] = { "spi5_grp" }; 369 static const char * const mrfld_uart0_groups[] = { "uart0_grp" }; 370 static const char * const mrfld_uart1_groups[] = { "uart1_grp" }; 371 static const char * const mrfld_uart2_groups[] = { "uart2_grp" }; 372 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" }; 373 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" }; 374 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" }; 375 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" }; 376 377 static const struct intel_function mrfld_functions[] = { 378 FUNCTION("sdio", mrfld_sdio_groups), 379 FUNCTION("spi5", mrfld_spi5_groups), 380 FUNCTION("uart0", mrfld_uart0_groups), 381 FUNCTION("uart1", mrfld_uart1_groups), 382 FUNCTION("uart2", mrfld_uart2_groups), 383 FUNCTION("pwm0", mrfld_pwm0_groups), 384 FUNCTION("pwm1", mrfld_pwm1_groups), 385 FUNCTION("pwm2", mrfld_pwm2_groups), 386 FUNCTION("pwm3", mrfld_pwm3_groups), 387 }; 388 389 static const struct mrfld_family mrfld_families[] = { 390 MRFLD_FAMILY(1, 0, 12), 391 MRFLD_FAMILY(2, 13, 36), 392 MRFLD_FAMILY(3, 37, 56), 393 MRFLD_FAMILY(4, 57, 64), 394 MRFLD_FAMILY(5, 65, 78), 395 MRFLD_FAMILY(6, 79, 100), 396 MRFLD_FAMILY_PROTECTED(7, 101, 114), 397 MRFLD_FAMILY(8, 115, 126), 398 MRFLD_FAMILY(9, 127, 145), 399 MRFLD_FAMILY(10, 146, 157), 400 MRFLD_FAMILY(11, 158, 179), 401 MRFLD_FAMILY_PROTECTED(12, 180, 194), 402 MRFLD_FAMILY(13, 195, 214), 403 MRFLD_FAMILY(14, 215, 227), 404 MRFLD_FAMILY(15, 228, 232), 405 }; 406 407 /** 408 * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure 409 * @dev: Pointer to the device structure 410 * @lock: Lock to serialize register access 411 * @pctldesc: Pin controller description 412 * @pctldev: Pointer to the pin controller device 413 * @families: Array of families this pinctrl handles 414 * @nfamilies: Number of families in the array 415 * @functions: Array of functions 416 * @nfunctions: Number of functions in the array 417 * @groups: Array of pin groups 418 * @ngroups: Number of groups in the array 419 * @pins: Array of pins this pinctrl controls 420 * @npins: Number of pins in the array 421 */ 422 struct mrfld_pinctrl { 423 struct device *dev; 424 raw_spinlock_t lock; 425 struct pinctrl_desc pctldesc; 426 struct pinctrl_dev *pctldev; 427 428 /* Pin controller configuration */ 429 const struct mrfld_family *families; 430 size_t nfamilies; 431 const struct intel_function *functions; 432 size_t nfunctions; 433 const struct intel_pingroup *groups; 434 size_t ngroups; 435 const struct pinctrl_pin_desc *pins; 436 size_t npins; 437 }; 438 439 #define pin_to_bufno(f, p) ((p) - (f)->pin_base) 440 441 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp, 442 unsigned int pin) 443 { 444 const struct mrfld_family *family; 445 unsigned int i; 446 447 for (i = 0; i < mp->nfamilies; i++) { 448 family = &mp->families[i]; 449 if (pin >= family->pin_base && 450 pin < family->pin_base + family->npins) 451 return family; 452 } 453 454 dev_warn(mp->dev, "failed to find family for pin %u\n", pin); 455 return NULL; 456 } 457 458 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin) 459 { 460 const struct mrfld_family *family; 461 462 family = mrfld_get_family(mp, pin); 463 if (!family) 464 return false; 465 466 return !family->protected; 467 } 468 469 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin) 470 { 471 const struct mrfld_family *family; 472 unsigned int bufno; 473 474 family = mrfld_get_family(mp, pin); 475 if (!family) 476 return NULL; 477 478 bufno = pin_to_bufno(family, pin); 479 return family->regs + BUFCFG_OFFSET + bufno * 4; 480 } 481 482 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) 483 { 484 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 485 486 return mp->ngroups; 487 } 488 489 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev, 490 unsigned int group) 491 { 492 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 493 494 return mp->groups[group].name; 495 } 496 497 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 498 const unsigned int **pins, unsigned int *npins) 499 { 500 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 501 502 *pins = mp->groups[group].pins; 503 *npins = mp->groups[group].npins; 504 return 0; 505 } 506 507 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 508 unsigned int pin) 509 { 510 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 511 void __iomem *bufcfg; 512 u32 value, mode; 513 514 if (!mrfld_buf_available(mp, pin)) { 515 seq_puts(s, "not available"); 516 return; 517 } 518 519 bufcfg = mrfld_get_bufcfg(mp, pin); 520 value = readl(bufcfg); 521 522 mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; 523 if (!mode) 524 seq_puts(s, "GPIO "); 525 else 526 seq_printf(s, "mode %d ", mode); 527 528 seq_printf(s, "0x%08x", value); 529 } 530 531 static const struct pinctrl_ops mrfld_pinctrl_ops = { 532 .get_groups_count = mrfld_get_groups_count, 533 .get_group_name = mrfld_get_group_name, 534 .get_group_pins = mrfld_get_group_pins, 535 .pin_dbg_show = mrfld_pin_dbg_show, 536 }; 537 538 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev) 539 { 540 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 541 542 return mp->nfunctions; 543 } 544 545 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, 546 unsigned int function) 547 { 548 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 549 550 return mp->functions[function].name; 551 } 552 553 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, 554 unsigned int function, 555 const char * const **groups, 556 unsigned int * const ngroups) 557 { 558 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 559 560 *groups = mp->functions[function].groups; 561 *ngroups = mp->functions[function].ngroups; 562 return 0; 563 } 564 565 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, 566 u32 bits, u32 mask) 567 { 568 void __iomem *bufcfg; 569 u32 value; 570 571 bufcfg = mrfld_get_bufcfg(mp, pin); 572 value = readl(bufcfg); 573 574 value &= ~mask; 575 value |= bits & mask; 576 577 writel(value, bufcfg); 578 } 579 580 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, 581 unsigned int function, 582 unsigned int group) 583 { 584 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 585 const struct intel_pingroup *grp = &mp->groups[group]; 586 u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; 587 u32 mask = BUFCFG_PINMODE_MASK; 588 unsigned long flags; 589 unsigned int i; 590 591 /* 592 * All pins in the groups needs to be accessible and writable 593 * before we can enable the mux for this group. 594 */ 595 for (i = 0; i < grp->npins; i++) { 596 if (!mrfld_buf_available(mp, grp->pins[i])) 597 return -EBUSY; 598 } 599 600 /* Now enable the mux setting for each pin in the group */ 601 raw_spin_lock_irqsave(&mp->lock, flags); 602 for (i = 0; i < grp->npins; i++) 603 mrfld_update_bufcfg(mp, grp->pins[i], bits, mask); 604 raw_spin_unlock_irqrestore(&mp->lock, flags); 605 606 return 0; 607 } 608 609 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev, 610 struct pinctrl_gpio_range *range, 611 unsigned int pin) 612 { 613 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 614 u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; 615 u32 mask = BUFCFG_PINMODE_MASK; 616 unsigned long flags; 617 618 if (!mrfld_buf_available(mp, pin)) 619 return -EBUSY; 620 621 raw_spin_lock_irqsave(&mp->lock, flags); 622 mrfld_update_bufcfg(mp, pin, bits, mask); 623 raw_spin_unlock_irqrestore(&mp->lock, flags); 624 625 return 0; 626 } 627 628 static const struct pinmux_ops mrfld_pinmux_ops = { 629 .get_functions_count = mrfld_get_functions_count, 630 .get_function_name = mrfld_get_function_name, 631 .get_function_groups = mrfld_get_function_groups, 632 .set_mux = mrfld_pinmux_set_mux, 633 .gpio_request_enable = mrfld_gpio_request_enable, 634 }; 635 636 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 637 unsigned long *config) 638 { 639 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 640 enum pin_config_param param = pinconf_to_config_param(*config); 641 u32 value, term; 642 u16 arg = 0; 643 644 if (!mrfld_buf_available(mp, pin)) 645 return -ENOTSUPP; 646 647 value = readl(mrfld_get_bufcfg(mp, pin)); 648 term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; 649 650 switch (param) { 651 case PIN_CONFIG_BIAS_DISABLE: 652 if (value & BUFCFG_Px_EN_MASK) 653 return -EINVAL; 654 break; 655 656 case PIN_CONFIG_BIAS_PULL_UP: 657 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) 658 return -EINVAL; 659 660 switch (term) { 661 case BUFCFG_PUPD_VAL_910: 662 arg = 910; 663 break; 664 case BUFCFG_PUPD_VAL_2K: 665 arg = 2000; 666 break; 667 case BUFCFG_PUPD_VAL_20K: 668 arg = 20000; 669 break; 670 case BUFCFG_PUPD_VAL_50K: 671 arg = 50000; 672 break; 673 } 674 675 break; 676 677 case PIN_CONFIG_BIAS_PULL_DOWN: 678 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) 679 return -EINVAL; 680 681 switch (term) { 682 case BUFCFG_PUPD_VAL_910: 683 arg = 910; 684 break; 685 case BUFCFG_PUPD_VAL_2K: 686 arg = 2000; 687 break; 688 case BUFCFG_PUPD_VAL_20K: 689 arg = 20000; 690 break; 691 case BUFCFG_PUPD_VAL_50K: 692 arg = 50000; 693 break; 694 } 695 696 break; 697 698 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 699 if (!(value & BUFCFG_OD_EN)) 700 return -EINVAL; 701 break; 702 703 case PIN_CONFIG_SLEW_RATE: 704 if (!(value & BUFCFG_SLEWSEL)) 705 arg = 0; 706 else 707 arg = 1; 708 break; 709 710 default: 711 return -ENOTSUPP; 712 } 713 714 *config = pinconf_to_config_packed(param, arg); 715 return 0; 716 } 717 718 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, 719 unsigned long config) 720 { 721 unsigned int param = pinconf_to_config_param(config); 722 unsigned int arg = pinconf_to_config_argument(config); 723 u32 bits = 0, mask = 0; 724 unsigned long flags; 725 726 switch (param) { 727 case PIN_CONFIG_BIAS_DISABLE: 728 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 729 break; 730 731 case PIN_CONFIG_BIAS_PULL_UP: 732 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 733 bits |= BUFCFG_PU_EN; 734 735 switch (arg) { 736 case 50000: 737 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; 738 break; 739 case 20000: 740 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; 741 break; 742 case 2000: 743 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; 744 break; 745 default: 746 return -EINVAL; 747 } 748 749 break; 750 751 case PIN_CONFIG_BIAS_PULL_DOWN: 752 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; 753 bits |= BUFCFG_PD_EN; 754 755 switch (arg) { 756 case 50000: 757 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; 758 break; 759 case 20000: 760 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; 761 break; 762 case 2000: 763 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; 764 break; 765 default: 766 return -EINVAL; 767 } 768 769 break; 770 771 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 772 mask |= BUFCFG_OD_EN; 773 if (arg) 774 bits |= BUFCFG_OD_EN; 775 break; 776 777 case PIN_CONFIG_SLEW_RATE: 778 mask |= BUFCFG_SLEWSEL; 779 if (arg) 780 bits |= BUFCFG_SLEWSEL; 781 break; 782 } 783 784 raw_spin_lock_irqsave(&mp->lock, flags); 785 mrfld_update_bufcfg(mp, pin, bits, mask); 786 raw_spin_unlock_irqrestore(&mp->lock, flags); 787 788 return 0; 789 } 790 791 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 792 unsigned long *configs, unsigned int nconfigs) 793 { 794 struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); 795 unsigned int i; 796 int ret; 797 798 if (!mrfld_buf_available(mp, pin)) 799 return -ENOTSUPP; 800 801 for (i = 0; i < nconfigs; i++) { 802 switch (pinconf_to_config_param(configs[i])) { 803 case PIN_CONFIG_BIAS_DISABLE: 804 case PIN_CONFIG_BIAS_PULL_UP: 805 case PIN_CONFIG_BIAS_PULL_DOWN: 806 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 807 case PIN_CONFIG_SLEW_RATE: 808 ret = mrfld_config_set_pin(mp, pin, configs[i]); 809 if (ret) 810 return ret; 811 break; 812 813 default: 814 return -ENOTSUPP; 815 } 816 } 817 818 return 0; 819 } 820 821 static int mrfld_config_group_get(struct pinctrl_dev *pctldev, 822 unsigned int group, unsigned long *config) 823 { 824 const unsigned int *pins; 825 unsigned int npins; 826 int ret; 827 828 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); 829 if (ret) 830 return ret; 831 832 ret = mrfld_config_get(pctldev, pins[0], config); 833 if (ret) 834 return ret; 835 836 return 0; 837 } 838 839 static int mrfld_config_group_set(struct pinctrl_dev *pctldev, 840 unsigned int group, unsigned long *configs, 841 unsigned int num_configs) 842 { 843 const unsigned int *pins; 844 unsigned int npins; 845 int i, ret; 846 847 ret = mrfld_get_group_pins(pctldev, group, &pins, &npins); 848 if (ret) 849 return ret; 850 851 for (i = 0; i < npins; i++) { 852 ret = mrfld_config_set(pctldev, pins[i], configs, num_configs); 853 if (ret) 854 return ret; 855 } 856 857 return 0; 858 } 859 860 static const struct pinconf_ops mrfld_pinconf_ops = { 861 .is_generic = true, 862 .pin_config_get = mrfld_config_get, 863 .pin_config_set = mrfld_config_set, 864 .pin_config_group_get = mrfld_config_group_get, 865 .pin_config_group_set = mrfld_config_group_set, 866 }; 867 868 static const struct pinctrl_desc mrfld_pinctrl_desc = { 869 .pctlops = &mrfld_pinctrl_ops, 870 .pmxops = &mrfld_pinmux_ops, 871 .confops = &mrfld_pinconf_ops, 872 .owner = THIS_MODULE, 873 }; 874 875 static int mrfld_pinctrl_probe(struct platform_device *pdev) 876 { 877 struct mrfld_family *families; 878 struct mrfld_pinctrl *mp; 879 struct resource *mem; 880 void __iomem *regs; 881 size_t nfamilies; 882 unsigned int i; 883 884 mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); 885 if (!mp) 886 return -ENOMEM; 887 888 mp->dev = &pdev->dev; 889 raw_spin_lock_init(&mp->lock); 890 891 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 892 regs = devm_ioremap_resource(&pdev->dev, mem); 893 if (IS_ERR(regs)) 894 return PTR_ERR(regs); 895 896 /* 897 * Make a copy of the families which we can use to hold pointers 898 * to the registers. 899 */ 900 nfamilies = ARRAY_SIZE(mrfld_families), 901 families = devm_kmemdup(&pdev->dev, mrfld_families, 902 sizeof(mrfld_families), 903 GFP_KERNEL); 904 if (!families) 905 return -ENOMEM; 906 907 /* Splice memory resource by chunk per family */ 908 for (i = 0; i < nfamilies; i++) { 909 struct mrfld_family *family = &families[i]; 910 911 family->regs = regs + family->barno * MRFLD_FAMILY_LEN; 912 } 913 914 mp->families = families; 915 mp->nfamilies = nfamilies; 916 mp->functions = mrfld_functions; 917 mp->nfunctions = ARRAY_SIZE(mrfld_functions); 918 mp->groups = mrfld_groups; 919 mp->ngroups = ARRAY_SIZE(mrfld_groups); 920 mp->pctldesc = mrfld_pinctrl_desc; 921 mp->pctldesc.name = dev_name(&pdev->dev); 922 mp->pctldesc.pins = mrfld_pins; 923 mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); 924 925 mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp); 926 if (IS_ERR(mp->pctldev)) { 927 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 928 return PTR_ERR(mp->pctldev); 929 } 930 931 platform_set_drvdata(pdev, mp); 932 return 0; 933 } 934 935 static const struct acpi_device_id mrfld_acpi_table[] = { 936 { "INTC1002" }, 937 { } 938 }; 939 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table); 940 941 static struct platform_driver mrfld_pinctrl_driver = { 942 .probe = mrfld_pinctrl_probe, 943 .driver = { 944 .name = "pinctrl-merrifield", 945 .acpi_match_table = mrfld_acpi_table, 946 }, 947 }; 948 949 static int __init mrfld_pinctrl_init(void) 950 { 951 return platform_driver_register(&mrfld_pinctrl_driver); 952 } 953 subsys_initcall(mrfld_pinctrl_init); 954 955 static void __exit mrfld_pinctrl_exit(void) 956 { 957 platform_driver_unregister(&mrfld_pinctrl_driver); 958 } 959 module_exit(mrfld_pinctrl_exit); 960 961 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 962 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver"); 963 MODULE_LICENSE("GPL v2"); 964 MODULE_ALIAS("platform:pinctrl-merrifield"); 965