1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Merrifield SoC pinctrl driver
4  *
5  * Copyright (C) 2016, Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  */
8 
9 #include <linux/bits.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/platform_device.h>
15 #include <linux/seq_file.h>
16 
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 
22 #include "pinctrl-intel.h"
23 
24 #define MRFLD_FAMILY_NR			64
25 #define MRFLD_FAMILY_LEN		0x400
26 
27 #define SLEW_OFFSET			0x000
28 #define BUFCFG_OFFSET			0x100
29 #define MISC_OFFSET			0x300
30 
31 #define BUFCFG_PINMODE_SHIFT		0
32 #define BUFCFG_PINMODE_MASK		GENMASK(2, 0)
33 #define BUFCFG_PINMODE_GPIO		0
34 #define BUFCFG_PUPD_VAL_SHIFT		4
35 #define BUFCFG_PUPD_VAL_MASK		GENMASK(5, 4)
36 #define BUFCFG_PUPD_VAL_2K		0
37 #define BUFCFG_PUPD_VAL_20K		1
38 #define BUFCFG_PUPD_VAL_50K		2
39 #define BUFCFG_PUPD_VAL_910		3
40 #define BUFCFG_PU_EN			BIT(8)
41 #define BUFCFG_PD_EN			BIT(9)
42 #define BUFCFG_Px_EN_MASK		GENMASK(9, 8)
43 #define BUFCFG_SLEWSEL			BIT(10)
44 #define BUFCFG_OVINEN			BIT(12)
45 #define BUFCFG_OVINEN_EN		BIT(13)
46 #define BUFCFG_OVINEN_MASK		GENMASK(13, 12)
47 #define BUFCFG_OVOUTEN			BIT(14)
48 #define BUFCFG_OVOUTEN_EN		BIT(15)
49 #define BUFCFG_OVOUTEN_MASK		GENMASK(15, 14)
50 #define BUFCFG_INDATAOV_VAL		BIT(16)
51 #define BUFCFG_INDATAOV_EN		BIT(17)
52 #define BUFCFG_INDATAOV_MASK		GENMASK(17, 16)
53 #define BUFCFG_OUTDATAOV_VAL		BIT(18)
54 #define BUFCFG_OUTDATAOV_EN		BIT(19)
55 #define BUFCFG_OUTDATAOV_MASK		GENMASK(19, 18)
56 #define BUFCFG_OD_EN			BIT(21)
57 
58 /**
59  * struct mrfld_family - Intel pin family description
60  * @barno: MMIO BAR number where registers for this family reside
61  * @pin_base: Starting pin of pins in this family
62  * @npins: Number of pins in this family
63  * @protected: True if family is protected by access
64  * @regs: family specific common registers
65  */
66 struct mrfld_family {
67 	unsigned int barno;
68 	unsigned int pin_base;
69 	size_t npins;
70 	bool protected;
71 	void __iomem *regs;
72 };
73 
74 #define MRFLD_FAMILY(b, s, e)				\
75 	{						\
76 		.barno = (b),				\
77 		.pin_base = (s),			\
78 		.npins = (e) - (s) + 1,			\
79 	}
80 
81 #define MRFLD_FAMILY_PROTECTED(b, s, e)			\
82 	{						\
83 		.barno = (b),				\
84 		.pin_base = (s),			\
85 		.npins = (e) - (s) + 1,			\
86 		.protected = true,			\
87 	}
88 
89 static const struct pinctrl_pin_desc mrfld_pins[] = {
90 	/* Family 0: OCP2SSC (0 pins) */
91 	/* Family 1: ULPI (13 pins) */
92 	PINCTRL_PIN(0, "ULPI_CLK"),
93 	PINCTRL_PIN(1, "ULPI_D0"),
94 	PINCTRL_PIN(2, "ULPI_D1"),
95 	PINCTRL_PIN(3, "ULPI_D2"),
96 	PINCTRL_PIN(4, "ULPI_D3"),
97 	PINCTRL_PIN(5, "ULPI_D4"),
98 	PINCTRL_PIN(6, "ULPI_D5"),
99 	PINCTRL_PIN(7, "ULPI_D6"),
100 	PINCTRL_PIN(8, "ULPI_D7"),
101 	PINCTRL_PIN(9, "ULPI_DIR"),
102 	PINCTRL_PIN(10, "ULPI_NXT"),
103 	PINCTRL_PIN(11, "ULPI_REFCLK"),
104 	PINCTRL_PIN(12, "ULPI_STP"),
105 	/* Family 2: eMMC (24 pins) */
106 	PINCTRL_PIN(13, "EMMC_CLK"),
107 	PINCTRL_PIN(14, "EMMC_CMD"),
108 	PINCTRL_PIN(15, "EMMC_D0"),
109 	PINCTRL_PIN(16, "EMMC_D1"),
110 	PINCTRL_PIN(17, "EMMC_D2"),
111 	PINCTRL_PIN(18, "EMMC_D3"),
112 	PINCTRL_PIN(19, "EMMC_D4"),
113 	PINCTRL_PIN(20, "EMMC_D5"),
114 	PINCTRL_PIN(21, "EMMC_D6"),
115 	PINCTRL_PIN(22, "EMMC_D7"),
116 	PINCTRL_PIN(23, "EMMC_RST_N"),
117 	PINCTRL_PIN(24, "GP154"),
118 	PINCTRL_PIN(25, "GP155"),
119 	PINCTRL_PIN(26, "GP156"),
120 	PINCTRL_PIN(27, "GP157"),
121 	PINCTRL_PIN(28, "GP158"),
122 	PINCTRL_PIN(29, "GP159"),
123 	PINCTRL_PIN(30, "GP160"),
124 	PINCTRL_PIN(31, "GP161"),
125 	PINCTRL_PIN(32, "GP162"),
126 	PINCTRL_PIN(33, "GP163"),
127 	PINCTRL_PIN(34, "GP97"),
128 	PINCTRL_PIN(35, "GP14"),
129 	PINCTRL_PIN(36, "GP15"),
130 	/* Family 3: SDIO (20 pins) */
131 	PINCTRL_PIN(37, "GP77_SD_CD"),
132 	PINCTRL_PIN(38, "GP78_SD_CLK"),
133 	PINCTRL_PIN(39, "GP79_SD_CMD"),
134 	PINCTRL_PIN(40, "GP80_SD_D0"),
135 	PINCTRL_PIN(41, "GP81_SD_D1"),
136 	PINCTRL_PIN(42, "GP82_SD_D2"),
137 	PINCTRL_PIN(43, "GP83_SD_D3"),
138 	PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
139 	PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
140 	PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
141 	PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
142 	PINCTRL_PIN(48, "GP87_SD_PD"),
143 	PINCTRL_PIN(49, "GP89_SD_WP"),
144 	PINCTRL_PIN(50, "GP90_SDIO_CLK"),
145 	PINCTRL_PIN(51, "GP91_SDIO_CMD"),
146 	PINCTRL_PIN(52, "GP92_SDIO_D0"),
147 	PINCTRL_PIN(53, "GP93_SDIO_D1"),
148 	PINCTRL_PIN(54, "GP94_SDIO_D2"),
149 	PINCTRL_PIN(55, "GP95_SDIO_D3"),
150 	PINCTRL_PIN(56, "GP96_SDIO_PD"),
151 	/* Family 4: HSI (8 pins) */
152 	PINCTRL_PIN(57, "HSI_ACDATA"),
153 	PINCTRL_PIN(58, "HSI_ACFLAG"),
154 	PINCTRL_PIN(59, "HSI_ACREADY"),
155 	PINCTRL_PIN(60, "HSI_ACWAKE"),
156 	PINCTRL_PIN(61, "HSI_CADATA"),
157 	PINCTRL_PIN(62, "HSI_CAFLAG"),
158 	PINCTRL_PIN(63, "HSI_CAREADY"),
159 	PINCTRL_PIN(64, "HSI_CAWAKE"),
160 	/* Family 5: SSP Audio (14 pins) */
161 	PINCTRL_PIN(65, "GP70"),
162 	PINCTRL_PIN(66, "GP71"),
163 	PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
164 	PINCTRL_PIN(68, "GP33_I2S_0_FS"),
165 	PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
166 	PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
167 	PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
168 	PINCTRL_PIN(72, "GP37_I2S_1_FS"),
169 	PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
170 	PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
171 	PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
172 	PINCTRL_PIN(76, "GP41_I2S_2_FS"),
173 	PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
174 	PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
175 	/* Family 6: GP SSP (22 pins) */
176 	PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
177 	PINCTRL_PIN(80, "GP121_SPI_0_SS"),
178 	PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
179 	PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
180 	PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
181 	PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
182 	PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
183 	PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
184 	PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
185 	PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
186 	PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
187 	PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
188 	PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
189 	PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
190 	PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
191 	PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
192 	PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
193 	PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
194 	PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
195 	PINCTRL_PIN(98, "GP117_SPI_3_SS"),
196 	PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
197 	PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
198 	/* Family 7: I2C (14 pins) */
199 	PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
200 	PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
201 	PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
202 	PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
203 	PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
204 	PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
205 	PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
206 	PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
207 	PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
208 	PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
209 	PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
210 	PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
211 	PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
212 	PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
213 	/* Family 8: UART (12 pins) */
214 	PINCTRL_PIN(115, "GP124_UART_0_CTS"),
215 	PINCTRL_PIN(116, "GP125_UART_0_RTS"),
216 	PINCTRL_PIN(117, "GP126_UART_0_RX"),
217 	PINCTRL_PIN(118, "GP127_UART_0_TX"),
218 	PINCTRL_PIN(119, "GP128_UART_1_CTS"),
219 	PINCTRL_PIN(120, "GP129_UART_1_RTS"),
220 	PINCTRL_PIN(121, "GP130_UART_1_RX"),
221 	PINCTRL_PIN(122, "GP131_UART_1_TX"),
222 	PINCTRL_PIN(123, "GP132_UART_2_CTS"),
223 	PINCTRL_PIN(124, "GP133_UART_2_RTS"),
224 	PINCTRL_PIN(125, "GP134_UART_2_RX"),
225 	PINCTRL_PIN(126, "GP135_UART_2_TX"),
226 	/* Family 9: GPIO South (19 pins) */
227 	PINCTRL_PIN(127, "GP177"),
228 	PINCTRL_PIN(128, "GP178"),
229 	PINCTRL_PIN(129, "GP179"),
230 	PINCTRL_PIN(130, "GP180"),
231 	PINCTRL_PIN(131, "GP181"),
232 	PINCTRL_PIN(132, "GP182_PWM2"),
233 	PINCTRL_PIN(133, "GP183_PWM3"),
234 	PINCTRL_PIN(134, "GP184"),
235 	PINCTRL_PIN(135, "GP185"),
236 	PINCTRL_PIN(136, "GP186"),
237 	PINCTRL_PIN(137, "GP187"),
238 	PINCTRL_PIN(138, "GP188"),
239 	PINCTRL_PIN(139, "GP189"),
240 	PINCTRL_PIN(140, "GP64_FAST_INT0"),
241 	PINCTRL_PIN(141, "GP65_FAST_INT1"),
242 	PINCTRL_PIN(142, "GP66_FAST_INT2"),
243 	PINCTRL_PIN(143, "GP67_FAST_INT3"),
244 	PINCTRL_PIN(144, "GP12_PWM0"),
245 	PINCTRL_PIN(145, "GP13_PWM1"),
246 	/* Family 10: Camera Sideband (12 pins) */
247 	PINCTRL_PIN(146, "GP0"),
248 	PINCTRL_PIN(147, "GP1"),
249 	PINCTRL_PIN(148, "GP2"),
250 	PINCTRL_PIN(149, "GP3"),
251 	PINCTRL_PIN(150, "GP4"),
252 	PINCTRL_PIN(151, "GP5"),
253 	PINCTRL_PIN(152, "GP6"),
254 	PINCTRL_PIN(153, "GP7"),
255 	PINCTRL_PIN(154, "GP8"),
256 	PINCTRL_PIN(155, "GP9"),
257 	PINCTRL_PIN(156, "GP10"),
258 	PINCTRL_PIN(157, "GP11"),
259 	/* Family 11: Clock (22 pins) */
260 	PINCTRL_PIN(158, "GP137"),
261 	PINCTRL_PIN(159, "GP138"),
262 	PINCTRL_PIN(160, "GP139"),
263 	PINCTRL_PIN(161, "GP140"),
264 	PINCTRL_PIN(162, "GP141"),
265 	PINCTRL_PIN(163, "GP142"),
266 	PINCTRL_PIN(164, "GP16_HDMI_HPD"),
267 	PINCTRL_PIN(165, "GP68_DSI_A_TE"),
268 	PINCTRL_PIN(166, "GP69_DSI_C_TE"),
269 	PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
270 	PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
271 	PINCTRL_PIN(169, "OSC_CLK0"),
272 	PINCTRL_PIN(170, "OSC_CLK1"),
273 	PINCTRL_PIN(171, "OSC_CLK2"),
274 	PINCTRL_PIN(172, "OSC_CLK3"),
275 	PINCTRL_PIN(173, "OSC_CLK4"),
276 	PINCTRL_PIN(174, "RESETOUT"),
277 	PINCTRL_PIN(175, "PMODE"),
278 	PINCTRL_PIN(176, "PRDY"),
279 	PINCTRL_PIN(177, "PREQ"),
280 	PINCTRL_PIN(178, "GP190"),
281 	PINCTRL_PIN(179, "GP191"),
282 	/* Family 12: MSIC (15 pins) */
283 	PINCTRL_PIN(180, "I2C_0_SCL"),
284 	PINCTRL_PIN(181, "I2C_0_SDA"),
285 	PINCTRL_PIN(182, "IERR"),
286 	PINCTRL_PIN(183, "JTAG_TCK"),
287 	PINCTRL_PIN(184, "JTAG_TDI"),
288 	PINCTRL_PIN(185, "JTAG_TDO"),
289 	PINCTRL_PIN(186, "JTAG_TMS"),
290 	PINCTRL_PIN(187, "JTAG_TRST"),
291 	PINCTRL_PIN(188, "PROCHOT"),
292 	PINCTRL_PIN(189, "RTC_CLK"),
293 	PINCTRL_PIN(190, "SVID_ALERT"),
294 	PINCTRL_PIN(191, "SVID_CLK"),
295 	PINCTRL_PIN(192, "SVID_D"),
296 	PINCTRL_PIN(193, "THERMTRIP"),
297 	PINCTRL_PIN(194, "STANDBY"),
298 	/* Family 13: Keyboard (20 pins) */
299 	PINCTRL_PIN(195, "GP44"),
300 	PINCTRL_PIN(196, "GP45"),
301 	PINCTRL_PIN(197, "GP46"),
302 	PINCTRL_PIN(198, "GP47"),
303 	PINCTRL_PIN(199, "GP48"),
304 	PINCTRL_PIN(200, "GP49"),
305 	PINCTRL_PIN(201, "GP50"),
306 	PINCTRL_PIN(202, "GP51"),
307 	PINCTRL_PIN(203, "GP52"),
308 	PINCTRL_PIN(204, "GP53"),
309 	PINCTRL_PIN(205, "GP54"),
310 	PINCTRL_PIN(206, "GP55"),
311 	PINCTRL_PIN(207, "GP56"),
312 	PINCTRL_PIN(208, "GP57"),
313 	PINCTRL_PIN(209, "GP58"),
314 	PINCTRL_PIN(210, "GP59"),
315 	PINCTRL_PIN(211, "GP60"),
316 	PINCTRL_PIN(212, "GP61"),
317 	PINCTRL_PIN(213, "GP62"),
318 	PINCTRL_PIN(214, "GP63"),
319 	/* Family 14: GPIO North (13 pins) */
320 	PINCTRL_PIN(215, "GP164"),
321 	PINCTRL_PIN(216, "GP165"),
322 	PINCTRL_PIN(217, "GP166"),
323 	PINCTRL_PIN(218, "GP167"),
324 	PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
325 	PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
326 	PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
327 	PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
328 	PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
329 	PINCTRL_PIN(224, "GP173"),
330 	PINCTRL_PIN(225, "GP174"),
331 	PINCTRL_PIN(226, "GP175"),
332 	PINCTRL_PIN(227, "GP176"),
333 	/* Family 15: PTI (5 pins) */
334 	PINCTRL_PIN(228, "GP72_PTI_CLK"),
335 	PINCTRL_PIN(229, "GP73_PTI_D0"),
336 	PINCTRL_PIN(230, "GP74_PTI_D1"),
337 	PINCTRL_PIN(231, "GP75_PTI_D2"),
338 	PINCTRL_PIN(232, "GP76_PTI_D3"),
339 	/* Family 16: USB3 (0 pins) */
340 	/* Family 17: HSIC (0 pins) */
341 	/* Family 18: Broadcast (0 pins) */
342 };
343 
344 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
345 static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
346 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
347 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
348 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
349 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
350 static const unsigned int mrfld_pwm0_pins[] = { 144 };
351 static const unsigned int mrfld_pwm1_pins[] = { 145 };
352 static const unsigned int mrfld_pwm2_pins[] = { 132 };
353 static const unsigned int mrfld_pwm3_pins[] = { 133 };
354 
355 static const struct intel_pingroup mrfld_groups[] = {
356 	PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
357 	PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
358 	PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
359 	PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
360 	PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
361 	PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
362 	PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
363 	PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
364 	PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
365 	PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
366 };
367 
368 static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
369 static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
370 static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
371 static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
372 static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
373 static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
374 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
375 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
376 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
377 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
378 
379 static const struct intel_function mrfld_functions[] = {
380 	FUNCTION("sdio", mrfld_sdio_groups),
381 	FUNCTION("i2s2", mrfld_i2s2_groups),
382 	FUNCTION("spi5", mrfld_spi5_groups),
383 	FUNCTION("uart0", mrfld_uart0_groups),
384 	FUNCTION("uart1", mrfld_uart1_groups),
385 	FUNCTION("uart2", mrfld_uart2_groups),
386 	FUNCTION("pwm0", mrfld_pwm0_groups),
387 	FUNCTION("pwm1", mrfld_pwm1_groups),
388 	FUNCTION("pwm2", mrfld_pwm2_groups),
389 	FUNCTION("pwm3", mrfld_pwm3_groups),
390 };
391 
392 static const struct mrfld_family mrfld_families[] = {
393 	MRFLD_FAMILY(1, 0, 12),
394 	MRFLD_FAMILY(2, 13, 36),
395 	MRFLD_FAMILY(3, 37, 56),
396 	MRFLD_FAMILY(4, 57, 64),
397 	MRFLD_FAMILY(5, 65, 78),
398 	MRFLD_FAMILY(6, 79, 100),
399 	MRFLD_FAMILY_PROTECTED(7, 101, 114),
400 	MRFLD_FAMILY(8, 115, 126),
401 	MRFLD_FAMILY(9, 127, 145),
402 	MRFLD_FAMILY(10, 146, 157),
403 	MRFLD_FAMILY(11, 158, 179),
404 	MRFLD_FAMILY_PROTECTED(12, 180, 194),
405 	MRFLD_FAMILY(13, 195, 214),
406 	MRFLD_FAMILY(14, 215, 227),
407 	MRFLD_FAMILY(15, 228, 232),
408 };
409 
410 /**
411  * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
412  * @dev: Pointer to the device structure
413  * @lock: Lock to serialize register access
414  * @pctldesc: Pin controller description
415  * @pctldev: Pointer to the pin controller device
416  * @families: Array of families this pinctrl handles
417  * @nfamilies: Number of families in the array
418  * @functions: Array of functions
419  * @nfunctions: Number of functions in the array
420  * @groups: Array of pin groups
421  * @ngroups: Number of groups in the array
422  * @pins: Array of pins this pinctrl controls
423  * @npins: Number of pins in the array
424  */
425 struct mrfld_pinctrl {
426 	struct device *dev;
427 	raw_spinlock_t lock;
428 	struct pinctrl_desc pctldesc;
429 	struct pinctrl_dev *pctldev;
430 
431 	/* Pin controller configuration */
432 	const struct mrfld_family *families;
433 	size_t nfamilies;
434 	const struct intel_function *functions;
435 	size_t nfunctions;
436 	const struct intel_pingroup *groups;
437 	size_t ngroups;
438 	const struct pinctrl_pin_desc *pins;
439 	size_t npins;
440 };
441 
442 #define pin_to_bufno(f, p)		((p) - (f)->pin_base)
443 
444 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
445 						   unsigned int pin)
446 {
447 	const struct mrfld_family *family;
448 	unsigned int i;
449 
450 	for (i = 0; i < mp->nfamilies; i++) {
451 		family = &mp->families[i];
452 		if (pin >= family->pin_base &&
453 		    pin < family->pin_base + family->npins)
454 			return family;
455 	}
456 
457 	dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
458 	return NULL;
459 }
460 
461 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
462 {
463 	const struct mrfld_family *family;
464 
465 	family = mrfld_get_family(mp, pin);
466 	if (!family)
467 		return false;
468 
469 	return !family->protected;
470 }
471 
472 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
473 {
474 	const struct mrfld_family *family;
475 	unsigned int bufno;
476 
477 	family = mrfld_get_family(mp, pin);
478 	if (!family)
479 		return NULL;
480 
481 	bufno = pin_to_bufno(family, pin);
482 	return family->regs + BUFCFG_OFFSET + bufno * 4;
483 }
484 
485 static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
486 {
487 	void __iomem *bufcfg;
488 
489 	if (!mrfld_buf_available(mp, pin))
490 		return -EBUSY;
491 
492 	bufcfg = mrfld_get_bufcfg(mp, pin);
493 	*value = readl(bufcfg);
494 
495 	return 0;
496 }
497 
498 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
499 				u32 bits, u32 mask)
500 {
501 	void __iomem *bufcfg;
502 	u32 value;
503 
504 	bufcfg = mrfld_get_bufcfg(mp, pin);
505 	value = readl(bufcfg);
506 
507 	value &= ~mask;
508 	value |= bits & mask;
509 
510 	writel(value, bufcfg);
511 }
512 
513 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
514 {
515 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
516 
517 	return mp->ngroups;
518 }
519 
520 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
521 					unsigned int group)
522 {
523 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
524 
525 	return mp->groups[group].grp.name;
526 }
527 
528 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
529 				const unsigned int **pins, unsigned int *npins)
530 {
531 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
532 
533 	*pins = mp->groups[group].grp.pins;
534 	*npins = mp->groups[group].grp.npins;
535 	return 0;
536 }
537 
538 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
539 			       unsigned int pin)
540 {
541 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
542 	u32 value, mode;
543 	int ret;
544 
545 	ret = mrfld_read_bufcfg(mp, pin, &value);
546 	if (ret) {
547 		seq_puts(s, "not available");
548 		return;
549 	}
550 
551 	mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
552 	if (mode == BUFCFG_PINMODE_GPIO)
553 		seq_puts(s, "GPIO ");
554 	else
555 		seq_printf(s, "mode %d ", mode);
556 
557 	seq_printf(s, "0x%08x", value);
558 }
559 
560 static const struct pinctrl_ops mrfld_pinctrl_ops = {
561 	.get_groups_count = mrfld_get_groups_count,
562 	.get_group_name = mrfld_get_group_name,
563 	.get_group_pins = mrfld_get_group_pins,
564 	.pin_dbg_show = mrfld_pin_dbg_show,
565 };
566 
567 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
568 {
569 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
570 
571 	return mp->nfunctions;
572 }
573 
574 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
575 					   unsigned int function)
576 {
577 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
578 
579 	return mp->functions[function].func.name;
580 }
581 
582 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
583 				     unsigned int function,
584 				     const char * const **groups,
585 				     unsigned int * const ngroups)
586 {
587 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
588 
589 	*groups = mp->functions[function].func.groups;
590 	*ngroups = mp->functions[function].func.ngroups;
591 	return 0;
592 }
593 
594 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
595 				unsigned int function,
596 				unsigned int group)
597 {
598 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
599 	const struct intel_pingroup *grp = &mp->groups[group];
600 	u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
601 	u32 mask = BUFCFG_PINMODE_MASK;
602 	unsigned long flags;
603 	unsigned int i;
604 
605 	/*
606 	 * All pins in the groups needs to be accessible and writable
607 	 * before we can enable the mux for this group.
608 	 */
609 	for (i = 0; i < grp->grp.npins; i++) {
610 		if (!mrfld_buf_available(mp, grp->grp.pins[i]))
611 			return -EBUSY;
612 	}
613 
614 	/* Now enable the mux setting for each pin in the group */
615 	raw_spin_lock_irqsave(&mp->lock, flags);
616 	for (i = 0; i < grp->grp.npins; i++)
617 		mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
618 	raw_spin_unlock_irqrestore(&mp->lock, flags);
619 
620 	return 0;
621 }
622 
623 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
624 				     struct pinctrl_gpio_range *range,
625 				     unsigned int pin)
626 {
627 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
628 	u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
629 	u32 mask = BUFCFG_PINMODE_MASK;
630 	unsigned long flags;
631 
632 	if (!mrfld_buf_available(mp, pin))
633 		return -EBUSY;
634 
635 	raw_spin_lock_irqsave(&mp->lock, flags);
636 	mrfld_update_bufcfg(mp, pin, bits, mask);
637 	raw_spin_unlock_irqrestore(&mp->lock, flags);
638 
639 	return 0;
640 }
641 
642 static const struct pinmux_ops mrfld_pinmux_ops = {
643 	.get_functions_count = mrfld_get_functions_count,
644 	.get_function_name = mrfld_get_function_name,
645 	.get_function_groups = mrfld_get_function_groups,
646 	.set_mux = mrfld_pinmux_set_mux,
647 	.gpio_request_enable = mrfld_gpio_request_enable,
648 };
649 
650 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
651 			    unsigned long *config)
652 {
653 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
654 	enum pin_config_param param = pinconf_to_config_param(*config);
655 	u32 value, term;
656 	u16 arg = 0;
657 	int ret;
658 
659 	ret = mrfld_read_bufcfg(mp, pin, &value);
660 	if (ret)
661 		return -ENOTSUPP;
662 
663 	term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
664 
665 	switch (param) {
666 	case PIN_CONFIG_BIAS_DISABLE:
667 		if (value & BUFCFG_Px_EN_MASK)
668 			return -EINVAL;
669 		break;
670 
671 	case PIN_CONFIG_BIAS_PULL_UP:
672 		if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
673 			return -EINVAL;
674 
675 		switch (term) {
676 		case BUFCFG_PUPD_VAL_910:
677 			arg = 910;
678 			break;
679 		case BUFCFG_PUPD_VAL_2K:
680 			arg = 2000;
681 			break;
682 		case BUFCFG_PUPD_VAL_20K:
683 			arg = 20000;
684 			break;
685 		case BUFCFG_PUPD_VAL_50K:
686 			arg = 50000;
687 			break;
688 		}
689 
690 		break;
691 
692 	case PIN_CONFIG_BIAS_PULL_DOWN:
693 		if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
694 			return -EINVAL;
695 
696 		switch (term) {
697 		case BUFCFG_PUPD_VAL_910:
698 			arg = 910;
699 			break;
700 		case BUFCFG_PUPD_VAL_2K:
701 			arg = 2000;
702 			break;
703 		case BUFCFG_PUPD_VAL_20K:
704 			arg = 20000;
705 			break;
706 		case BUFCFG_PUPD_VAL_50K:
707 			arg = 50000;
708 			break;
709 		}
710 
711 		break;
712 
713 	case PIN_CONFIG_DRIVE_PUSH_PULL:
714 		if (value & BUFCFG_OD_EN)
715 			return -EINVAL;
716 		break;
717 
718 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
719 		if (!(value & BUFCFG_OD_EN))
720 			return -EINVAL;
721 		break;
722 
723 	case PIN_CONFIG_SLEW_RATE:
724 		if (!(value & BUFCFG_SLEWSEL))
725 			arg = 0;
726 		else
727 			arg = 1;
728 		break;
729 
730 	default:
731 		return -ENOTSUPP;
732 	}
733 
734 	*config = pinconf_to_config_packed(param, arg);
735 	return 0;
736 }
737 
738 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
739 				unsigned long config)
740 {
741 	unsigned int param = pinconf_to_config_param(config);
742 	unsigned int arg = pinconf_to_config_argument(config);
743 	u32 bits = 0, mask = 0;
744 	unsigned long flags;
745 
746 	switch (param) {
747 	case PIN_CONFIG_BIAS_DISABLE:
748 		mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
749 		break;
750 
751 	case PIN_CONFIG_BIAS_PULL_UP:
752 		mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
753 		bits |= BUFCFG_PU_EN;
754 
755 		/* Set default strength value in case none is given */
756 		if (arg == 1)
757 			arg = 20000;
758 
759 		switch (arg) {
760 		case 50000:
761 			bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
762 			break;
763 		case 20000:
764 			bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
765 			break;
766 		case 2000:
767 			bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
768 			break;
769 		default:
770 			return -EINVAL;
771 		}
772 
773 		break;
774 
775 	case PIN_CONFIG_BIAS_PULL_DOWN:
776 		mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
777 		bits |= BUFCFG_PD_EN;
778 
779 		/* Set default strength value in case none is given */
780 		if (arg == 1)
781 			arg = 20000;
782 
783 		switch (arg) {
784 		case 50000:
785 			bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
786 			break;
787 		case 20000:
788 			bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
789 			break;
790 		case 2000:
791 			bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
792 			break;
793 		default:
794 			return -EINVAL;
795 		}
796 
797 		break;
798 
799 	case PIN_CONFIG_DRIVE_PUSH_PULL:
800 		mask |= BUFCFG_OD_EN;
801 		bits &= ~BUFCFG_OD_EN;
802 		break;
803 
804 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
805 		mask |= BUFCFG_OD_EN;
806 		bits |= BUFCFG_OD_EN;
807 		break;
808 
809 	case PIN_CONFIG_SLEW_RATE:
810 		mask |= BUFCFG_SLEWSEL;
811 		if (arg)
812 			bits |= BUFCFG_SLEWSEL;
813 		break;
814 	}
815 
816 	raw_spin_lock_irqsave(&mp->lock, flags);
817 	mrfld_update_bufcfg(mp, pin, bits, mask);
818 	raw_spin_unlock_irqrestore(&mp->lock, flags);
819 
820 	return 0;
821 }
822 
823 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
824 			    unsigned long *configs, unsigned int nconfigs)
825 {
826 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
827 	unsigned int i;
828 	int ret;
829 
830 	if (!mrfld_buf_available(mp, pin))
831 		return -ENOTSUPP;
832 
833 	for (i = 0; i < nconfigs; i++) {
834 		switch (pinconf_to_config_param(configs[i])) {
835 		case PIN_CONFIG_BIAS_DISABLE:
836 		case PIN_CONFIG_BIAS_PULL_UP:
837 		case PIN_CONFIG_BIAS_PULL_DOWN:
838 		case PIN_CONFIG_DRIVE_PUSH_PULL:
839 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
840 		case PIN_CONFIG_SLEW_RATE:
841 			ret = mrfld_config_set_pin(mp, pin, configs[i]);
842 			if (ret)
843 				return ret;
844 			break;
845 
846 		default:
847 			return -ENOTSUPP;
848 		}
849 	}
850 
851 	return 0;
852 }
853 
854 static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
855 				  unsigned int group, unsigned long *config)
856 {
857 	const unsigned int *pins;
858 	unsigned int npins;
859 	int ret;
860 
861 	ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
862 	if (ret)
863 		return ret;
864 
865 	ret = mrfld_config_get(pctldev, pins[0], config);
866 	if (ret)
867 		return ret;
868 
869 	return 0;
870 }
871 
872 static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
873 				  unsigned int group, unsigned long *configs,
874 				  unsigned int num_configs)
875 {
876 	const unsigned int *pins;
877 	unsigned int npins;
878 	int i, ret;
879 
880 	ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
881 	if (ret)
882 		return ret;
883 
884 	for (i = 0; i < npins; i++) {
885 		ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
886 		if (ret)
887 			return ret;
888 	}
889 
890 	return 0;
891 }
892 
893 static const struct pinconf_ops mrfld_pinconf_ops = {
894 	.is_generic = true,
895 	.pin_config_get = mrfld_config_get,
896 	.pin_config_set = mrfld_config_set,
897 	.pin_config_group_get = mrfld_config_group_get,
898 	.pin_config_group_set = mrfld_config_group_set,
899 };
900 
901 static const struct pinctrl_desc mrfld_pinctrl_desc = {
902 	.pctlops = &mrfld_pinctrl_ops,
903 	.pmxops = &mrfld_pinmux_ops,
904 	.confops = &mrfld_pinconf_ops,
905 	.owner = THIS_MODULE,
906 };
907 
908 static int mrfld_pinctrl_probe(struct platform_device *pdev)
909 {
910 	struct device *dev = &pdev->dev;
911 	struct mrfld_family *families;
912 	struct mrfld_pinctrl *mp;
913 	void __iomem *regs;
914 	size_t nfamilies;
915 	unsigned int i;
916 
917 	mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
918 	if (!mp)
919 		return -ENOMEM;
920 
921 	mp->dev = dev;
922 	raw_spin_lock_init(&mp->lock);
923 
924 	regs = devm_platform_ioremap_resource(pdev, 0);
925 	if (IS_ERR(regs))
926 		return PTR_ERR(regs);
927 
928 	/*
929 	 * Make a copy of the families which we can use to hold pointers
930 	 * to the registers.
931 	 */
932 	nfamilies = ARRAY_SIZE(mrfld_families),
933 	families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL);
934 	if (!families)
935 		return -ENOMEM;
936 
937 	/* Splice memory resource by chunk per family */
938 	for (i = 0; i < nfamilies; i++) {
939 		struct mrfld_family *family = &families[i];
940 
941 		family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
942 	}
943 
944 	mp->families = families;
945 	mp->nfamilies = nfamilies;
946 	mp->functions = mrfld_functions;
947 	mp->nfunctions = ARRAY_SIZE(mrfld_functions);
948 	mp->groups = mrfld_groups;
949 	mp->ngroups = ARRAY_SIZE(mrfld_groups);
950 	mp->pctldesc = mrfld_pinctrl_desc;
951 	mp->pctldesc.name = dev_name(dev);
952 	mp->pctldesc.pins = mrfld_pins;
953 	mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
954 
955 	mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
956 	if (IS_ERR(mp->pctldev)) {
957 		dev_err(dev, "failed to register pinctrl driver\n");
958 		return PTR_ERR(mp->pctldev);
959 	}
960 
961 	platform_set_drvdata(pdev, mp);
962 	return 0;
963 }
964 
965 static const struct acpi_device_id mrfld_acpi_table[] = {
966 	{ "INTC1002" },
967 	{ }
968 };
969 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
970 
971 static struct platform_driver mrfld_pinctrl_driver = {
972 	.probe = mrfld_pinctrl_probe,
973 	.driver = {
974 		.name = "pinctrl-merrifield",
975 		.acpi_match_table = mrfld_acpi_table,
976 	},
977 };
978 
979 static int __init mrfld_pinctrl_init(void)
980 {
981 	return platform_driver_register(&mrfld_pinctrl_driver);
982 }
983 subsys_initcall(mrfld_pinctrl_init);
984 
985 static void __exit mrfld_pinctrl_exit(void)
986 {
987 	platform_driver_unregister(&mrfld_pinctrl_driver);
988 }
989 module_exit(mrfld_pinctrl_exit);
990 
991 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
992 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
993 MODULE_LICENSE("GPL v2");
994 MODULE_ALIAS("platform:pinctrl-merrifield");
995