1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO controller driver for Intel Lynxpoint PCH chipset> 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 /* LynxPoint chipset has support for 94 gpio pins */ 22 23 #define LP_NUM_GPIO 94 24 25 /* Bitmapped register offsets */ 26 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 27 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 28 #define LP_INT_STAT 0x80 29 #define LP_INT_ENABLE 0x90 30 31 /* Each pin has two 32 bit config registers, starting at 0x100 */ 32 #define LP_CONFIG1 0x100 33 #define LP_CONFIG2 0x104 34 35 /* LP_CONFIG1 reg bits */ 36 #define OUT_LVL_BIT BIT(31) 37 #define IN_LVL_BIT BIT(30) 38 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 39 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 40 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 41 #define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */ 42 43 /* LP_CONFIG2 reg bits */ 44 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 45 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ 46 47 struct lp_gpio { 48 struct gpio_chip chip; 49 struct platform_device *pdev; 50 raw_spinlock_t lock; 51 unsigned long reg_base; 52 }; 53 54 /* 55 * Lynxpoint gpios are controlled through both bitmapped registers and 56 * per gpio specific registers. The bitmapped registers are in chunks of 57 * 3 x 32bit registers to cover all 94 gpios 58 * 59 * per gpio specific registers consist of two 32bit registers per gpio 60 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of 61 * 188 config registers. 62 * 63 * A simplified view of the register layout look like this: 64 * 65 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 66 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 67 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 68 * ... 69 * LP_INT_ENABLE[31:0] ... 70 * LP_INT_ENABLE[63:31] ... 71 * LP_INT_ENABLE[94:64] ... 72 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 73 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 74 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 75 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 76 * LP2_CONFIG1 (gpio 2) ... 77 * LP2_CONFIG2 (gpio 2) ... 78 * ... 79 * LP94_CONFIG1 (gpio 94) ... 80 * LP94_CONFIG2 (gpio 94) ... 81 */ 82 83 static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset, 84 int reg) 85 { 86 struct lp_gpio *lg = gpiochip_get_data(chip); 87 int reg_offset; 88 89 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 90 /* per gpio specific config registers */ 91 reg_offset = offset * 8; 92 else 93 /* bitmapped registers */ 94 reg_offset = (offset / 32) * 4; 95 96 return lg->reg_base + reg + reg_offset; 97 } 98 99 static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) 100 { 101 struct lp_gpio *lg = gpiochip_get_data(chip); 102 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 103 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 104 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); 105 106 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */ 107 108 /* Fail if BIOS reserved pin for ACPI use */ 109 if (!(inl(acpi_use) & BIT(offset % 32))) { 110 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset); 111 return -EBUSY; 112 } 113 /* Fail if pin is in alternate function mode (not GPIO mode) */ 114 if (!(inl(reg) & USE_SEL_BIT)) 115 return -ENODEV; 116 117 /* enable input sensing */ 118 outl(inl(conf2) & ~GPINDIS_BIT, conf2); 119 120 121 return 0; 122 } 123 124 static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) 125 { 126 struct lp_gpio *lg = gpiochip_get_data(chip); 127 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 128 129 /* disable input sensing */ 130 outl(inl(conf2) | GPINDIS_BIT, conf2); 131 132 pm_runtime_put(&lg->pdev->dev); 133 } 134 135 static int lp_irq_type(struct irq_data *d, unsigned type) 136 { 137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 138 struct lp_gpio *lg = gpiochip_get_data(gc); 139 u32 hwirq = irqd_to_hwirq(d); 140 unsigned long flags; 141 u32 value; 142 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 143 144 if (hwirq >= lg->chip.ngpio) 145 return -EINVAL; 146 147 raw_spin_lock_irqsave(&lg->lock, flags); 148 value = inl(reg); 149 150 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 151 if (type & IRQ_TYPE_EDGE_RISING) 152 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 153 154 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 155 if (type & IRQ_TYPE_EDGE_FALLING) 156 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 157 158 /* TRIG_SEL bit 1, INV bit 0 for level low */ 159 if (type & IRQ_TYPE_LEVEL_LOW) 160 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 161 162 /* TRIG_SEL bit 1, INV bit 1 for level high */ 163 if (type & IRQ_TYPE_LEVEL_HIGH) 164 value |= TRIG_SEL_BIT | INT_INV_BIT; 165 166 outl(value, reg); 167 168 if (type & IRQ_TYPE_EDGE_BOTH) 169 irq_set_handler_locked(d, handle_edge_irq); 170 else if (type & IRQ_TYPE_LEVEL_MASK) 171 irq_set_handler_locked(d, handle_level_irq); 172 173 raw_spin_unlock_irqrestore(&lg->lock, flags); 174 175 return 0; 176 } 177 178 static int lp_gpio_get(struct gpio_chip *chip, unsigned offset) 179 { 180 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 181 return !!(inl(reg) & IN_LVL_BIT); 182 } 183 184 static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 185 { 186 struct lp_gpio *lg = gpiochip_get_data(chip); 187 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 188 unsigned long flags; 189 190 raw_spin_lock_irqsave(&lg->lock, flags); 191 192 if (value) 193 outl(inl(reg) | OUT_LVL_BIT, reg); 194 else 195 outl(inl(reg) & ~OUT_LVL_BIT, reg); 196 197 raw_spin_unlock_irqrestore(&lg->lock, flags); 198 } 199 200 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 201 { 202 struct lp_gpio *lg = gpiochip_get_data(chip); 203 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 204 unsigned long flags; 205 206 raw_spin_lock_irqsave(&lg->lock, flags); 207 outl(inl(reg) | DIR_BIT, reg); 208 raw_spin_unlock_irqrestore(&lg->lock, flags); 209 210 return 0; 211 } 212 213 static int lp_gpio_direction_output(struct gpio_chip *chip, 214 unsigned offset, int value) 215 { 216 struct lp_gpio *lg = gpiochip_get_data(chip); 217 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 218 unsigned long flags; 219 220 lp_gpio_set(chip, offset, value); 221 222 raw_spin_lock_irqsave(&lg->lock, flags); 223 outl(inl(reg) & ~DIR_BIT, reg); 224 raw_spin_unlock_irqrestore(&lg->lock, flags); 225 226 return 0; 227 } 228 229 static void lp_gpio_irq_handler(struct irq_desc *desc) 230 { 231 struct irq_data *data = irq_desc_get_irq_data(desc); 232 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 233 struct lp_gpio *lg = gpiochip_get_data(gc); 234 struct irq_chip *chip = irq_data_get_irq_chip(data); 235 unsigned long reg, ena, pending; 236 u32 base, pin; 237 238 /* check from GPIO controller which pin triggered the interrupt */ 239 for (base = 0; base < lg->chip.ngpio; base += 32) { 240 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 241 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 242 243 /* Only interrupts that are enabled */ 244 pending = inl(reg) & inl(ena); 245 246 for_each_set_bit(pin, &pending, 32) { 247 unsigned irq; 248 249 /* Clear before handling so we don't lose an edge */ 250 outl(BIT(pin), reg); 251 252 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 253 generic_handle_irq(irq); 254 } 255 } 256 chip->irq_eoi(data); 257 } 258 259 static void lp_irq_unmask(struct irq_data *d) 260 { 261 } 262 263 static void lp_irq_mask(struct irq_data *d) 264 { 265 } 266 267 static void lp_irq_enable(struct irq_data *d) 268 { 269 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 270 struct lp_gpio *lg = gpiochip_get_data(gc); 271 u32 hwirq = irqd_to_hwirq(d); 272 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 273 unsigned long flags; 274 275 raw_spin_lock_irqsave(&lg->lock, flags); 276 outl(inl(reg) | BIT(hwirq % 32), reg); 277 raw_spin_unlock_irqrestore(&lg->lock, flags); 278 } 279 280 static void lp_irq_disable(struct irq_data *d) 281 { 282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 283 struct lp_gpio *lg = gpiochip_get_data(gc); 284 u32 hwirq = irqd_to_hwirq(d); 285 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 286 unsigned long flags; 287 288 raw_spin_lock_irqsave(&lg->lock, flags); 289 outl(inl(reg) & ~BIT(hwirq % 32), reg); 290 raw_spin_unlock_irqrestore(&lg->lock, flags); 291 } 292 293 static struct irq_chip lp_irqchip = { 294 .name = "LP-GPIO", 295 .irq_mask = lp_irq_mask, 296 .irq_unmask = lp_irq_unmask, 297 .irq_enable = lp_irq_enable, 298 .irq_disable = lp_irq_disable, 299 .irq_set_type = lp_irq_type, 300 .flags = IRQCHIP_SKIP_SET_WAKE, 301 }; 302 303 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 304 { 305 struct lp_gpio *lg = gpiochip_get_data(chip); 306 unsigned long reg; 307 unsigned base; 308 309 for (base = 0; base < lg->chip.ngpio; base += 32) { 310 /* disable gpio pin interrupts */ 311 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 312 outl(0, reg); 313 /* Clear interrupt status register */ 314 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 315 outl(0xffffffff, reg); 316 } 317 318 return 0; 319 } 320 321 static int lp_gpio_probe(struct platform_device *pdev) 322 { 323 struct lp_gpio *lg; 324 struct gpio_chip *gc; 325 struct resource *io_rc, *irq_rc; 326 struct device *dev = &pdev->dev; 327 unsigned long reg_len; 328 int ret = -ENODEV; 329 330 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL); 331 if (!lg) 332 return -ENOMEM; 333 334 lg->pdev = pdev; 335 platform_set_drvdata(pdev, lg); 336 337 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 338 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 339 340 if (!io_rc) { 341 dev_err(dev, "missing IO resources\n"); 342 return -EINVAL; 343 } 344 345 lg->reg_base = io_rc->start; 346 reg_len = resource_size(io_rc); 347 348 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { 349 dev_err(dev, "failed requesting IO region 0x%x\n", 350 (unsigned int)lg->reg_base); 351 return -EBUSY; 352 } 353 354 raw_spin_lock_init(&lg->lock); 355 356 gc = &lg->chip; 357 gc->label = dev_name(dev); 358 gc->owner = THIS_MODULE; 359 gc->request = lp_gpio_request; 360 gc->free = lp_gpio_free; 361 gc->direction_input = lp_gpio_direction_input; 362 gc->direction_output = lp_gpio_direction_output; 363 gc->get = lp_gpio_get; 364 gc->set = lp_gpio_set; 365 gc->base = -1; 366 gc->ngpio = LP_NUM_GPIO; 367 gc->can_sleep = false; 368 gc->parent = dev; 369 370 /* set up interrupts */ 371 if (irq_rc && irq_rc->start) { 372 struct gpio_irq_chip *girq; 373 374 girq = &gc->irq; 375 girq->chip = &lp_irqchip; 376 girq->init_hw = lp_gpio_irq_init_hw; 377 girq->parent_handler = lp_gpio_irq_handler; 378 girq->num_parents = 1; 379 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, 380 sizeof(*girq->parents), 381 GFP_KERNEL); 382 if (!girq->parents) 383 return -ENOMEM; 384 girq->parents[0] = (unsigned)irq_rc->start; 385 girq->default_type = IRQ_TYPE_NONE; 386 girq->handler = handle_bad_irq; 387 } 388 389 ret = devm_gpiochip_add_data(dev, gc, lg); 390 if (ret) { 391 dev_err(dev, "failed adding lp-gpio chip\n"); 392 return ret; 393 } 394 395 pm_runtime_enable(dev); 396 397 return 0; 398 } 399 400 static int lp_gpio_runtime_suspend(struct device *dev) 401 { 402 return 0; 403 } 404 405 static int lp_gpio_runtime_resume(struct device *dev) 406 { 407 return 0; 408 } 409 410 static int lp_gpio_resume(struct device *dev) 411 { 412 struct lp_gpio *lg = dev_get_drvdata(dev); 413 unsigned long reg; 414 int i; 415 416 /* on some hardware suspend clears input sensing, re-enable it here */ 417 for (i = 0; i < lg->chip.ngpio; i++) { 418 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 419 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 420 outl(inl(reg) & ~GPINDIS_BIT, reg); 421 } 422 } 423 return 0; 424 } 425 426 static const struct dev_pm_ops lp_gpio_pm_ops = { 427 .runtime_suspend = lp_gpio_runtime_suspend, 428 .runtime_resume = lp_gpio_runtime_resume, 429 .resume = lp_gpio_resume, 430 }; 431 432 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 433 { "INT33C7", 0 }, 434 { "INT3437", 0 }, 435 { } 436 }; 437 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 438 439 static int lp_gpio_remove(struct platform_device *pdev) 440 { 441 pm_runtime_disable(&pdev->dev); 442 return 0; 443 } 444 445 static struct platform_driver lp_gpio_driver = { 446 .probe = lp_gpio_probe, 447 .remove = lp_gpio_remove, 448 .driver = { 449 .name = "lp_gpio", 450 .pm = &lp_gpio_pm_ops, 451 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 452 }, 453 }; 454 455 static int __init lp_gpio_init(void) 456 { 457 return platform_driver_register(&lp_gpio_driver); 458 } 459 460 static void __exit lp_gpio_exit(void) 461 { 462 platform_driver_unregister(&lp_gpio_driver); 463 } 464 465 subsys_initcall(lp_gpio_init); 466 module_exit(lp_gpio_exit); 467 468 MODULE_AUTHOR("Mathias Nyman (Intel)"); 469 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); 470 MODULE_LICENSE("GPL v2"); 471 MODULE_ALIAS("platform:lp_gpio"); 472