1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO controller driver for Intel Lynxpoint PCH chipset> 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 26 #include "pinctrl-intel.h" 27 28 #define COMMUNITY(p, n) \ 29 { \ 30 .pin_base = (p), \ 31 .npins = (n), \ 32 } 33 34 static const struct pinctrl_pin_desc lptlp_pins[] = { 35 PINCTRL_PIN(0, "GP0_UART1_RXD"), 36 PINCTRL_PIN(1, "GP1_UART1_TXD"), 37 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 38 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 39 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 40 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 41 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 42 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 43 PINCTRL_PIN(8, "GP8"), 44 PINCTRL_PIN(9, "GP9"), 45 PINCTRL_PIN(10, "GP10"), 46 PINCTRL_PIN(11, "GP11_SMBALERTB"), 47 PINCTRL_PIN(12, "GP12_LANPHYPC"), 48 PINCTRL_PIN(13, "GP13"), 49 PINCTRL_PIN(14, "GP14"), 50 PINCTRL_PIN(15, "GP15"), 51 PINCTRL_PIN(16, "GP16_MGPIO9"), 52 PINCTRL_PIN(17, "GP17_MGPIO10"), 53 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 54 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 55 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 56 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 57 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 58 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 59 PINCTRL_PIN(24, "GP24_MGPIO0"), 60 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 61 PINCTRL_PIN(26, "GP26_MGPIO5"), 62 PINCTRL_PIN(27, "GP27_MGPIO6"), 63 PINCTRL_PIN(28, "GP28_MGPIO7"), 64 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 65 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 66 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 67 PINCTRL_PIN(32, "GP32_CLKRUNB"), 68 PINCTRL_PIN(33, "GP33_DEVSLP0"), 69 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 70 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 71 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 72 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 73 PINCTRL_PIN(38, "GP38_DEVSLP1"), 74 PINCTRL_PIN(39, "GP39_DEVSLP2"), 75 PINCTRL_PIN(40, "GP40_OC0B"), 76 PINCTRL_PIN(41, "GP41_OC1B"), 77 PINCTRL_PIN(42, "GP42_OC2B"), 78 PINCTRL_PIN(43, "GP43_OC3B"), 79 PINCTRL_PIN(44, "GP44"), 80 PINCTRL_PIN(45, "GP45_TMS2"), 81 PINCTRL_PIN(46, "GP46_TDO2"), 82 PINCTRL_PIN(47, "GP47"), 83 PINCTRL_PIN(48, "GP48"), 84 PINCTRL_PIN(49, "GP49"), 85 PINCTRL_PIN(50, "GP50"), 86 PINCTRL_PIN(51, "GP51_GSXDOUT"), 87 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 88 PINCTRL_PIN(53, "GP53_GSXDIN"), 89 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 90 PINCTRL_PIN(55, "GP55_GSXCLK"), 91 PINCTRL_PIN(56, "GP56"), 92 PINCTRL_PIN(57, "GP57"), 93 PINCTRL_PIN(58, "GP58"), 94 PINCTRL_PIN(59, "GP59"), 95 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 96 PINCTRL_PIN(61, "GP61_SUS_STATB"), 97 PINCTRL_PIN(62, "GP62_SUSCLK"), 98 PINCTRL_PIN(63, "GP63_SLP_S5B"), 99 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 100 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 101 PINCTRL_PIN(66, "GP66_SDIO_D0"), 102 PINCTRL_PIN(67, "GP67_SDIO_D1"), 103 PINCTRL_PIN(68, "GP68_SDIO_D2"), 104 PINCTRL_PIN(69, "GP69_SDIO_D3"), 105 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 106 PINCTRL_PIN(71, "GP71_MPHYPC"), 107 PINCTRL_PIN(72, "GP72_BATLOWB"), 108 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 109 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 110 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 111 PINCTRL_PIN(76, "GP76_BMBUSYB"), 112 PINCTRL_PIN(77, "GP77_PIRQAB"), 113 PINCTRL_PIN(78, "GP78_PIRQBB"), 114 PINCTRL_PIN(79, "GP79_PIRQCB"), 115 PINCTRL_PIN(80, "GP80_PIRQDB"), 116 PINCTRL_PIN(81, "GP81_SPKR"), 117 PINCTRL_PIN(82, "GP82_RCINB"), 118 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 119 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 120 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 121 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 122 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 123 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 124 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 125 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 126 PINCTRL_PIN(91, "GP91_UART0_RXD"), 127 PINCTRL_PIN(92, "GP92_UART0_TXD"), 128 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 129 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 130 }; 131 132 static const struct intel_community lptlp_communities[] = { 133 COMMUNITY(0, 95), 134 }; 135 136 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 137 .pins = lptlp_pins, 138 .npins = ARRAY_SIZE(lptlp_pins), 139 .communities = lptlp_communities, 140 .ncommunities = ARRAY_SIZE(lptlp_communities), 141 }; 142 143 /* LynxPoint chipset has support for 95 GPIO pins */ 144 145 #define LP_NUM_GPIO 95 146 147 /* Bitmapped register offsets */ 148 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 149 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 150 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 151 #define LP_INT_STAT 0x80 152 #define LP_INT_ENABLE 0x90 153 154 /* Each pin has two 32 bit config registers, starting at 0x100 */ 155 #define LP_CONFIG1 0x100 156 #define LP_CONFIG2 0x104 157 158 /* LP_CONFIG1 reg bits */ 159 #define OUT_LVL_BIT BIT(31) 160 #define IN_LVL_BIT BIT(30) 161 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 162 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 163 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 164 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 165 #define USE_SEL_NATIVE (0 << 0) 166 #define USE_SEL_GPIO (1 << 0) 167 168 /* LP_CONFIG2 reg bits */ 169 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 170 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 171 #define GPIWP_NONE 0 /* none */ 172 #define GPIWP_DOWN 1 /* weak pull down */ 173 #define GPIWP_UP 2 /* weak pull up */ 174 175 /* 176 * Lynxpoint gpios are controlled through both bitmapped registers and 177 * per gpio specific registers. The bitmapped registers are in chunks of 178 * 3 x 32bit registers to cover all 95 GPIOs 179 * 180 * per gpio specific registers consist of two 32bit registers per gpio 181 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 182 * 190 config registers. 183 * 184 * A simplified view of the register layout look like this: 185 * 186 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 187 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 188 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 189 * ... 190 * LP_INT_ENABLE[31:0] ... 191 * LP_INT_ENABLE[63:32] ... 192 * LP_INT_ENABLE[94:64] ... 193 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 194 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 195 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 196 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 197 * LP2_CONFIG1 (gpio 2) ... 198 * LP2_CONFIG2 (gpio 2) ... 199 * ... 200 * LP94_CONFIG1 (gpio 94) ... 201 * LP94_CONFIG2 (gpio 94) ... 202 * 203 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 204 */ 205 206 static struct intel_community *lp_get_community(struct intel_pinctrl *lg, 207 unsigned int pin) 208 { 209 struct intel_community *comm; 210 int i; 211 212 for (i = 0; i < lg->ncommunities; i++) { 213 comm = &lg->communities[i]; 214 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 215 return comm; 216 } 217 218 return NULL; 219 } 220 221 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 222 int reg) 223 { 224 struct intel_pinctrl *lg = gpiochip_get_data(chip); 225 struct intel_community *comm; 226 int reg_offset; 227 228 comm = lp_get_community(lg, offset); 229 if (!comm) 230 return NULL; 231 232 offset -= comm->pin_base; 233 234 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 235 /* per gpio specific config registers */ 236 reg_offset = offset * 8; 237 else 238 /* bitmapped registers */ 239 reg_offset = (offset / 32) * 4; 240 241 return comm->regs + reg_offset + reg; 242 } 243 244 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 245 { 246 void __iomem *acpi_use; 247 248 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 249 if (!acpi_use) 250 return true; 251 252 return !(ioread32(acpi_use) & BIT(pin % 32)); 253 } 254 255 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 256 { 257 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 258 u32 value; 259 260 value = ioread32(ioxapic_use); 261 262 if (offset >= 8 && offset <= 10) 263 return !!(value & BIT(offset - 8 + 0)); 264 if (offset >= 13 && offset <= 14) 265 return !!(value & BIT(offset - 13 + 3)); 266 if (offset >= 45 && offset <= 55) 267 return !!(value & BIT(offset - 45 + 5)); 268 269 return false; 270 } 271 272 static int lp_get_groups_count(struct pinctrl_dev *pctldev) 273 { 274 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 275 276 return lg->soc->ngroups; 277 } 278 279 static const char *lp_get_group_name(struct pinctrl_dev *pctldev, 280 unsigned int selector) 281 { 282 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 283 284 return lg->soc->groups[selector].name; 285 } 286 287 static int lp_get_group_pins(struct pinctrl_dev *pctldev, 288 unsigned int selector, 289 const unsigned int **pins, 290 unsigned int *num_pins) 291 { 292 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 293 294 *pins = lg->soc->groups[selector].pins; 295 *num_pins = lg->soc->groups[selector].npins; 296 297 return 0; 298 } 299 300 static const struct pinctrl_ops lptlp_pinctrl_ops = { 301 .get_groups_count = lp_get_groups_count, 302 .get_group_name = lp_get_group_name, 303 .get_group_pins = lp_get_group_pins, 304 }; 305 306 static int lp_get_functions_count(struct pinctrl_dev *pctldev) 307 { 308 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 309 310 return lg->soc->nfunctions; 311 } 312 313 static const char *lp_get_function_name(struct pinctrl_dev *pctldev, 314 unsigned int selector) 315 { 316 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 317 318 return lg->soc->functions[selector].name; 319 } 320 321 static int lp_get_function_groups(struct pinctrl_dev *pctldev, 322 unsigned int selector, 323 const char * const **groups, 324 unsigned int *num_groups) 325 { 326 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 327 328 *groups = lg->soc->functions[selector].groups; 329 *num_groups = lg->soc->functions[selector].ngroups; 330 331 return 0; 332 } 333 334 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 335 unsigned int function, unsigned int group) 336 { 337 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 338 const struct intel_pingroup *grp = &lg->soc->groups[group]; 339 unsigned long flags; 340 int i; 341 342 raw_spin_lock_irqsave(&lg->lock, flags); 343 344 /* Now enable the mux setting for each pin in the group */ 345 for (i = 0; i < grp->npins; i++) { 346 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); 347 u32 value; 348 349 value = ioread32(reg); 350 351 value &= ~USE_SEL_MASK; 352 if (grp->modes) 353 value |= grp->modes[i]; 354 else 355 value |= grp->mode; 356 357 iowrite32(value, reg); 358 } 359 360 raw_spin_unlock_irqrestore(&lg->lock, flags); 361 362 return 0; 363 } 364 365 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 366 struct pinctrl_gpio_range *range, 367 unsigned int pin) 368 { 369 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 370 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 371 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 372 unsigned long flags; 373 u32 value; 374 375 pm_runtime_get(lg->dev); 376 377 raw_spin_lock_irqsave(&lg->lock, flags); 378 379 /* 380 * Reconfigure pin to GPIO mode if needed and issue a warning, 381 * since we expect firmware to configure it properly. 382 */ 383 value = ioread32(reg); 384 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 385 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 386 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 387 } 388 389 /* Enable input sensing */ 390 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 391 392 raw_spin_unlock_irqrestore(&lg->lock, flags); 393 394 return 0; 395 } 396 397 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 398 struct pinctrl_gpio_range *range, 399 unsigned int pin) 400 { 401 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 402 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 403 unsigned long flags; 404 405 raw_spin_lock_irqsave(&lg->lock, flags); 406 407 /* Disable input sensing */ 408 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 409 410 raw_spin_unlock_irqrestore(&lg->lock, flags); 411 412 pm_runtime_put(lg->dev); 413 } 414 415 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 416 struct pinctrl_gpio_range *range, 417 unsigned int pin, bool input) 418 { 419 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 420 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 421 unsigned long flags; 422 u32 value; 423 424 raw_spin_lock_irqsave(&lg->lock, flags); 425 426 value = ioread32(reg); 427 value &= ~DIR_BIT; 428 if (input) { 429 value |= DIR_BIT; 430 } else { 431 /* 432 * Before making any direction modifications, do a check if GPIO 433 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 434 * does not make sense, so let's at least warn the caller before 435 * they shoot themselves in the foot. 436 */ 437 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 438 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 439 } 440 iowrite32(value, reg); 441 442 raw_spin_unlock_irqrestore(&lg->lock, flags); 443 444 return 0; 445 } 446 447 static const struct pinmux_ops lptlp_pinmux_ops = { 448 .get_functions_count = lp_get_functions_count, 449 .get_function_name = lp_get_function_name, 450 .get_function_groups = lp_get_function_groups, 451 .set_mux = lp_pinmux_set_mux, 452 .gpio_request_enable = lp_gpio_request_enable, 453 .gpio_disable_free = lp_gpio_disable_free, 454 .gpio_set_direction = lp_gpio_set_direction, 455 }; 456 457 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 458 unsigned long *config) 459 { 460 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 461 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 462 enum pin_config_param param = pinconf_to_config_param(*config); 463 unsigned long flags; 464 u32 value, pull; 465 u16 arg = 0; 466 467 raw_spin_lock_irqsave(&lg->lock, flags); 468 value = ioread32(conf2); 469 raw_spin_unlock_irqrestore(&lg->lock, flags); 470 471 pull = value & GPIWP_MASK; 472 473 switch (param) { 474 case PIN_CONFIG_BIAS_DISABLE: 475 if (pull) 476 return -EINVAL; 477 break; 478 case PIN_CONFIG_BIAS_PULL_DOWN: 479 if (pull != GPIWP_DOWN) 480 return -EINVAL; 481 482 arg = 1; 483 break; 484 case PIN_CONFIG_BIAS_PULL_UP: 485 if (pull != GPIWP_UP) 486 return -EINVAL; 487 488 arg = 1; 489 break; 490 default: 491 return -ENOTSUPP; 492 } 493 494 *config = pinconf_to_config_packed(param, arg); 495 496 return 0; 497 } 498 499 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 500 unsigned long *configs, unsigned int num_configs) 501 { 502 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 503 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 504 enum pin_config_param param; 505 unsigned long flags; 506 int i, ret = 0; 507 u32 value; 508 509 raw_spin_lock_irqsave(&lg->lock, flags); 510 511 value = ioread32(conf2); 512 513 for (i = 0; i < num_configs; i++) { 514 param = pinconf_to_config_param(configs[i]); 515 516 switch (param) { 517 case PIN_CONFIG_BIAS_DISABLE: 518 value &= ~GPIWP_MASK; 519 break; 520 case PIN_CONFIG_BIAS_PULL_DOWN: 521 value &= ~GPIWP_MASK; 522 value |= GPIWP_DOWN; 523 break; 524 case PIN_CONFIG_BIAS_PULL_UP: 525 value &= ~GPIWP_MASK; 526 value |= GPIWP_UP; 527 break; 528 default: 529 ret = -ENOTSUPP; 530 } 531 532 if (ret) 533 break; 534 } 535 536 if (!ret) 537 iowrite32(value, conf2); 538 539 raw_spin_unlock_irqrestore(&lg->lock, flags); 540 541 return ret; 542 } 543 544 static const struct pinconf_ops lptlp_pinconf_ops = { 545 .is_generic = true, 546 .pin_config_get = lp_pin_config_get, 547 .pin_config_set = lp_pin_config_set, 548 }; 549 550 static const struct pinctrl_desc lptlp_pinctrl_desc = { 551 .pctlops = &lptlp_pinctrl_ops, 552 .pmxops = &lptlp_pinmux_ops, 553 .confops = &lptlp_pinconf_ops, 554 .owner = THIS_MODULE, 555 }; 556 557 static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) 558 { 559 struct intel_pinctrl *lg = gpiochip_get_data(chip); 560 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 561 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 562 u32 value; 563 564 pm_runtime_get(lg->dev); /* should we put if failed */ 565 566 /* 567 * Reconfigure pin to GPIO mode if needed and issue a warning, 568 * since we expect firmware to configure it properly. 569 */ 570 value = ioread32(reg); 571 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 572 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 573 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); 574 } 575 576 /* enable input sensing */ 577 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 578 579 580 return 0; 581 } 582 583 static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) 584 { 585 struct intel_pinctrl *lg = gpiochip_get_data(chip); 586 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 587 588 /* disable input sensing */ 589 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 590 591 pm_runtime_put(lg->dev); 592 } 593 594 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 595 { 596 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 597 return !!(ioread32(reg) & IN_LVL_BIT); 598 } 599 600 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 601 { 602 struct intel_pinctrl *lg = gpiochip_get_data(chip); 603 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 604 unsigned long flags; 605 606 raw_spin_lock_irqsave(&lg->lock, flags); 607 608 if (value) 609 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 610 else 611 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 612 613 raw_spin_unlock_irqrestore(&lg->lock, flags); 614 } 615 616 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 617 { 618 struct intel_pinctrl *lg = gpiochip_get_data(chip); 619 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 620 unsigned long flags; 621 622 raw_spin_lock_irqsave(&lg->lock, flags); 623 iowrite32(ioread32(reg) | DIR_BIT, reg); 624 raw_spin_unlock_irqrestore(&lg->lock, flags); 625 626 return 0; 627 } 628 629 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 630 int value) 631 { 632 struct intel_pinctrl *lg = gpiochip_get_data(chip); 633 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 634 unsigned long flags; 635 636 lp_gpio_set(chip, offset, value); 637 638 raw_spin_lock_irqsave(&lg->lock, flags); 639 iowrite32(ioread32(reg) & ~DIR_BIT, reg); 640 raw_spin_unlock_irqrestore(&lg->lock, flags); 641 642 return 0; 643 } 644 645 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 646 { 647 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 648 649 if (ioread32(reg) & DIR_BIT) 650 return GPIO_LINE_DIRECTION_IN; 651 652 return GPIO_LINE_DIRECTION_OUT; 653 } 654 655 static void lp_gpio_irq_handler(struct irq_desc *desc) 656 { 657 struct irq_data *data = irq_desc_get_irq_data(desc); 658 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 659 struct intel_pinctrl *lg = gpiochip_get_data(gc); 660 struct irq_chip *chip = irq_data_get_irq_chip(data); 661 void __iomem *reg, *ena; 662 unsigned long pending; 663 u32 base, pin; 664 665 /* check from GPIO controller which pin triggered the interrupt */ 666 for (base = 0; base < lg->chip.ngpio; base += 32) { 667 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 668 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 669 670 /* Only interrupts that are enabled */ 671 pending = ioread32(reg) & ioread32(ena); 672 673 for_each_set_bit(pin, &pending, 32) { 674 unsigned int irq; 675 676 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 677 generic_handle_irq(irq); 678 } 679 } 680 chip->irq_eoi(data); 681 } 682 683 static void lp_irq_ack(struct irq_data *d) 684 { 685 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 686 struct intel_pinctrl *lg = gpiochip_get_data(gc); 687 u32 hwirq = irqd_to_hwirq(d); 688 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 689 unsigned long flags; 690 691 raw_spin_lock_irqsave(&lg->lock, flags); 692 iowrite32(BIT(hwirq % 32), reg); 693 raw_spin_unlock_irqrestore(&lg->lock, flags); 694 } 695 696 static void lp_irq_unmask(struct irq_data *d) 697 { 698 } 699 700 static void lp_irq_mask(struct irq_data *d) 701 { 702 } 703 704 static void lp_irq_enable(struct irq_data *d) 705 { 706 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 707 struct intel_pinctrl *lg = gpiochip_get_data(gc); 708 u32 hwirq = irqd_to_hwirq(d); 709 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 710 unsigned long flags; 711 712 raw_spin_lock_irqsave(&lg->lock, flags); 713 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 714 raw_spin_unlock_irqrestore(&lg->lock, flags); 715 } 716 717 static void lp_irq_disable(struct irq_data *d) 718 { 719 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 720 struct intel_pinctrl *lg = gpiochip_get_data(gc); 721 u32 hwirq = irqd_to_hwirq(d); 722 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 723 unsigned long flags; 724 725 raw_spin_lock_irqsave(&lg->lock, flags); 726 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 727 raw_spin_unlock_irqrestore(&lg->lock, flags); 728 } 729 730 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 731 { 732 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 733 struct intel_pinctrl *lg = gpiochip_get_data(gc); 734 u32 hwirq = irqd_to_hwirq(d); 735 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 736 unsigned long flags; 737 u32 value; 738 739 if (hwirq >= lg->chip.ngpio) 740 return -EINVAL; 741 742 /* Fail if BIOS reserved pin for ACPI use */ 743 if (lp_gpio_acpi_use(lg, hwirq)) { 744 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); 745 return -EBUSY; 746 } 747 748 raw_spin_lock_irqsave(&lg->lock, flags); 749 value = ioread32(reg); 750 751 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 752 if (type & IRQ_TYPE_EDGE_RISING) 753 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 754 755 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 756 if (type & IRQ_TYPE_EDGE_FALLING) 757 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 758 759 /* TRIG_SEL bit 1, INV bit 0 for level low */ 760 if (type & IRQ_TYPE_LEVEL_LOW) 761 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 762 763 /* TRIG_SEL bit 1, INV bit 1 for level high */ 764 if (type & IRQ_TYPE_LEVEL_HIGH) 765 value |= TRIG_SEL_BIT | INT_INV_BIT; 766 767 iowrite32(value, reg); 768 769 if (type & IRQ_TYPE_EDGE_BOTH) 770 irq_set_handler_locked(d, handle_edge_irq); 771 else if (type & IRQ_TYPE_LEVEL_MASK) 772 irq_set_handler_locked(d, handle_level_irq); 773 774 raw_spin_unlock_irqrestore(&lg->lock, flags); 775 776 return 0; 777 } 778 779 static struct irq_chip lp_irqchip = { 780 .name = "LP-GPIO", 781 .irq_ack = lp_irq_ack, 782 .irq_mask = lp_irq_mask, 783 .irq_unmask = lp_irq_unmask, 784 .irq_enable = lp_irq_enable, 785 .irq_disable = lp_irq_disable, 786 .irq_set_type = lp_irq_set_type, 787 .flags = IRQCHIP_SKIP_SET_WAKE, 788 }; 789 790 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 791 { 792 struct intel_pinctrl *lg = gpiochip_get_data(chip); 793 void __iomem *reg; 794 unsigned int base; 795 796 for (base = 0; base < lg->chip.ngpio; base += 32) { 797 /* disable gpio pin interrupts */ 798 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 799 iowrite32(0, reg); 800 /* Clear interrupt status register */ 801 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 802 iowrite32(0xffffffff, reg); 803 } 804 805 return 0; 806 } 807 808 static int lp_gpio_probe(struct platform_device *pdev) 809 { 810 const struct intel_pinctrl_soc_data *soc; 811 struct intel_pinctrl *lg; 812 struct gpio_chip *gc; 813 struct resource *io_rc, *irq_rc; 814 struct device *dev = &pdev->dev; 815 void __iomem *regs; 816 unsigned int i; 817 int ret; 818 819 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 820 if (!soc) 821 return -ENODEV; 822 823 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 824 if (!lg) 825 return -ENOMEM; 826 827 lg->dev = dev; 828 lg->soc = soc; 829 830 lg->ncommunities = lg->soc->ncommunities; 831 lg->communities = devm_kcalloc(dev, lg->ncommunities, 832 sizeof(*lg->communities), GFP_KERNEL); 833 if (!lg->communities) 834 return -ENOMEM; 835 836 lg->pctldesc = lptlp_pinctrl_desc; 837 lg->pctldesc.name = dev_name(dev); 838 lg->pctldesc.pins = lg->soc->pins; 839 lg->pctldesc.npins = lg->soc->npins; 840 841 platform_set_drvdata(pdev, lg); 842 843 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 844 if (!io_rc) { 845 dev_err(dev, "missing IO resources\n"); 846 return -EINVAL; 847 } 848 849 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 850 if (!regs) { 851 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 852 return -EBUSY; 853 } 854 855 for (i = 0; i < lg->soc->ncommunities; i++) { 856 struct intel_community *comm = &lg->communities[i]; 857 858 *comm = lg->soc->communities[i]; 859 860 comm->regs = regs; 861 comm->pad_regs = regs + 0x100; 862 } 863 864 raw_spin_lock_init(&lg->lock); 865 866 gc = &lg->chip; 867 gc->label = dev_name(dev); 868 gc->owner = THIS_MODULE; 869 gc->request = lp_gpio_request; 870 gc->free = lp_gpio_free; 871 gc->direction_input = lp_gpio_direction_input; 872 gc->direction_output = lp_gpio_direction_output; 873 gc->get = lp_gpio_get; 874 gc->set = lp_gpio_set; 875 gc->get_direction = lp_gpio_get_direction; 876 gc->base = -1; 877 gc->ngpio = LP_NUM_GPIO; 878 gc->can_sleep = false; 879 gc->parent = dev; 880 881 /* set up interrupts */ 882 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 883 if (irq_rc && irq_rc->start) { 884 struct gpio_irq_chip *girq; 885 886 girq = &gc->irq; 887 girq->chip = &lp_irqchip; 888 girq->init_hw = lp_gpio_irq_init_hw; 889 girq->parent_handler = lp_gpio_irq_handler; 890 girq->num_parents = 1; 891 girq->parents = devm_kcalloc(dev, girq->num_parents, 892 sizeof(*girq->parents), 893 GFP_KERNEL); 894 if (!girq->parents) 895 return -ENOMEM; 896 girq->parents[0] = (unsigned int)irq_rc->start; 897 girq->default_type = IRQ_TYPE_NONE; 898 girq->handler = handle_bad_irq; 899 } 900 901 ret = devm_gpiochip_add_data(dev, gc, lg); 902 if (ret) { 903 dev_err(dev, "failed adding lp-gpio chip\n"); 904 return ret; 905 } 906 907 pm_runtime_enable(dev); 908 909 return 0; 910 } 911 912 static int lp_gpio_remove(struct platform_device *pdev) 913 { 914 pm_runtime_disable(&pdev->dev); 915 return 0; 916 } 917 918 static int lp_gpio_runtime_suspend(struct device *dev) 919 { 920 return 0; 921 } 922 923 static int lp_gpio_runtime_resume(struct device *dev) 924 { 925 return 0; 926 } 927 928 static int lp_gpio_resume(struct device *dev) 929 { 930 struct intel_pinctrl *lg = dev_get_drvdata(dev); 931 void __iomem *reg; 932 int i; 933 934 /* on some hardware suspend clears input sensing, re-enable it here */ 935 for (i = 0; i < lg->chip.ngpio; i++) { 936 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 937 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 938 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 939 } 940 } 941 return 0; 942 } 943 944 static const struct dev_pm_ops lp_gpio_pm_ops = { 945 .runtime_suspend = lp_gpio_runtime_suspend, 946 .runtime_resume = lp_gpio_runtime_resume, 947 .resume = lp_gpio_resume, 948 }; 949 950 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 951 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 952 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 953 { } 954 }; 955 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 956 957 static struct platform_driver lp_gpio_driver = { 958 .probe = lp_gpio_probe, 959 .remove = lp_gpio_remove, 960 .driver = { 961 .name = "lp_gpio", 962 .pm = &lp_gpio_pm_ops, 963 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 964 }, 965 }; 966 967 static int __init lp_gpio_init(void) 968 { 969 return platform_driver_register(&lp_gpio_driver); 970 } 971 972 static void __exit lp_gpio_exit(void) 973 { 974 platform_driver_unregister(&lp_gpio_driver); 975 } 976 977 subsys_initcall(lp_gpio_init); 978 module_exit(lp_gpio_exit); 979 980 MODULE_AUTHOR("Mathias Nyman (Intel)"); 981 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); 982 MODULE_LICENSE("GPL v2"); 983 MODULE_ALIAS("platform:lp_gpio"); 984