1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Lynxpoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (c) 2012, 2019, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitops.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 #include <linux/types.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include "pinctrl-intel.h" 30 31 #define COMMUNITY(p, n) \ 32 { \ 33 .pin_base = (p), \ 34 .npins = (n), \ 35 } 36 37 static const struct pinctrl_pin_desc lptlp_pins[] = { 38 PINCTRL_PIN(0, "GP0_UART1_RXD"), 39 PINCTRL_PIN(1, "GP1_UART1_TXD"), 40 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 41 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 42 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 43 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 44 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 45 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 46 PINCTRL_PIN(8, "GP8"), 47 PINCTRL_PIN(9, "GP9"), 48 PINCTRL_PIN(10, "GP10"), 49 PINCTRL_PIN(11, "GP11_SMBALERTB"), 50 PINCTRL_PIN(12, "GP12_LANPHYPC"), 51 PINCTRL_PIN(13, "GP13"), 52 PINCTRL_PIN(14, "GP14"), 53 PINCTRL_PIN(15, "GP15"), 54 PINCTRL_PIN(16, "GP16_MGPIO9"), 55 PINCTRL_PIN(17, "GP17_MGPIO10"), 56 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 57 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 58 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 59 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 60 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 61 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 62 PINCTRL_PIN(24, "GP24_MGPIO0"), 63 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 64 PINCTRL_PIN(26, "GP26_MGPIO5"), 65 PINCTRL_PIN(27, "GP27_MGPIO6"), 66 PINCTRL_PIN(28, "GP28_MGPIO7"), 67 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 68 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 69 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 70 PINCTRL_PIN(32, "GP32_CLKRUNB"), 71 PINCTRL_PIN(33, "GP33_DEVSLP0"), 72 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 73 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 74 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 75 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 76 PINCTRL_PIN(38, "GP38_DEVSLP1"), 77 PINCTRL_PIN(39, "GP39_DEVSLP2"), 78 PINCTRL_PIN(40, "GP40_OC0B"), 79 PINCTRL_PIN(41, "GP41_OC1B"), 80 PINCTRL_PIN(42, "GP42_OC2B"), 81 PINCTRL_PIN(43, "GP43_OC3B"), 82 PINCTRL_PIN(44, "GP44"), 83 PINCTRL_PIN(45, "GP45_TMS2"), 84 PINCTRL_PIN(46, "GP46_TDO2"), 85 PINCTRL_PIN(47, "GP47"), 86 PINCTRL_PIN(48, "GP48"), 87 PINCTRL_PIN(49, "GP49"), 88 PINCTRL_PIN(50, "GP50"), 89 PINCTRL_PIN(51, "GP51_GSXDOUT"), 90 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 91 PINCTRL_PIN(53, "GP53_GSXDIN"), 92 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 93 PINCTRL_PIN(55, "GP55_GSXCLK"), 94 PINCTRL_PIN(56, "GP56"), 95 PINCTRL_PIN(57, "GP57"), 96 PINCTRL_PIN(58, "GP58"), 97 PINCTRL_PIN(59, "GP59"), 98 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 99 PINCTRL_PIN(61, "GP61_SUS_STATB"), 100 PINCTRL_PIN(62, "GP62_SUSCLK"), 101 PINCTRL_PIN(63, "GP63_SLP_S5B"), 102 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 103 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 104 PINCTRL_PIN(66, "GP66_SDIO_D0"), 105 PINCTRL_PIN(67, "GP67_SDIO_D1"), 106 PINCTRL_PIN(68, "GP68_SDIO_D2"), 107 PINCTRL_PIN(69, "GP69_SDIO_D3"), 108 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 109 PINCTRL_PIN(71, "GP71_MPHYPC"), 110 PINCTRL_PIN(72, "GP72_BATLOWB"), 111 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 112 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 113 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 114 PINCTRL_PIN(76, "GP76_BMBUSYB"), 115 PINCTRL_PIN(77, "GP77_PIRQAB"), 116 PINCTRL_PIN(78, "GP78_PIRQBB"), 117 PINCTRL_PIN(79, "GP79_PIRQCB"), 118 PINCTRL_PIN(80, "GP80_PIRQDB"), 119 PINCTRL_PIN(81, "GP81_SPKR"), 120 PINCTRL_PIN(82, "GP82_RCINB"), 121 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 122 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 123 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 124 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 125 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 126 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 127 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 128 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 129 PINCTRL_PIN(91, "GP91_UART0_RXD"), 130 PINCTRL_PIN(92, "GP92_UART0_TXD"), 131 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 132 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 133 }; 134 135 static const struct intel_community lptlp_communities[] = { 136 COMMUNITY(0, 95), 137 }; 138 139 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 140 .pins = lptlp_pins, 141 .npins = ARRAY_SIZE(lptlp_pins), 142 .communities = lptlp_communities, 143 .ncommunities = ARRAY_SIZE(lptlp_communities), 144 }; 145 146 /* LynxPoint chipset has support for 95 GPIO pins */ 147 148 #define LP_NUM_GPIO 95 149 150 /* Bitmapped register offsets */ 151 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 152 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 153 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 154 #define LP_INT_STAT 0x80 155 #define LP_INT_ENABLE 0x90 156 157 /* Each pin has two 32 bit config registers, starting at 0x100 */ 158 #define LP_CONFIG1 0x100 159 #define LP_CONFIG2 0x104 160 161 /* LP_CONFIG1 reg bits */ 162 #define OUT_LVL_BIT BIT(31) 163 #define IN_LVL_BIT BIT(30) 164 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 165 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 166 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 167 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 168 #define USE_SEL_NATIVE (0 << 0) 169 #define USE_SEL_GPIO (1 << 0) 170 171 /* LP_CONFIG2 reg bits */ 172 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 173 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 174 #define GPIWP_NONE 0 /* none */ 175 #define GPIWP_DOWN 1 /* weak pull down */ 176 #define GPIWP_UP 2 /* weak pull up */ 177 178 /* 179 * Lynxpoint gpios are controlled through both bitmapped registers and 180 * per gpio specific registers. The bitmapped registers are in chunks of 181 * 3 x 32bit registers to cover all 95 GPIOs 182 * 183 * per gpio specific registers consist of two 32bit registers per gpio 184 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 185 * 190 config registers. 186 * 187 * A simplified view of the register layout look like this: 188 * 189 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 190 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 191 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 192 * ... 193 * LP_INT_ENABLE[31:0] ... 194 * LP_INT_ENABLE[63:32] ... 195 * LP_INT_ENABLE[94:64] ... 196 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 197 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 198 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 199 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 200 * LP2_CONFIG1 (gpio 2) ... 201 * LP2_CONFIG2 (gpio 2) ... 202 * ... 203 * LP94_CONFIG1 (gpio 94) ... 204 * LP94_CONFIG2 (gpio 94) ... 205 * 206 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 207 */ 208 209 static struct intel_community *lp_get_community(struct intel_pinctrl *lg, 210 unsigned int pin) 211 { 212 struct intel_community *comm; 213 int i; 214 215 for (i = 0; i < lg->ncommunities; i++) { 216 comm = &lg->communities[i]; 217 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 218 return comm; 219 } 220 221 return NULL; 222 } 223 224 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 225 int reg) 226 { 227 struct intel_pinctrl *lg = gpiochip_get_data(chip); 228 struct intel_community *comm; 229 int reg_offset; 230 231 comm = lp_get_community(lg, offset); 232 if (!comm) 233 return NULL; 234 235 offset -= comm->pin_base; 236 237 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 238 /* per gpio specific config registers */ 239 reg_offset = offset * 8; 240 else 241 /* bitmapped registers */ 242 reg_offset = (offset / 32) * 4; 243 244 return comm->regs + reg_offset + reg; 245 } 246 247 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 248 { 249 void __iomem *acpi_use; 250 251 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 252 if (!acpi_use) 253 return true; 254 255 return !(ioread32(acpi_use) & BIT(pin % 32)); 256 } 257 258 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 259 { 260 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 261 u32 value; 262 263 value = ioread32(ioxapic_use); 264 265 if (offset >= 8 && offset <= 10) 266 return !!(value & BIT(offset - 8 + 0)); 267 if (offset >= 13 && offset <= 14) 268 return !!(value & BIT(offset - 13 + 3)); 269 if (offset >= 45 && offset <= 55) 270 return !!(value & BIT(offset - 45 + 5)); 271 272 return false; 273 } 274 275 static int lp_get_groups_count(struct pinctrl_dev *pctldev) 276 { 277 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 278 279 return lg->soc->ngroups; 280 } 281 282 static const char *lp_get_group_name(struct pinctrl_dev *pctldev, 283 unsigned int selector) 284 { 285 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 286 287 return lg->soc->groups[selector].grp.name; 288 } 289 290 static int lp_get_group_pins(struct pinctrl_dev *pctldev, 291 unsigned int selector, 292 const unsigned int **pins, 293 unsigned int *num_pins) 294 { 295 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 296 297 *pins = lg->soc->groups[selector].grp.pins; 298 *num_pins = lg->soc->groups[selector].grp.npins; 299 300 return 0; 301 } 302 303 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 304 unsigned int pin) 305 { 306 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 307 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 308 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 309 u32 value, mode; 310 311 value = ioread32(reg); 312 313 mode = value & USE_SEL_MASK; 314 if (mode == USE_SEL_GPIO) 315 seq_puts(s, "GPIO "); 316 else 317 seq_printf(s, "mode %d ", mode); 318 319 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 320 321 if (lp_gpio_acpi_use(lg, pin)) 322 seq_puts(s, " [ACPI]"); 323 } 324 325 static const struct pinctrl_ops lptlp_pinctrl_ops = { 326 .get_groups_count = lp_get_groups_count, 327 .get_group_name = lp_get_group_name, 328 .get_group_pins = lp_get_group_pins, 329 .pin_dbg_show = lp_pin_dbg_show, 330 }; 331 332 static int lp_get_functions_count(struct pinctrl_dev *pctldev) 333 { 334 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 335 336 return lg->soc->nfunctions; 337 } 338 339 static const char *lp_get_function_name(struct pinctrl_dev *pctldev, 340 unsigned int selector) 341 { 342 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 343 344 return lg->soc->functions[selector].name; 345 } 346 347 static int lp_get_function_groups(struct pinctrl_dev *pctldev, 348 unsigned int selector, 349 const char * const **groups, 350 unsigned int *num_groups) 351 { 352 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 353 354 *groups = lg->soc->functions[selector].groups; 355 *num_groups = lg->soc->functions[selector].ngroups; 356 357 return 0; 358 } 359 360 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 361 unsigned int function, unsigned int group) 362 { 363 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 364 const struct intel_pingroup *grp = &lg->soc->groups[group]; 365 unsigned long flags; 366 int i; 367 368 raw_spin_lock_irqsave(&lg->lock, flags); 369 370 /* Now enable the mux setting for each pin in the group */ 371 for (i = 0; i < grp->grp.npins; i++) { 372 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); 373 u32 value; 374 375 value = ioread32(reg); 376 377 value &= ~USE_SEL_MASK; 378 if (grp->modes) 379 value |= grp->modes[i]; 380 else 381 value |= grp->mode; 382 383 iowrite32(value, reg); 384 } 385 386 raw_spin_unlock_irqrestore(&lg->lock, flags); 387 388 return 0; 389 } 390 391 static void lp_gpio_enable_input(void __iomem *reg) 392 { 393 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 394 } 395 396 static void lp_gpio_disable_input(void __iomem *reg) 397 { 398 iowrite32(ioread32(reg) | GPINDIS_BIT, reg); 399 } 400 401 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 402 struct pinctrl_gpio_range *range, 403 unsigned int pin) 404 { 405 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 406 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 407 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 408 unsigned long flags; 409 u32 value; 410 411 pm_runtime_get(lg->dev); 412 413 raw_spin_lock_irqsave(&lg->lock, flags); 414 415 /* 416 * Reconfigure pin to GPIO mode if needed and issue a warning, 417 * since we expect firmware to configure it properly. 418 */ 419 value = ioread32(reg); 420 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 421 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 422 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 423 } 424 425 /* Enable input sensing */ 426 lp_gpio_enable_input(conf2); 427 428 raw_spin_unlock_irqrestore(&lg->lock, flags); 429 430 return 0; 431 } 432 433 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 434 struct pinctrl_gpio_range *range, 435 unsigned int pin) 436 { 437 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 438 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 439 unsigned long flags; 440 441 raw_spin_lock_irqsave(&lg->lock, flags); 442 443 /* Disable input sensing */ 444 lp_gpio_disable_input(conf2); 445 446 raw_spin_unlock_irqrestore(&lg->lock, flags); 447 448 pm_runtime_put(lg->dev); 449 } 450 451 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 452 struct pinctrl_gpio_range *range, 453 unsigned int pin, bool input) 454 { 455 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 456 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 457 unsigned long flags; 458 u32 value; 459 460 raw_spin_lock_irqsave(&lg->lock, flags); 461 462 value = ioread32(reg); 463 value &= ~DIR_BIT; 464 if (input) { 465 value |= DIR_BIT; 466 } else { 467 /* 468 * Before making any direction modifications, do a check if GPIO 469 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 470 * does not make sense, so let's at least warn the caller before 471 * they shoot themselves in the foot. 472 */ 473 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 474 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 475 } 476 iowrite32(value, reg); 477 478 raw_spin_unlock_irqrestore(&lg->lock, flags); 479 480 return 0; 481 } 482 483 static const struct pinmux_ops lptlp_pinmux_ops = { 484 .get_functions_count = lp_get_functions_count, 485 .get_function_name = lp_get_function_name, 486 .get_function_groups = lp_get_function_groups, 487 .set_mux = lp_pinmux_set_mux, 488 .gpio_request_enable = lp_gpio_request_enable, 489 .gpio_disable_free = lp_gpio_disable_free, 490 .gpio_set_direction = lp_gpio_set_direction, 491 }; 492 493 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 494 unsigned long *config) 495 { 496 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 497 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 498 enum pin_config_param param = pinconf_to_config_param(*config); 499 unsigned long flags; 500 u32 value, pull; 501 u16 arg; 502 503 raw_spin_lock_irqsave(&lg->lock, flags); 504 value = ioread32(conf2); 505 raw_spin_unlock_irqrestore(&lg->lock, flags); 506 507 pull = value & GPIWP_MASK; 508 509 switch (param) { 510 case PIN_CONFIG_BIAS_DISABLE: 511 if (pull != GPIWP_NONE) 512 return -EINVAL; 513 arg = 0; 514 break; 515 case PIN_CONFIG_BIAS_PULL_DOWN: 516 if (pull != GPIWP_DOWN) 517 return -EINVAL; 518 519 arg = 1; 520 break; 521 case PIN_CONFIG_BIAS_PULL_UP: 522 if (pull != GPIWP_UP) 523 return -EINVAL; 524 525 arg = 1; 526 break; 527 default: 528 return -ENOTSUPP; 529 } 530 531 *config = pinconf_to_config_packed(param, arg); 532 533 return 0; 534 } 535 536 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 537 unsigned long *configs, unsigned int num_configs) 538 { 539 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 540 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 541 enum pin_config_param param; 542 unsigned long flags; 543 int i, ret = 0; 544 u32 value; 545 546 raw_spin_lock_irqsave(&lg->lock, flags); 547 548 value = ioread32(conf2); 549 550 for (i = 0; i < num_configs; i++) { 551 param = pinconf_to_config_param(configs[i]); 552 553 switch (param) { 554 case PIN_CONFIG_BIAS_DISABLE: 555 value &= ~GPIWP_MASK; 556 value |= GPIWP_NONE; 557 break; 558 case PIN_CONFIG_BIAS_PULL_DOWN: 559 value &= ~GPIWP_MASK; 560 value |= GPIWP_DOWN; 561 break; 562 case PIN_CONFIG_BIAS_PULL_UP: 563 value &= ~GPIWP_MASK; 564 value |= GPIWP_UP; 565 break; 566 default: 567 ret = -ENOTSUPP; 568 } 569 570 if (ret) 571 break; 572 } 573 574 if (!ret) 575 iowrite32(value, conf2); 576 577 raw_spin_unlock_irqrestore(&lg->lock, flags); 578 579 return ret; 580 } 581 582 static const struct pinconf_ops lptlp_pinconf_ops = { 583 .is_generic = true, 584 .pin_config_get = lp_pin_config_get, 585 .pin_config_set = lp_pin_config_set, 586 }; 587 588 static const struct pinctrl_desc lptlp_pinctrl_desc = { 589 .pctlops = &lptlp_pinctrl_ops, 590 .pmxops = &lptlp_pinmux_ops, 591 .confops = &lptlp_pinconf_ops, 592 .owner = THIS_MODULE, 593 }; 594 595 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 596 { 597 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 598 return !!(ioread32(reg) & IN_LVL_BIT); 599 } 600 601 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 602 { 603 struct intel_pinctrl *lg = gpiochip_get_data(chip); 604 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 605 unsigned long flags; 606 607 raw_spin_lock_irqsave(&lg->lock, flags); 608 609 if (value) 610 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 611 else 612 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 613 614 raw_spin_unlock_irqrestore(&lg->lock, flags); 615 } 616 617 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 618 { 619 return pinctrl_gpio_direction_input(chip->base + offset); 620 } 621 622 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 623 int value) 624 { 625 lp_gpio_set(chip, offset, value); 626 627 return pinctrl_gpio_direction_output(chip->base + offset); 628 } 629 630 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 631 { 632 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 633 634 if (ioread32(reg) & DIR_BIT) 635 return GPIO_LINE_DIRECTION_IN; 636 637 return GPIO_LINE_DIRECTION_OUT; 638 } 639 640 static void lp_gpio_irq_handler(struct irq_desc *desc) 641 { 642 struct irq_data *data = irq_desc_get_irq_data(desc); 643 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 644 struct intel_pinctrl *lg = gpiochip_get_data(gc); 645 struct irq_chip *chip = irq_data_get_irq_chip(data); 646 void __iomem *reg, *ena; 647 unsigned long pending; 648 u32 base, pin; 649 650 /* check from GPIO controller which pin triggered the interrupt */ 651 for (base = 0; base < lg->chip.ngpio; base += 32) { 652 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 653 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 654 655 /* Only interrupts that are enabled */ 656 pending = ioread32(reg) & ioread32(ena); 657 658 for_each_set_bit(pin, &pending, 32) 659 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); 660 } 661 chip->irq_eoi(data); 662 } 663 664 static void lp_irq_ack(struct irq_data *d) 665 { 666 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 667 struct intel_pinctrl *lg = gpiochip_get_data(gc); 668 irq_hw_number_t hwirq = irqd_to_hwirq(d); 669 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 670 unsigned long flags; 671 672 raw_spin_lock_irqsave(&lg->lock, flags); 673 iowrite32(BIT(hwirq % 32), reg); 674 raw_spin_unlock_irqrestore(&lg->lock, flags); 675 } 676 677 static void lp_irq_unmask(struct irq_data *d) 678 { 679 } 680 681 static void lp_irq_mask(struct irq_data *d) 682 { 683 } 684 685 static void lp_irq_enable(struct irq_data *d) 686 { 687 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 688 struct intel_pinctrl *lg = gpiochip_get_data(gc); 689 irq_hw_number_t hwirq = irqd_to_hwirq(d); 690 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 691 unsigned long flags; 692 693 gpiochip_enable_irq(gc, hwirq); 694 695 raw_spin_lock_irqsave(&lg->lock, flags); 696 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 697 raw_spin_unlock_irqrestore(&lg->lock, flags); 698 } 699 700 static void lp_irq_disable(struct irq_data *d) 701 { 702 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 703 struct intel_pinctrl *lg = gpiochip_get_data(gc); 704 irq_hw_number_t hwirq = irqd_to_hwirq(d); 705 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 706 unsigned long flags; 707 708 raw_spin_lock_irqsave(&lg->lock, flags); 709 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 710 raw_spin_unlock_irqrestore(&lg->lock, flags); 711 712 gpiochip_disable_irq(gc, hwirq); 713 } 714 715 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 716 { 717 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 718 struct intel_pinctrl *lg = gpiochip_get_data(gc); 719 irq_hw_number_t hwirq = irqd_to_hwirq(d); 720 unsigned long flags; 721 void __iomem *reg; 722 u32 value; 723 724 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 725 if (!reg) 726 return -EINVAL; 727 728 /* Fail if BIOS reserved pin for ACPI use */ 729 if (lp_gpio_acpi_use(lg, hwirq)) { 730 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); 731 return -EBUSY; 732 } 733 734 raw_spin_lock_irqsave(&lg->lock, flags); 735 value = ioread32(reg); 736 737 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 738 if (type & IRQ_TYPE_EDGE_RISING) 739 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 740 741 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 742 if (type & IRQ_TYPE_EDGE_FALLING) 743 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 744 745 /* TRIG_SEL bit 1, INV bit 0 for level low */ 746 if (type & IRQ_TYPE_LEVEL_LOW) 747 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 748 749 /* TRIG_SEL bit 1, INV bit 1 for level high */ 750 if (type & IRQ_TYPE_LEVEL_HIGH) 751 value |= TRIG_SEL_BIT | INT_INV_BIT; 752 753 iowrite32(value, reg); 754 755 if (type & IRQ_TYPE_EDGE_BOTH) 756 irq_set_handler_locked(d, handle_edge_irq); 757 else if (type & IRQ_TYPE_LEVEL_MASK) 758 irq_set_handler_locked(d, handle_level_irq); 759 760 raw_spin_unlock_irqrestore(&lg->lock, flags); 761 762 return 0; 763 } 764 765 static const struct irq_chip lp_irqchip = { 766 .name = "LP-GPIO", 767 .irq_ack = lp_irq_ack, 768 .irq_mask = lp_irq_mask, 769 .irq_unmask = lp_irq_unmask, 770 .irq_enable = lp_irq_enable, 771 .irq_disable = lp_irq_disable, 772 .irq_set_type = lp_irq_set_type, 773 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 774 GPIOCHIP_IRQ_RESOURCE_HELPERS, 775 }; 776 777 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 778 { 779 struct intel_pinctrl *lg = gpiochip_get_data(chip); 780 void __iomem *reg; 781 unsigned int base; 782 783 for (base = 0; base < lg->chip.ngpio; base += 32) { 784 /* disable gpio pin interrupts */ 785 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 786 iowrite32(0, reg); 787 /* Clear interrupt status register */ 788 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 789 iowrite32(0xffffffff, reg); 790 } 791 792 return 0; 793 } 794 795 static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) 796 { 797 struct intel_pinctrl *lg = gpiochip_get_data(chip); 798 struct device *dev = lg->dev; 799 int ret; 800 801 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); 802 if (ret) 803 dev_err(dev, "failed to add GPIO pin range\n"); 804 805 return ret; 806 } 807 808 static int lp_gpio_probe(struct platform_device *pdev) 809 { 810 const struct intel_pinctrl_soc_data *soc; 811 struct intel_pinctrl *lg; 812 struct gpio_chip *gc; 813 struct device *dev = &pdev->dev; 814 struct resource *io_rc; 815 void __iomem *regs; 816 unsigned int i; 817 int irq, ret; 818 819 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 820 if (!soc) 821 return -ENODEV; 822 823 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 824 if (!lg) 825 return -ENOMEM; 826 827 lg->dev = dev; 828 lg->soc = soc; 829 830 lg->ncommunities = lg->soc->ncommunities; 831 lg->communities = devm_kcalloc(dev, lg->ncommunities, 832 sizeof(*lg->communities), GFP_KERNEL); 833 if (!lg->communities) 834 return -ENOMEM; 835 836 lg->pctldesc = lptlp_pinctrl_desc; 837 lg->pctldesc.name = dev_name(dev); 838 lg->pctldesc.pins = lg->soc->pins; 839 lg->pctldesc.npins = lg->soc->npins; 840 841 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 842 if (IS_ERR(lg->pctldev)) { 843 dev_err(dev, "failed to register pinctrl driver\n"); 844 return PTR_ERR(lg->pctldev); 845 } 846 847 platform_set_drvdata(pdev, lg); 848 849 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 850 if (!io_rc) { 851 dev_err(dev, "missing IO resources\n"); 852 return -EINVAL; 853 } 854 855 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 856 if (!regs) { 857 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 858 return -EBUSY; 859 } 860 861 for (i = 0; i < lg->soc->ncommunities; i++) { 862 struct intel_community *comm = &lg->communities[i]; 863 864 *comm = lg->soc->communities[i]; 865 866 comm->regs = regs; 867 comm->pad_regs = regs + 0x100; 868 } 869 870 raw_spin_lock_init(&lg->lock); 871 872 gc = &lg->chip; 873 gc->label = dev_name(dev); 874 gc->owner = THIS_MODULE; 875 gc->request = gpiochip_generic_request; 876 gc->free = gpiochip_generic_free; 877 gc->direction_input = lp_gpio_direction_input; 878 gc->direction_output = lp_gpio_direction_output; 879 gc->get = lp_gpio_get; 880 gc->set = lp_gpio_set; 881 gc->set_config = gpiochip_generic_config; 882 gc->get_direction = lp_gpio_get_direction; 883 gc->base = -1; 884 gc->ngpio = LP_NUM_GPIO; 885 gc->can_sleep = false; 886 gc->add_pin_ranges = lp_gpio_add_pin_ranges; 887 gc->parent = dev; 888 889 /* set up interrupts */ 890 irq = platform_get_irq_optional(pdev, 0); 891 if (irq > 0) { 892 struct gpio_irq_chip *girq; 893 894 girq = &gc->irq; 895 gpio_irq_chip_set_chip(girq, &lp_irqchip); 896 girq->init_hw = lp_gpio_irq_init_hw; 897 girq->parent_handler = lp_gpio_irq_handler; 898 girq->num_parents = 1; 899 girq->parents = devm_kcalloc(dev, girq->num_parents, 900 sizeof(*girq->parents), 901 GFP_KERNEL); 902 if (!girq->parents) 903 return -ENOMEM; 904 girq->parents[0] = irq; 905 girq->default_type = IRQ_TYPE_NONE; 906 girq->handler = handle_bad_irq; 907 } 908 909 ret = devm_gpiochip_add_data(dev, gc, lg); 910 if (ret) { 911 dev_err(dev, "failed adding lp-gpio chip\n"); 912 return ret; 913 } 914 915 pm_runtime_enable(dev); 916 917 return 0; 918 } 919 920 static int lp_gpio_remove(struct platform_device *pdev) 921 { 922 pm_runtime_disable(&pdev->dev); 923 return 0; 924 } 925 926 static int lp_gpio_runtime_suspend(struct device *dev) 927 { 928 return 0; 929 } 930 931 static int lp_gpio_runtime_resume(struct device *dev) 932 { 933 return 0; 934 } 935 936 static int lp_gpio_resume(struct device *dev) 937 { 938 struct intel_pinctrl *lg = dev_get_drvdata(dev); 939 struct gpio_chip *chip = &lg->chip; 940 const char *dummy; 941 int i; 942 943 /* on some hardware suspend clears input sensing, re-enable it here */ 944 for_each_requested_gpio(chip, i, dummy) 945 lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2)); 946 947 return 0; 948 } 949 950 static const struct dev_pm_ops lp_gpio_pm_ops = { 951 .runtime_suspend = lp_gpio_runtime_suspend, 952 .runtime_resume = lp_gpio_runtime_resume, 953 .resume = lp_gpio_resume, 954 }; 955 956 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 957 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 958 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 959 { } 960 }; 961 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 962 963 static struct platform_driver lp_gpio_driver = { 964 .probe = lp_gpio_probe, 965 .remove = lp_gpio_remove, 966 .driver = { 967 .name = "lp_gpio", 968 .pm = &lp_gpio_pm_ops, 969 .acpi_match_table = lynxpoint_gpio_acpi_match, 970 }, 971 }; 972 973 static int __init lp_gpio_init(void) 974 { 975 return platform_driver_register(&lp_gpio_driver); 976 } 977 subsys_initcall(lp_gpio_init); 978 979 static void __exit lp_gpio_exit(void) 980 { 981 platform_driver_unregister(&lp_gpio_driver); 982 } 983 module_exit(lp_gpio_exit); 984 985 MODULE_AUTHOR("Mathias Nyman (Intel)"); 986 MODULE_AUTHOR("Andy Shevchenko (Intel)"); 987 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); 988 MODULE_LICENSE("GPL v2"); 989 MODULE_ALIAS("platform:lp_gpio"); 990