1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO controller driver for Intel Lynxpoint PCH chipset> 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 /* LynxPoint chipset has support for 95 GPIO pins */ 22 23 #define LP_NUM_GPIO 95 24 25 /* Bitmapped register offsets */ 26 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 27 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 28 #define LP_INT_STAT 0x80 29 #define LP_INT_ENABLE 0x90 30 31 /* Each pin has two 32 bit config registers, starting at 0x100 */ 32 #define LP_CONFIG1 0x100 33 #define LP_CONFIG2 0x104 34 35 /* LP_CONFIG1 reg bits */ 36 #define OUT_LVL_BIT BIT(31) 37 #define IN_LVL_BIT BIT(30) 38 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 39 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 40 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 41 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 42 #define USE_SEL_NATIVE (0 << 0) 43 #define USE_SEL_GPIO (1 << 0) 44 45 /* LP_CONFIG2 reg bits */ 46 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 47 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ 48 49 struct lp_gpio { 50 struct gpio_chip chip; 51 struct device *dev; 52 raw_spinlock_t lock; 53 void __iomem *regs; 54 }; 55 56 /* 57 * Lynxpoint gpios are controlled through both bitmapped registers and 58 * per gpio specific registers. The bitmapped registers are in chunks of 59 * 3 x 32bit registers to cover all 95 GPIOs 60 * 61 * per gpio specific registers consist of two 32bit registers per gpio 62 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 63 * 190 config registers. 64 * 65 * A simplified view of the register layout look like this: 66 * 67 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 68 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 69 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 70 * ... 71 * LP_INT_ENABLE[31:0] ... 72 * LP_INT_ENABLE[63:32] ... 73 * LP_INT_ENABLE[94:64] ... 74 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 75 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 76 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 77 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 78 * LP2_CONFIG1 (gpio 2) ... 79 * LP2_CONFIG2 (gpio 2) ... 80 * ... 81 * LP94_CONFIG1 (gpio 94) ... 82 * LP94_CONFIG2 (gpio 94) ... 83 */ 84 85 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 86 int reg) 87 { 88 struct lp_gpio *lg = gpiochip_get_data(chip); 89 int reg_offset; 90 91 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 92 /* per gpio specific config registers */ 93 reg_offset = offset * 8; 94 else 95 /* bitmapped registers */ 96 reg_offset = (offset / 32) * 4; 97 98 return lg->regs + reg + reg_offset; 99 } 100 101 static bool lp_gpio_acpi_use(struct lp_gpio *lg, unsigned int pin) 102 { 103 void __iomem *acpi_use; 104 105 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 106 if (!acpi_use) 107 return true; 108 109 return !(ioread32(acpi_use) & BIT(pin % 32)); 110 } 111 112 static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) 113 { 114 struct lp_gpio *lg = gpiochip_get_data(chip); 115 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 116 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 117 u32 value; 118 119 pm_runtime_get(lg->dev); /* should we put if failed */ 120 121 /* 122 * Reconfigure pin to GPIO mode if needed and issue a warning, 123 * since we expect firmware to configure it properly. 124 */ 125 value = ioread32(reg); 126 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 127 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 128 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); 129 } 130 131 /* enable input sensing */ 132 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 133 134 135 return 0; 136 } 137 138 static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) 139 { 140 struct lp_gpio *lg = gpiochip_get_data(chip); 141 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 142 143 /* disable input sensing */ 144 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 145 146 pm_runtime_put(lg->dev); 147 } 148 149 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 150 { 151 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 152 return !!(ioread32(reg) & IN_LVL_BIT); 153 } 154 155 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 156 { 157 struct lp_gpio *lg = gpiochip_get_data(chip); 158 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 159 unsigned long flags; 160 161 raw_spin_lock_irqsave(&lg->lock, flags); 162 163 if (value) 164 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 165 else 166 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 167 168 raw_spin_unlock_irqrestore(&lg->lock, flags); 169 } 170 171 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 172 { 173 struct lp_gpio *lg = gpiochip_get_data(chip); 174 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 175 unsigned long flags; 176 177 raw_spin_lock_irqsave(&lg->lock, flags); 178 iowrite32(ioread32(reg) | DIR_BIT, reg); 179 raw_spin_unlock_irqrestore(&lg->lock, flags); 180 181 return 0; 182 } 183 184 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 185 int value) 186 { 187 struct lp_gpio *lg = gpiochip_get_data(chip); 188 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 189 unsigned long flags; 190 191 lp_gpio_set(chip, offset, value); 192 193 raw_spin_lock_irqsave(&lg->lock, flags); 194 iowrite32(ioread32(reg) & ~DIR_BIT, reg); 195 raw_spin_unlock_irqrestore(&lg->lock, flags); 196 197 return 0; 198 } 199 200 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 201 { 202 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 203 204 if (ioread32(reg) & DIR_BIT) 205 return GPIO_LINE_DIRECTION_IN; 206 207 return GPIO_LINE_DIRECTION_OUT; 208 } 209 210 static void lp_gpio_irq_handler(struct irq_desc *desc) 211 { 212 struct irq_data *data = irq_desc_get_irq_data(desc); 213 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 214 struct lp_gpio *lg = gpiochip_get_data(gc); 215 struct irq_chip *chip = irq_data_get_irq_chip(data); 216 void __iomem *reg, *ena; 217 unsigned long pending; 218 u32 base, pin; 219 220 /* check from GPIO controller which pin triggered the interrupt */ 221 for (base = 0; base < lg->chip.ngpio; base += 32) { 222 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 223 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 224 225 /* Only interrupts that are enabled */ 226 pending = ioread32(reg) & ioread32(ena); 227 228 for_each_set_bit(pin, &pending, 32) { 229 unsigned int irq; 230 231 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 232 generic_handle_irq(irq); 233 } 234 } 235 chip->irq_eoi(data); 236 } 237 238 static void lp_irq_ack(struct irq_data *d) 239 { 240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 241 struct lp_gpio *lg = gpiochip_get_data(gc); 242 u32 hwirq = irqd_to_hwirq(d); 243 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 244 unsigned long flags; 245 246 raw_spin_lock_irqsave(&lg->lock, flags); 247 iowrite32(BIT(hwirq % 32), reg); 248 raw_spin_unlock_irqrestore(&lg->lock, flags); 249 } 250 251 static void lp_irq_unmask(struct irq_data *d) 252 { 253 } 254 255 static void lp_irq_mask(struct irq_data *d) 256 { 257 } 258 259 static void lp_irq_enable(struct irq_data *d) 260 { 261 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 262 struct lp_gpio *lg = gpiochip_get_data(gc); 263 u32 hwirq = irqd_to_hwirq(d); 264 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 265 unsigned long flags; 266 267 raw_spin_lock_irqsave(&lg->lock, flags); 268 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 269 raw_spin_unlock_irqrestore(&lg->lock, flags); 270 } 271 272 static void lp_irq_disable(struct irq_data *d) 273 { 274 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 275 struct lp_gpio *lg = gpiochip_get_data(gc); 276 u32 hwirq = irqd_to_hwirq(d); 277 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 278 unsigned long flags; 279 280 raw_spin_lock_irqsave(&lg->lock, flags); 281 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 282 raw_spin_unlock_irqrestore(&lg->lock, flags); 283 } 284 285 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 286 { 287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 288 struct lp_gpio *lg = gpiochip_get_data(gc); 289 u32 hwirq = irqd_to_hwirq(d); 290 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 291 unsigned long flags; 292 u32 value; 293 294 if (hwirq >= lg->chip.ngpio) 295 return -EINVAL; 296 297 /* Fail if BIOS reserved pin for ACPI use */ 298 if (lp_gpio_acpi_use(lg, hwirq)) { 299 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); 300 return -EBUSY; 301 } 302 303 raw_spin_lock_irqsave(&lg->lock, flags); 304 value = ioread32(reg); 305 306 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 307 if (type & IRQ_TYPE_EDGE_RISING) 308 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 309 310 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 311 if (type & IRQ_TYPE_EDGE_FALLING) 312 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 313 314 /* TRIG_SEL bit 1, INV bit 0 for level low */ 315 if (type & IRQ_TYPE_LEVEL_LOW) 316 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 317 318 /* TRIG_SEL bit 1, INV bit 1 for level high */ 319 if (type & IRQ_TYPE_LEVEL_HIGH) 320 value |= TRIG_SEL_BIT | INT_INV_BIT; 321 322 iowrite32(value, reg); 323 324 if (type & IRQ_TYPE_EDGE_BOTH) 325 irq_set_handler_locked(d, handle_edge_irq); 326 else if (type & IRQ_TYPE_LEVEL_MASK) 327 irq_set_handler_locked(d, handle_level_irq); 328 329 raw_spin_unlock_irqrestore(&lg->lock, flags); 330 331 return 0; 332 } 333 334 static struct irq_chip lp_irqchip = { 335 .name = "LP-GPIO", 336 .irq_ack = lp_irq_ack, 337 .irq_mask = lp_irq_mask, 338 .irq_unmask = lp_irq_unmask, 339 .irq_enable = lp_irq_enable, 340 .irq_disable = lp_irq_disable, 341 .irq_set_type = lp_irq_set_type, 342 .flags = IRQCHIP_SKIP_SET_WAKE, 343 }; 344 345 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 346 { 347 struct lp_gpio *lg = gpiochip_get_data(chip); 348 void __iomem *reg; 349 unsigned int base; 350 351 for (base = 0; base < lg->chip.ngpio; base += 32) { 352 /* disable gpio pin interrupts */ 353 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 354 iowrite32(0, reg); 355 /* Clear interrupt status register */ 356 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 357 iowrite32(0xffffffff, reg); 358 } 359 360 return 0; 361 } 362 363 static int lp_gpio_probe(struct platform_device *pdev) 364 { 365 struct lp_gpio *lg; 366 struct gpio_chip *gc; 367 struct resource *io_rc, *irq_rc; 368 struct device *dev = &pdev->dev; 369 void __iomem *regs; 370 int ret; 371 372 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 373 if (!lg) 374 return -ENOMEM; 375 376 lg->dev = dev; 377 platform_set_drvdata(pdev, lg); 378 379 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 380 if (!io_rc) { 381 dev_err(dev, "missing IO resources\n"); 382 return -EINVAL; 383 } 384 385 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 386 if (!regs) { 387 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 388 return -EBUSY; 389 } 390 391 lg->regs = regs; 392 393 raw_spin_lock_init(&lg->lock); 394 395 gc = &lg->chip; 396 gc->label = dev_name(dev); 397 gc->owner = THIS_MODULE; 398 gc->request = lp_gpio_request; 399 gc->free = lp_gpio_free; 400 gc->direction_input = lp_gpio_direction_input; 401 gc->direction_output = lp_gpio_direction_output; 402 gc->get = lp_gpio_get; 403 gc->set = lp_gpio_set; 404 gc->get_direction = lp_gpio_get_direction; 405 gc->base = -1; 406 gc->ngpio = LP_NUM_GPIO; 407 gc->can_sleep = false; 408 gc->parent = dev; 409 410 /* set up interrupts */ 411 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 412 if (irq_rc && irq_rc->start) { 413 struct gpio_irq_chip *girq; 414 415 girq = &gc->irq; 416 girq->chip = &lp_irqchip; 417 girq->init_hw = lp_gpio_irq_init_hw; 418 girq->parent_handler = lp_gpio_irq_handler; 419 girq->num_parents = 1; 420 girq->parents = devm_kcalloc(dev, girq->num_parents, 421 sizeof(*girq->parents), 422 GFP_KERNEL); 423 if (!girq->parents) 424 return -ENOMEM; 425 girq->parents[0] = (unsigned int)irq_rc->start; 426 girq->default_type = IRQ_TYPE_NONE; 427 girq->handler = handle_bad_irq; 428 } 429 430 ret = devm_gpiochip_add_data(dev, gc, lg); 431 if (ret) { 432 dev_err(dev, "failed adding lp-gpio chip\n"); 433 return ret; 434 } 435 436 pm_runtime_enable(dev); 437 438 return 0; 439 } 440 441 static int lp_gpio_remove(struct platform_device *pdev) 442 { 443 pm_runtime_disable(&pdev->dev); 444 return 0; 445 } 446 447 static int lp_gpio_runtime_suspend(struct device *dev) 448 { 449 return 0; 450 } 451 452 static int lp_gpio_runtime_resume(struct device *dev) 453 { 454 return 0; 455 } 456 457 static int lp_gpio_resume(struct device *dev) 458 { 459 struct lp_gpio *lg = dev_get_drvdata(dev); 460 void __iomem *reg; 461 int i; 462 463 /* on some hardware suspend clears input sensing, re-enable it here */ 464 for (i = 0; i < lg->chip.ngpio; i++) { 465 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 466 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 467 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 468 } 469 } 470 return 0; 471 } 472 473 static const struct dev_pm_ops lp_gpio_pm_ops = { 474 .runtime_suspend = lp_gpio_runtime_suspend, 475 .runtime_resume = lp_gpio_runtime_resume, 476 .resume = lp_gpio_resume, 477 }; 478 479 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 480 { "INT33C7", 0 }, 481 { "INT3437", 0 }, 482 { } 483 }; 484 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 485 486 static struct platform_driver lp_gpio_driver = { 487 .probe = lp_gpio_probe, 488 .remove = lp_gpio_remove, 489 .driver = { 490 .name = "lp_gpio", 491 .pm = &lp_gpio_pm_ops, 492 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 493 }, 494 }; 495 496 static int __init lp_gpio_init(void) 497 { 498 return platform_driver_register(&lp_gpio_driver); 499 } 500 501 static void __exit lp_gpio_exit(void) 502 { 503 platform_driver_unregister(&lp_gpio_driver); 504 } 505 506 subsys_initcall(lp_gpio_init); 507 module_exit(lp_gpio_exit); 508 509 MODULE_AUTHOR("Mathias Nyman (Intel)"); 510 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); 511 MODULE_LICENSE("GPL v2"); 512 MODULE_ALIAS("platform:lp_gpio"); 513