1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO controller driver for Intel Lynxpoint PCH chipset> 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 /* LynxPoint chipset has support for 95 GPIO pins */ 22 23 #define LP_NUM_GPIO 95 24 25 /* Bitmapped register offsets */ 26 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 27 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 28 #define LP_INT_STAT 0x80 29 #define LP_INT_ENABLE 0x90 30 31 /* Each pin has two 32 bit config registers, starting at 0x100 */ 32 #define LP_CONFIG1 0x100 33 #define LP_CONFIG2 0x104 34 35 /* LP_CONFIG1 reg bits */ 36 #define OUT_LVL_BIT BIT(31) 37 #define IN_LVL_BIT BIT(30) 38 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 39 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 40 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 41 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 42 #define USE_SEL_NATIVE (0 << 0) 43 #define USE_SEL_GPIO (1 << 0) 44 45 /* LP_CONFIG2 reg bits */ 46 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 47 #define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */ 48 49 struct lp_gpio { 50 struct gpio_chip chip; 51 struct device *dev; 52 raw_spinlock_t lock; 53 unsigned long reg_base; 54 }; 55 56 /* 57 * Lynxpoint gpios are controlled through both bitmapped registers and 58 * per gpio specific registers. The bitmapped registers are in chunks of 59 * 3 x 32bit registers to cover all 95 GPIOs 60 * 61 * per gpio specific registers consist of two 32bit registers per gpio 62 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 63 * 190 config registers. 64 * 65 * A simplified view of the register layout look like this: 66 * 67 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 68 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 69 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 70 * ... 71 * LP_INT_ENABLE[31:0] ... 72 * LP_INT_ENABLE[63:32] ... 73 * LP_INT_ENABLE[94:64] ... 74 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 75 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 76 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 77 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 78 * LP2_CONFIG1 (gpio 2) ... 79 * LP2_CONFIG2 (gpio 2) ... 80 * ... 81 * LP94_CONFIG1 (gpio 94) ... 82 * LP94_CONFIG2 (gpio 94) ... 83 */ 84 85 static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset, 86 int reg) 87 { 88 struct lp_gpio *lg = gpiochip_get_data(chip); 89 int reg_offset; 90 91 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 92 /* per gpio specific config registers */ 93 reg_offset = offset * 8; 94 else 95 /* bitmapped registers */ 96 reg_offset = (offset / 32) * 4; 97 98 return lg->reg_base + reg + reg_offset; 99 } 100 101 static int lp_gpio_request(struct gpio_chip *chip, unsigned offset) 102 { 103 struct lp_gpio *lg = gpiochip_get_data(chip); 104 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 105 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 106 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED); 107 u32 value; 108 109 pm_runtime_get(lg->dev); /* should we put if failed */ 110 111 /* Fail if BIOS reserved pin for ACPI use */ 112 if (!(inl(acpi_use) & BIT(offset % 32))) { 113 dev_err(lg->dev, "gpio %d reserved for ACPI\n", offset); 114 return -EBUSY; 115 } 116 117 /* 118 * Reconfigure pin to GPIO mode if needed and issue a warning, 119 * since we expect firmware to configure it properly. 120 */ 121 value = inl(reg); 122 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 123 outl((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 124 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); 125 } 126 127 /* enable input sensing */ 128 outl(inl(conf2) & ~GPINDIS_BIT, conf2); 129 130 131 return 0; 132 } 133 134 static void lp_gpio_free(struct gpio_chip *chip, unsigned offset) 135 { 136 struct lp_gpio *lg = gpiochip_get_data(chip); 137 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 138 139 /* disable input sensing */ 140 outl(inl(conf2) | GPINDIS_BIT, conf2); 141 142 pm_runtime_put(lg->dev); 143 } 144 145 static int lp_irq_type(struct irq_data *d, unsigned type) 146 { 147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 148 struct lp_gpio *lg = gpiochip_get_data(gc); 149 u32 hwirq = irqd_to_hwirq(d); 150 unsigned long flags; 151 u32 value; 152 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 153 154 if (hwirq >= lg->chip.ngpio) 155 return -EINVAL; 156 157 raw_spin_lock_irqsave(&lg->lock, flags); 158 value = inl(reg); 159 160 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 161 if (type & IRQ_TYPE_EDGE_RISING) 162 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 163 164 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 165 if (type & IRQ_TYPE_EDGE_FALLING) 166 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 167 168 /* TRIG_SEL bit 1, INV bit 0 for level low */ 169 if (type & IRQ_TYPE_LEVEL_LOW) 170 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 171 172 /* TRIG_SEL bit 1, INV bit 1 for level high */ 173 if (type & IRQ_TYPE_LEVEL_HIGH) 174 value |= TRIG_SEL_BIT | INT_INV_BIT; 175 176 outl(value, reg); 177 178 if (type & IRQ_TYPE_EDGE_BOTH) 179 irq_set_handler_locked(d, handle_edge_irq); 180 else if (type & IRQ_TYPE_LEVEL_MASK) 181 irq_set_handler_locked(d, handle_level_irq); 182 183 raw_spin_unlock_irqrestore(&lg->lock, flags); 184 185 return 0; 186 } 187 188 static int lp_gpio_get(struct gpio_chip *chip, unsigned offset) 189 { 190 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 191 return !!(inl(reg) & IN_LVL_BIT); 192 } 193 194 static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 195 { 196 struct lp_gpio *lg = gpiochip_get_data(chip); 197 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 198 unsigned long flags; 199 200 raw_spin_lock_irqsave(&lg->lock, flags); 201 202 if (value) 203 outl(inl(reg) | OUT_LVL_BIT, reg); 204 else 205 outl(inl(reg) & ~OUT_LVL_BIT, reg); 206 207 raw_spin_unlock_irqrestore(&lg->lock, flags); 208 } 209 210 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 211 { 212 struct lp_gpio *lg = gpiochip_get_data(chip); 213 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 214 unsigned long flags; 215 216 raw_spin_lock_irqsave(&lg->lock, flags); 217 outl(inl(reg) | DIR_BIT, reg); 218 raw_spin_unlock_irqrestore(&lg->lock, flags); 219 220 return 0; 221 } 222 223 static int lp_gpio_direction_output(struct gpio_chip *chip, 224 unsigned offset, int value) 225 { 226 struct lp_gpio *lg = gpiochip_get_data(chip); 227 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 228 unsigned long flags; 229 230 lp_gpio_set(chip, offset, value); 231 232 raw_spin_lock_irqsave(&lg->lock, flags); 233 outl(inl(reg) & ~DIR_BIT, reg); 234 raw_spin_unlock_irqrestore(&lg->lock, flags); 235 236 return 0; 237 } 238 239 static void lp_gpio_irq_handler(struct irq_desc *desc) 240 { 241 struct irq_data *data = irq_desc_get_irq_data(desc); 242 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 243 struct lp_gpio *lg = gpiochip_get_data(gc); 244 struct irq_chip *chip = irq_data_get_irq_chip(data); 245 unsigned long reg, ena, pending; 246 u32 base, pin; 247 248 /* check from GPIO controller which pin triggered the interrupt */ 249 for (base = 0; base < lg->chip.ngpio; base += 32) { 250 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 251 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 252 253 /* Only interrupts that are enabled */ 254 pending = inl(reg) & inl(ena); 255 256 for_each_set_bit(pin, &pending, 32) { 257 unsigned irq; 258 259 /* Clear before handling so we don't lose an edge */ 260 outl(BIT(pin), reg); 261 262 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 263 generic_handle_irq(irq); 264 } 265 } 266 chip->irq_eoi(data); 267 } 268 269 static void lp_irq_unmask(struct irq_data *d) 270 { 271 } 272 273 static void lp_irq_mask(struct irq_data *d) 274 { 275 } 276 277 static void lp_irq_enable(struct irq_data *d) 278 { 279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 280 struct lp_gpio *lg = gpiochip_get_data(gc); 281 u32 hwirq = irqd_to_hwirq(d); 282 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 283 unsigned long flags; 284 285 raw_spin_lock_irqsave(&lg->lock, flags); 286 outl(inl(reg) | BIT(hwirq % 32), reg); 287 raw_spin_unlock_irqrestore(&lg->lock, flags); 288 } 289 290 static void lp_irq_disable(struct irq_data *d) 291 { 292 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 293 struct lp_gpio *lg = gpiochip_get_data(gc); 294 u32 hwirq = irqd_to_hwirq(d); 295 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 296 unsigned long flags; 297 298 raw_spin_lock_irqsave(&lg->lock, flags); 299 outl(inl(reg) & ~BIT(hwirq % 32), reg); 300 raw_spin_unlock_irqrestore(&lg->lock, flags); 301 } 302 303 static struct irq_chip lp_irqchip = { 304 .name = "LP-GPIO", 305 .irq_mask = lp_irq_mask, 306 .irq_unmask = lp_irq_unmask, 307 .irq_enable = lp_irq_enable, 308 .irq_disable = lp_irq_disable, 309 .irq_set_type = lp_irq_type, 310 .flags = IRQCHIP_SKIP_SET_WAKE, 311 }; 312 313 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 314 { 315 struct lp_gpio *lg = gpiochip_get_data(chip); 316 unsigned long reg; 317 unsigned base; 318 319 for (base = 0; base < lg->chip.ngpio; base += 32) { 320 /* disable gpio pin interrupts */ 321 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 322 outl(0, reg); 323 /* Clear interrupt status register */ 324 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 325 outl(0xffffffff, reg); 326 } 327 328 return 0; 329 } 330 331 static int lp_gpio_probe(struct platform_device *pdev) 332 { 333 struct lp_gpio *lg; 334 struct gpio_chip *gc; 335 struct resource *io_rc, *irq_rc; 336 struct device *dev = &pdev->dev; 337 unsigned long reg_len; 338 int ret; 339 340 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 341 if (!lg) 342 return -ENOMEM; 343 344 lg->dev = dev; 345 platform_set_drvdata(pdev, lg); 346 347 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 348 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 349 350 if (!io_rc) { 351 dev_err(dev, "missing IO resources\n"); 352 return -EINVAL; 353 } 354 355 lg->reg_base = io_rc->start; 356 reg_len = resource_size(io_rc); 357 358 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { 359 dev_err(dev, "failed requesting IO region %pR\n", &io_rc); 360 return -EBUSY; 361 } 362 363 raw_spin_lock_init(&lg->lock); 364 365 gc = &lg->chip; 366 gc->label = dev_name(dev); 367 gc->owner = THIS_MODULE; 368 gc->request = lp_gpio_request; 369 gc->free = lp_gpio_free; 370 gc->direction_input = lp_gpio_direction_input; 371 gc->direction_output = lp_gpio_direction_output; 372 gc->get = lp_gpio_get; 373 gc->set = lp_gpio_set; 374 gc->base = -1; 375 gc->ngpio = LP_NUM_GPIO; 376 gc->can_sleep = false; 377 gc->parent = dev; 378 379 /* set up interrupts */ 380 if (irq_rc && irq_rc->start) { 381 struct gpio_irq_chip *girq; 382 383 girq = &gc->irq; 384 girq->chip = &lp_irqchip; 385 girq->init_hw = lp_gpio_irq_init_hw; 386 girq->parent_handler = lp_gpio_irq_handler; 387 girq->num_parents = 1; 388 girq->parents = devm_kcalloc(dev, girq->num_parents, 389 sizeof(*girq->parents), 390 GFP_KERNEL); 391 if (!girq->parents) 392 return -ENOMEM; 393 girq->parents[0] = (unsigned)irq_rc->start; 394 girq->default_type = IRQ_TYPE_NONE; 395 girq->handler = handle_bad_irq; 396 } 397 398 ret = devm_gpiochip_add_data(dev, gc, lg); 399 if (ret) { 400 dev_err(dev, "failed adding lp-gpio chip\n"); 401 return ret; 402 } 403 404 pm_runtime_enable(dev); 405 406 return 0; 407 } 408 409 static int lp_gpio_runtime_suspend(struct device *dev) 410 { 411 return 0; 412 } 413 414 static int lp_gpio_runtime_resume(struct device *dev) 415 { 416 return 0; 417 } 418 419 static int lp_gpio_resume(struct device *dev) 420 { 421 struct lp_gpio *lg = dev_get_drvdata(dev); 422 unsigned long reg; 423 int i; 424 425 /* on some hardware suspend clears input sensing, re-enable it here */ 426 for (i = 0; i < lg->chip.ngpio; i++) { 427 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 428 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 429 outl(inl(reg) & ~GPINDIS_BIT, reg); 430 } 431 } 432 return 0; 433 } 434 435 static const struct dev_pm_ops lp_gpio_pm_ops = { 436 .runtime_suspend = lp_gpio_runtime_suspend, 437 .runtime_resume = lp_gpio_runtime_resume, 438 .resume = lp_gpio_resume, 439 }; 440 441 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 442 { "INT33C7", 0 }, 443 { "INT3437", 0 }, 444 { } 445 }; 446 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 447 448 static int lp_gpio_remove(struct platform_device *pdev) 449 { 450 pm_runtime_disable(&pdev->dev); 451 return 0; 452 } 453 454 static struct platform_driver lp_gpio_driver = { 455 .probe = lp_gpio_probe, 456 .remove = lp_gpio_remove, 457 .driver = { 458 .name = "lp_gpio", 459 .pm = &lp_gpio_pm_ops, 460 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 461 }, 462 }; 463 464 static int __init lp_gpio_init(void) 465 { 466 return platform_driver_register(&lp_gpio_driver); 467 } 468 469 static void __exit lp_gpio_exit(void) 470 { 471 platform_driver_unregister(&lp_gpio_driver); 472 } 473 474 subsys_initcall(lp_gpio_init); 475 module_exit(lp_gpio_exit); 476 477 MODULE_AUTHOR("Mathias Nyman (Intel)"); 478 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); 479 MODULE_LICENSE("GPL v2"); 480 MODULE_ALIAS("platform:lp_gpio"); 481