1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO controller driver for Intel Lynxpoint PCH chipset> 4 * Copyright (c) 2012, Intel Corporation. 5 * 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/slab.h> 19 #include <linux/types.h> 20 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 26 #include "pinctrl-intel.h" 27 28 #define COMMUNITY(p, n) \ 29 { \ 30 .pin_base = (p), \ 31 .npins = (n), \ 32 } 33 34 static const struct pinctrl_pin_desc lptlp_pins[] = { 35 PINCTRL_PIN(0, "GP0_UART1_RXD"), 36 PINCTRL_PIN(1, "GP1_UART1_TXD"), 37 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 38 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 39 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 40 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 41 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 42 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 43 PINCTRL_PIN(8, "GP8"), 44 PINCTRL_PIN(9, "GP9"), 45 PINCTRL_PIN(10, "GP10"), 46 PINCTRL_PIN(11, "GP11_SMBALERTB"), 47 PINCTRL_PIN(12, "GP12_LANPHYPC"), 48 PINCTRL_PIN(13, "GP13"), 49 PINCTRL_PIN(14, "GP14"), 50 PINCTRL_PIN(15, "GP15"), 51 PINCTRL_PIN(16, "GP16_MGPIO9"), 52 PINCTRL_PIN(17, "GP17_MGPIO10"), 53 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 54 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 55 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 56 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 57 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 58 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 59 PINCTRL_PIN(24, "GP24_MGPIO0"), 60 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 61 PINCTRL_PIN(26, "GP26_MGPIO5"), 62 PINCTRL_PIN(27, "GP27_MGPIO6"), 63 PINCTRL_PIN(28, "GP28_MGPIO7"), 64 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 65 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 66 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 67 PINCTRL_PIN(32, "GP32_CLKRUNB"), 68 PINCTRL_PIN(33, "GP33_DEVSLP0"), 69 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 70 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 71 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 72 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 73 PINCTRL_PIN(38, "GP38_DEVSLP1"), 74 PINCTRL_PIN(39, "GP39_DEVSLP2"), 75 PINCTRL_PIN(40, "GP40_OC0B"), 76 PINCTRL_PIN(41, "GP41_OC1B"), 77 PINCTRL_PIN(42, "GP42_OC2B"), 78 PINCTRL_PIN(43, "GP43_OC3B"), 79 PINCTRL_PIN(44, "GP44"), 80 PINCTRL_PIN(45, "GP45_TMS2"), 81 PINCTRL_PIN(46, "GP46_TDO2"), 82 PINCTRL_PIN(47, "GP47"), 83 PINCTRL_PIN(48, "GP48"), 84 PINCTRL_PIN(49, "GP49"), 85 PINCTRL_PIN(50, "GP50"), 86 PINCTRL_PIN(51, "GP51_GSXDOUT"), 87 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 88 PINCTRL_PIN(53, "GP53_GSXDIN"), 89 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 90 PINCTRL_PIN(55, "GP55_GSXCLK"), 91 PINCTRL_PIN(56, "GP56"), 92 PINCTRL_PIN(57, "GP57"), 93 PINCTRL_PIN(58, "GP58"), 94 PINCTRL_PIN(59, "GP59"), 95 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 96 PINCTRL_PIN(61, "GP61_SUS_STATB"), 97 PINCTRL_PIN(62, "GP62_SUSCLK"), 98 PINCTRL_PIN(63, "GP63_SLP_S5B"), 99 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 100 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 101 PINCTRL_PIN(66, "GP66_SDIO_D0"), 102 PINCTRL_PIN(67, "GP67_SDIO_D1"), 103 PINCTRL_PIN(68, "GP68_SDIO_D2"), 104 PINCTRL_PIN(69, "GP69_SDIO_D3"), 105 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 106 PINCTRL_PIN(71, "GP71_MPHYPC"), 107 PINCTRL_PIN(72, "GP72_BATLOWB"), 108 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 109 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 110 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 111 PINCTRL_PIN(76, "GP76_BMBUSYB"), 112 PINCTRL_PIN(77, "GP77_PIRQAB"), 113 PINCTRL_PIN(78, "GP78_PIRQBB"), 114 PINCTRL_PIN(79, "GP79_PIRQCB"), 115 PINCTRL_PIN(80, "GP80_PIRQDB"), 116 PINCTRL_PIN(81, "GP81_SPKR"), 117 PINCTRL_PIN(82, "GP82_RCINB"), 118 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 119 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 120 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 121 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 122 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 123 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 124 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 125 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 126 PINCTRL_PIN(91, "GP91_UART0_RXD"), 127 PINCTRL_PIN(92, "GP92_UART0_TXD"), 128 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 129 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 130 }; 131 132 static const struct intel_community lptlp_communities[] = { 133 COMMUNITY(0, 95), 134 }; 135 136 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 137 .pins = lptlp_pins, 138 .npins = ARRAY_SIZE(lptlp_pins), 139 .communities = lptlp_communities, 140 .ncommunities = ARRAY_SIZE(lptlp_communities), 141 }; 142 143 /* LynxPoint chipset has support for 95 GPIO pins */ 144 145 #define LP_NUM_GPIO 95 146 147 /* Bitmapped register offsets */ 148 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 149 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 150 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 151 #define LP_INT_STAT 0x80 152 #define LP_INT_ENABLE 0x90 153 154 /* Each pin has two 32 bit config registers, starting at 0x100 */ 155 #define LP_CONFIG1 0x100 156 #define LP_CONFIG2 0x104 157 158 /* LP_CONFIG1 reg bits */ 159 #define OUT_LVL_BIT BIT(31) 160 #define IN_LVL_BIT BIT(30) 161 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 162 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 163 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 164 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 165 #define USE_SEL_NATIVE (0 << 0) 166 #define USE_SEL_GPIO (1 << 0) 167 168 /* LP_CONFIG2 reg bits */ 169 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 170 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 171 #define GPIWP_NONE 0 /* none */ 172 #define GPIWP_DOWN 1 /* weak pull down */ 173 #define GPIWP_UP 2 /* weak pull up */ 174 175 /* 176 * Lynxpoint gpios are controlled through both bitmapped registers and 177 * per gpio specific registers. The bitmapped registers are in chunks of 178 * 3 x 32bit registers to cover all 95 GPIOs 179 * 180 * per gpio specific registers consist of two 32bit registers per gpio 181 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 182 * 190 config registers. 183 * 184 * A simplified view of the register layout look like this: 185 * 186 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 187 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 188 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 189 * ... 190 * LP_INT_ENABLE[31:0] ... 191 * LP_INT_ENABLE[63:32] ... 192 * LP_INT_ENABLE[94:64] ... 193 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 194 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 195 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 196 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 197 * LP2_CONFIG1 (gpio 2) ... 198 * LP2_CONFIG2 (gpio 2) ... 199 * ... 200 * LP94_CONFIG1 (gpio 94) ... 201 * LP94_CONFIG2 (gpio 94) ... 202 * 203 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 204 */ 205 206 static struct intel_community *lp_get_community(struct intel_pinctrl *lg, 207 unsigned int pin) 208 { 209 struct intel_community *comm; 210 int i; 211 212 for (i = 0; i < lg->ncommunities; i++) { 213 comm = &lg->communities[i]; 214 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 215 return comm; 216 } 217 218 return NULL; 219 } 220 221 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 222 int reg) 223 { 224 struct intel_pinctrl *lg = gpiochip_get_data(chip); 225 struct intel_community *comm; 226 int reg_offset; 227 228 comm = lp_get_community(lg, offset); 229 if (!comm) 230 return NULL; 231 232 offset -= comm->pin_base; 233 234 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 235 /* per gpio specific config registers */ 236 reg_offset = offset * 8; 237 else 238 /* bitmapped registers */ 239 reg_offset = (offset / 32) * 4; 240 241 return comm->regs + reg_offset + reg; 242 } 243 244 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 245 { 246 void __iomem *acpi_use; 247 248 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 249 if (!acpi_use) 250 return true; 251 252 return !(ioread32(acpi_use) & BIT(pin % 32)); 253 } 254 255 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 256 { 257 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 258 u32 value; 259 260 value = ioread32(ioxapic_use); 261 262 if (offset >= 8 && offset <= 10) 263 return !!(value & BIT(offset - 8 + 0)); 264 if (offset >= 13 && offset <= 14) 265 return !!(value & BIT(offset - 13 + 3)); 266 if (offset >= 45 && offset <= 55) 267 return !!(value & BIT(offset - 45 + 5)); 268 269 return false; 270 } 271 272 static int lp_get_groups_count(struct pinctrl_dev *pctldev) 273 { 274 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 275 276 return lg->soc->ngroups; 277 } 278 279 static const char *lp_get_group_name(struct pinctrl_dev *pctldev, 280 unsigned int selector) 281 { 282 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 283 284 return lg->soc->groups[selector].name; 285 } 286 287 static int lp_get_group_pins(struct pinctrl_dev *pctldev, 288 unsigned int selector, 289 const unsigned int **pins, 290 unsigned int *num_pins) 291 { 292 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 293 294 *pins = lg->soc->groups[selector].pins; 295 *num_pins = lg->soc->groups[selector].npins; 296 297 return 0; 298 } 299 300 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 301 unsigned int pin) 302 { 303 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 304 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 305 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 306 u32 value, mode; 307 308 value = ioread32(reg); 309 310 mode = value & USE_SEL_MASK; 311 if (mode == USE_SEL_GPIO) 312 seq_puts(s, "GPIO "); 313 else 314 seq_printf(s, "mode %d ", mode); 315 316 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 317 318 if (lp_gpio_acpi_use(lg, pin)) 319 seq_puts(s, " [ACPI]"); 320 } 321 322 static const struct pinctrl_ops lptlp_pinctrl_ops = { 323 .get_groups_count = lp_get_groups_count, 324 .get_group_name = lp_get_group_name, 325 .get_group_pins = lp_get_group_pins, 326 .pin_dbg_show = lp_pin_dbg_show, 327 }; 328 329 static int lp_get_functions_count(struct pinctrl_dev *pctldev) 330 { 331 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 332 333 return lg->soc->nfunctions; 334 } 335 336 static const char *lp_get_function_name(struct pinctrl_dev *pctldev, 337 unsigned int selector) 338 { 339 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 340 341 return lg->soc->functions[selector].name; 342 } 343 344 static int lp_get_function_groups(struct pinctrl_dev *pctldev, 345 unsigned int selector, 346 const char * const **groups, 347 unsigned int *num_groups) 348 { 349 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 350 351 *groups = lg->soc->functions[selector].groups; 352 *num_groups = lg->soc->functions[selector].ngroups; 353 354 return 0; 355 } 356 357 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 358 unsigned int function, unsigned int group) 359 { 360 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 361 const struct intel_pingroup *grp = &lg->soc->groups[group]; 362 unsigned long flags; 363 int i; 364 365 raw_spin_lock_irqsave(&lg->lock, flags); 366 367 /* Now enable the mux setting for each pin in the group */ 368 for (i = 0; i < grp->npins; i++) { 369 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); 370 u32 value; 371 372 value = ioread32(reg); 373 374 value &= ~USE_SEL_MASK; 375 if (grp->modes) 376 value |= grp->modes[i]; 377 else 378 value |= grp->mode; 379 380 iowrite32(value, reg); 381 } 382 383 raw_spin_unlock_irqrestore(&lg->lock, flags); 384 385 return 0; 386 } 387 388 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 389 struct pinctrl_gpio_range *range, 390 unsigned int pin) 391 { 392 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 393 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 394 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 395 unsigned long flags; 396 u32 value; 397 398 pm_runtime_get(lg->dev); 399 400 raw_spin_lock_irqsave(&lg->lock, flags); 401 402 /* 403 * Reconfigure pin to GPIO mode if needed and issue a warning, 404 * since we expect firmware to configure it properly. 405 */ 406 value = ioread32(reg); 407 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 408 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 409 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 410 } 411 412 /* Enable input sensing */ 413 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 414 415 raw_spin_unlock_irqrestore(&lg->lock, flags); 416 417 return 0; 418 } 419 420 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 421 struct pinctrl_gpio_range *range, 422 unsigned int pin) 423 { 424 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 425 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 426 unsigned long flags; 427 428 raw_spin_lock_irqsave(&lg->lock, flags); 429 430 /* Disable input sensing */ 431 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 432 433 raw_spin_unlock_irqrestore(&lg->lock, flags); 434 435 pm_runtime_put(lg->dev); 436 } 437 438 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 439 struct pinctrl_gpio_range *range, 440 unsigned int pin, bool input) 441 { 442 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 443 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 444 unsigned long flags; 445 u32 value; 446 447 raw_spin_lock_irqsave(&lg->lock, flags); 448 449 value = ioread32(reg); 450 value &= ~DIR_BIT; 451 if (input) { 452 value |= DIR_BIT; 453 } else { 454 /* 455 * Before making any direction modifications, do a check if GPIO 456 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 457 * does not make sense, so let's at least warn the caller before 458 * they shoot themselves in the foot. 459 */ 460 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 461 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 462 } 463 iowrite32(value, reg); 464 465 raw_spin_unlock_irqrestore(&lg->lock, flags); 466 467 return 0; 468 } 469 470 static const struct pinmux_ops lptlp_pinmux_ops = { 471 .get_functions_count = lp_get_functions_count, 472 .get_function_name = lp_get_function_name, 473 .get_function_groups = lp_get_function_groups, 474 .set_mux = lp_pinmux_set_mux, 475 .gpio_request_enable = lp_gpio_request_enable, 476 .gpio_disable_free = lp_gpio_disable_free, 477 .gpio_set_direction = lp_gpio_set_direction, 478 }; 479 480 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 481 unsigned long *config) 482 { 483 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 484 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 485 enum pin_config_param param = pinconf_to_config_param(*config); 486 unsigned long flags; 487 u32 value, pull; 488 u16 arg = 0; 489 490 raw_spin_lock_irqsave(&lg->lock, flags); 491 value = ioread32(conf2); 492 raw_spin_unlock_irqrestore(&lg->lock, flags); 493 494 pull = value & GPIWP_MASK; 495 496 switch (param) { 497 case PIN_CONFIG_BIAS_DISABLE: 498 if (pull) 499 return -EINVAL; 500 break; 501 case PIN_CONFIG_BIAS_PULL_DOWN: 502 if (pull != GPIWP_DOWN) 503 return -EINVAL; 504 505 arg = 1; 506 break; 507 case PIN_CONFIG_BIAS_PULL_UP: 508 if (pull != GPIWP_UP) 509 return -EINVAL; 510 511 arg = 1; 512 break; 513 default: 514 return -ENOTSUPP; 515 } 516 517 *config = pinconf_to_config_packed(param, arg); 518 519 return 0; 520 } 521 522 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 523 unsigned long *configs, unsigned int num_configs) 524 { 525 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 526 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 527 enum pin_config_param param; 528 unsigned long flags; 529 int i, ret = 0; 530 u32 value; 531 532 raw_spin_lock_irqsave(&lg->lock, flags); 533 534 value = ioread32(conf2); 535 536 for (i = 0; i < num_configs; i++) { 537 param = pinconf_to_config_param(configs[i]); 538 539 switch (param) { 540 case PIN_CONFIG_BIAS_DISABLE: 541 value &= ~GPIWP_MASK; 542 break; 543 case PIN_CONFIG_BIAS_PULL_DOWN: 544 value &= ~GPIWP_MASK; 545 value |= GPIWP_DOWN; 546 break; 547 case PIN_CONFIG_BIAS_PULL_UP: 548 value &= ~GPIWP_MASK; 549 value |= GPIWP_UP; 550 break; 551 default: 552 ret = -ENOTSUPP; 553 } 554 555 if (ret) 556 break; 557 } 558 559 if (!ret) 560 iowrite32(value, conf2); 561 562 raw_spin_unlock_irqrestore(&lg->lock, flags); 563 564 return ret; 565 } 566 567 static const struct pinconf_ops lptlp_pinconf_ops = { 568 .is_generic = true, 569 .pin_config_get = lp_pin_config_get, 570 .pin_config_set = lp_pin_config_set, 571 }; 572 573 static const struct pinctrl_desc lptlp_pinctrl_desc = { 574 .pctlops = &lptlp_pinctrl_ops, 575 .pmxops = &lptlp_pinmux_ops, 576 .confops = &lptlp_pinconf_ops, 577 .owner = THIS_MODULE, 578 }; 579 580 static int lp_gpio_request(struct gpio_chip *chip, unsigned int offset) 581 { 582 struct intel_pinctrl *lg = gpiochip_get_data(chip); 583 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 584 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 585 u32 value; 586 587 pm_runtime_get(lg->dev); /* should we put if failed */ 588 589 /* 590 * Reconfigure pin to GPIO mode if needed and issue a warning, 591 * since we expect firmware to configure it properly. 592 */ 593 value = ioread32(reg); 594 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 595 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 596 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", offset); 597 } 598 599 /* enable input sensing */ 600 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 601 602 603 return 0; 604 } 605 606 static void lp_gpio_free(struct gpio_chip *chip, unsigned int offset) 607 { 608 struct intel_pinctrl *lg = gpiochip_get_data(chip); 609 void __iomem *conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2); 610 611 /* disable input sensing */ 612 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 613 614 pm_runtime_put(lg->dev); 615 } 616 617 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 618 { 619 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 620 return !!(ioread32(reg) & IN_LVL_BIT); 621 } 622 623 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 624 { 625 struct intel_pinctrl *lg = gpiochip_get_data(chip); 626 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 627 unsigned long flags; 628 629 raw_spin_lock_irqsave(&lg->lock, flags); 630 631 if (value) 632 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 633 else 634 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 635 636 raw_spin_unlock_irqrestore(&lg->lock, flags); 637 } 638 639 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 640 { 641 struct intel_pinctrl *lg = gpiochip_get_data(chip); 642 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 643 unsigned long flags; 644 645 raw_spin_lock_irqsave(&lg->lock, flags); 646 iowrite32(ioread32(reg) | DIR_BIT, reg); 647 raw_spin_unlock_irqrestore(&lg->lock, flags); 648 649 return 0; 650 } 651 652 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 653 int value) 654 { 655 struct intel_pinctrl *lg = gpiochip_get_data(chip); 656 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 657 unsigned long flags; 658 659 lp_gpio_set(chip, offset, value); 660 661 raw_spin_lock_irqsave(&lg->lock, flags); 662 iowrite32(ioread32(reg) & ~DIR_BIT, reg); 663 raw_spin_unlock_irqrestore(&lg->lock, flags); 664 665 return 0; 666 } 667 668 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 669 { 670 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 671 672 if (ioread32(reg) & DIR_BIT) 673 return GPIO_LINE_DIRECTION_IN; 674 675 return GPIO_LINE_DIRECTION_OUT; 676 } 677 678 static void lp_gpio_irq_handler(struct irq_desc *desc) 679 { 680 struct irq_data *data = irq_desc_get_irq_data(desc); 681 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 682 struct intel_pinctrl *lg = gpiochip_get_data(gc); 683 struct irq_chip *chip = irq_data_get_irq_chip(data); 684 void __iomem *reg, *ena; 685 unsigned long pending; 686 u32 base, pin; 687 688 /* check from GPIO controller which pin triggered the interrupt */ 689 for (base = 0; base < lg->chip.ngpio; base += 32) { 690 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 691 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 692 693 /* Only interrupts that are enabled */ 694 pending = ioread32(reg) & ioread32(ena); 695 696 for_each_set_bit(pin, &pending, 32) { 697 unsigned int irq; 698 699 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 700 generic_handle_irq(irq); 701 } 702 } 703 chip->irq_eoi(data); 704 } 705 706 static void lp_irq_ack(struct irq_data *d) 707 { 708 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 709 struct intel_pinctrl *lg = gpiochip_get_data(gc); 710 u32 hwirq = irqd_to_hwirq(d); 711 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 712 unsigned long flags; 713 714 raw_spin_lock_irqsave(&lg->lock, flags); 715 iowrite32(BIT(hwirq % 32), reg); 716 raw_spin_unlock_irqrestore(&lg->lock, flags); 717 } 718 719 static void lp_irq_unmask(struct irq_data *d) 720 { 721 } 722 723 static void lp_irq_mask(struct irq_data *d) 724 { 725 } 726 727 static void lp_irq_enable(struct irq_data *d) 728 { 729 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 730 struct intel_pinctrl *lg = gpiochip_get_data(gc); 731 u32 hwirq = irqd_to_hwirq(d); 732 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 733 unsigned long flags; 734 735 raw_spin_lock_irqsave(&lg->lock, flags); 736 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 737 raw_spin_unlock_irqrestore(&lg->lock, flags); 738 } 739 740 static void lp_irq_disable(struct irq_data *d) 741 { 742 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 743 struct intel_pinctrl *lg = gpiochip_get_data(gc); 744 u32 hwirq = irqd_to_hwirq(d); 745 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 746 unsigned long flags; 747 748 raw_spin_lock_irqsave(&lg->lock, flags); 749 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 750 raw_spin_unlock_irqrestore(&lg->lock, flags); 751 } 752 753 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 754 { 755 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 756 struct intel_pinctrl *lg = gpiochip_get_data(gc); 757 u32 hwirq = irqd_to_hwirq(d); 758 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 759 unsigned long flags; 760 u32 value; 761 762 if (hwirq >= lg->chip.ngpio) 763 return -EINVAL; 764 765 /* Fail if BIOS reserved pin for ACPI use */ 766 if (lp_gpio_acpi_use(lg, hwirq)) { 767 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); 768 return -EBUSY; 769 } 770 771 raw_spin_lock_irqsave(&lg->lock, flags); 772 value = ioread32(reg); 773 774 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 775 if (type & IRQ_TYPE_EDGE_RISING) 776 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 777 778 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 779 if (type & IRQ_TYPE_EDGE_FALLING) 780 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 781 782 /* TRIG_SEL bit 1, INV bit 0 for level low */ 783 if (type & IRQ_TYPE_LEVEL_LOW) 784 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 785 786 /* TRIG_SEL bit 1, INV bit 1 for level high */ 787 if (type & IRQ_TYPE_LEVEL_HIGH) 788 value |= TRIG_SEL_BIT | INT_INV_BIT; 789 790 iowrite32(value, reg); 791 792 if (type & IRQ_TYPE_EDGE_BOTH) 793 irq_set_handler_locked(d, handle_edge_irq); 794 else if (type & IRQ_TYPE_LEVEL_MASK) 795 irq_set_handler_locked(d, handle_level_irq); 796 797 raw_spin_unlock_irqrestore(&lg->lock, flags); 798 799 return 0; 800 } 801 802 static struct irq_chip lp_irqchip = { 803 .name = "LP-GPIO", 804 .irq_ack = lp_irq_ack, 805 .irq_mask = lp_irq_mask, 806 .irq_unmask = lp_irq_unmask, 807 .irq_enable = lp_irq_enable, 808 .irq_disable = lp_irq_disable, 809 .irq_set_type = lp_irq_set_type, 810 .flags = IRQCHIP_SKIP_SET_WAKE, 811 }; 812 813 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 814 { 815 struct intel_pinctrl *lg = gpiochip_get_data(chip); 816 void __iomem *reg; 817 unsigned int base; 818 819 for (base = 0; base < lg->chip.ngpio; base += 32) { 820 /* disable gpio pin interrupts */ 821 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 822 iowrite32(0, reg); 823 /* Clear interrupt status register */ 824 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 825 iowrite32(0xffffffff, reg); 826 } 827 828 return 0; 829 } 830 831 static int lp_gpio_probe(struct platform_device *pdev) 832 { 833 const struct intel_pinctrl_soc_data *soc; 834 struct intel_pinctrl *lg; 835 struct gpio_chip *gc; 836 struct resource *io_rc, *irq_rc; 837 struct device *dev = &pdev->dev; 838 void __iomem *regs; 839 unsigned int i; 840 int ret; 841 842 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 843 if (!soc) 844 return -ENODEV; 845 846 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 847 if (!lg) 848 return -ENOMEM; 849 850 lg->dev = dev; 851 lg->soc = soc; 852 853 lg->ncommunities = lg->soc->ncommunities; 854 lg->communities = devm_kcalloc(dev, lg->ncommunities, 855 sizeof(*lg->communities), GFP_KERNEL); 856 if (!lg->communities) 857 return -ENOMEM; 858 859 lg->pctldesc = lptlp_pinctrl_desc; 860 lg->pctldesc.name = dev_name(dev); 861 lg->pctldesc.pins = lg->soc->pins; 862 lg->pctldesc.npins = lg->soc->npins; 863 864 platform_set_drvdata(pdev, lg); 865 866 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 867 if (!io_rc) { 868 dev_err(dev, "missing IO resources\n"); 869 return -EINVAL; 870 } 871 872 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 873 if (!regs) { 874 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 875 return -EBUSY; 876 } 877 878 for (i = 0; i < lg->soc->ncommunities; i++) { 879 struct intel_community *comm = &lg->communities[i]; 880 881 *comm = lg->soc->communities[i]; 882 883 comm->regs = regs; 884 comm->pad_regs = regs + 0x100; 885 } 886 887 raw_spin_lock_init(&lg->lock); 888 889 gc = &lg->chip; 890 gc->label = dev_name(dev); 891 gc->owner = THIS_MODULE; 892 gc->request = lp_gpio_request; 893 gc->free = lp_gpio_free; 894 gc->direction_input = lp_gpio_direction_input; 895 gc->direction_output = lp_gpio_direction_output; 896 gc->get = lp_gpio_get; 897 gc->set = lp_gpio_set; 898 gc->get_direction = lp_gpio_get_direction; 899 gc->base = -1; 900 gc->ngpio = LP_NUM_GPIO; 901 gc->can_sleep = false; 902 gc->parent = dev; 903 904 /* set up interrupts */ 905 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 906 if (irq_rc && irq_rc->start) { 907 struct gpio_irq_chip *girq; 908 909 girq = &gc->irq; 910 girq->chip = &lp_irqchip; 911 girq->init_hw = lp_gpio_irq_init_hw; 912 girq->parent_handler = lp_gpio_irq_handler; 913 girq->num_parents = 1; 914 girq->parents = devm_kcalloc(dev, girq->num_parents, 915 sizeof(*girq->parents), 916 GFP_KERNEL); 917 if (!girq->parents) 918 return -ENOMEM; 919 girq->parents[0] = (unsigned int)irq_rc->start; 920 girq->default_type = IRQ_TYPE_NONE; 921 girq->handler = handle_bad_irq; 922 } 923 924 ret = devm_gpiochip_add_data(dev, gc, lg); 925 if (ret) { 926 dev_err(dev, "failed adding lp-gpio chip\n"); 927 return ret; 928 } 929 930 pm_runtime_enable(dev); 931 932 return 0; 933 } 934 935 static int lp_gpio_remove(struct platform_device *pdev) 936 { 937 pm_runtime_disable(&pdev->dev); 938 return 0; 939 } 940 941 static int lp_gpio_runtime_suspend(struct device *dev) 942 { 943 return 0; 944 } 945 946 static int lp_gpio_runtime_resume(struct device *dev) 947 { 948 return 0; 949 } 950 951 static int lp_gpio_resume(struct device *dev) 952 { 953 struct intel_pinctrl *lg = dev_get_drvdata(dev); 954 void __iomem *reg; 955 int i; 956 957 /* on some hardware suspend clears input sensing, re-enable it here */ 958 for (i = 0; i < lg->chip.ngpio; i++) { 959 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 960 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 961 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 962 } 963 } 964 return 0; 965 } 966 967 static const struct dev_pm_ops lp_gpio_pm_ops = { 968 .runtime_suspend = lp_gpio_runtime_suspend, 969 .runtime_resume = lp_gpio_runtime_resume, 970 .resume = lp_gpio_resume, 971 }; 972 973 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 974 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 975 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 976 { } 977 }; 978 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 979 980 static struct platform_driver lp_gpio_driver = { 981 .probe = lp_gpio_probe, 982 .remove = lp_gpio_remove, 983 .driver = { 984 .name = "lp_gpio", 985 .pm = &lp_gpio_pm_ops, 986 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 987 }, 988 }; 989 990 static int __init lp_gpio_init(void) 991 { 992 return platform_driver_register(&lp_gpio_driver); 993 } 994 995 static void __exit lp_gpio_exit(void) 996 { 997 platform_driver_unregister(&lp_gpio_driver); 998 } 999 1000 subsys_initcall(lp_gpio_init); 1001 module_exit(lp_gpio_exit); 1002 1003 MODULE_AUTHOR("Mathias Nyman (Intel)"); 1004 MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint"); 1005 MODULE_LICENSE("GPL v2"); 1006 MODULE_ALIAS("platform:lp_gpio"); 1007