1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Core pinctrl/GPIO driver for Intel GPIO controllers 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #ifndef PINCTRL_INTEL_H 11 #define PINCTRL_INTEL_H 12 13 #include <linux/gpio/driver.h> 14 #include <linux/irq.h> 15 #include <linux/pm.h> 16 #include <linux/spinlock_types.h> 17 18 struct pinctrl_pin_desc; 19 struct platform_device; 20 struct device; 21 22 /** 23 * struct intel_pingroup - Description about group of pins 24 * @name: Name of the groups 25 * @pins: All pins in this group 26 * @npins: Number of pins in this groups 27 * @mode: Native mode in which the group is muxed out @pins. Used if @modes 28 * is %NULL. 29 * @modes: If not %NULL this will hold mode for each pin in @pins 30 */ 31 struct intel_pingroup { 32 const char *name; 33 const unsigned int *pins; 34 size_t npins; 35 unsigned short mode; 36 const unsigned int *modes; 37 }; 38 39 /** 40 * struct intel_function - Description about a function 41 * @name: Name of the function 42 * @groups: An array of groups for this function 43 * @ngroups: Number of groups in @groups 44 */ 45 struct intel_function { 46 const char *name; 47 const char * const *groups; 48 size_t ngroups; 49 }; 50 51 /** 52 * struct intel_padgroup - Hardware pad group information 53 * @reg_num: GPI_IS register number 54 * @base: Starting pin of this group 55 * @size: Size of this group (maximum is 32). 56 * @gpio_base: Starting GPIO base of this group (%0 if matches with @base, 57 * and %-1 if no GPIO mapping should be created) 58 * @padown_num: PAD_OWN register number (assigned by the core driver) 59 * 60 * If pad groups of a community are not the same size, use this structure 61 * to specify them. 62 */ 63 struct intel_padgroup { 64 unsigned int reg_num; 65 unsigned int base; 66 unsigned int size; 67 int gpio_base; 68 unsigned int padown_num; 69 }; 70 71 /** 72 * struct intel_community - Intel pin community description 73 * @barno: MMIO BAR number where registers for this community reside 74 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 75 * then there is no support for owner. 76 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then 77 * locking is not supported. 78 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it 79 * is assumed that the host owns the pin (rather than 80 * ACPI). 81 * @is_offset: Register offset of GPI_IS from @regs. 82 * @ie_offset: Register offset of GPI_IE from @regs. 83 * @features: Additional features supported by the hardware 84 * @pin_base: Starting pin of pins in this community 85 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, 86 * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. 87 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at 88 * minimum. Use %0 if the number of registers can be 89 * determined by the size of the group. 90 * @npins: Number of pins in this community 91 * @gpps: Pad groups if the controller has variable size pad groups 92 * @ngpps: Number of pad groups in this community 93 * @pad_map: Optional non-linear mapping of the pads 94 * @regs: Community specific common registers (reserved for core driver) 95 * @pad_regs: Community specific pad registers (reserved for core driver) 96 * 97 * Most Intel GPIO host controllers this driver supports each pad group is 98 * of equal size (except the last one). In that case the driver can just 99 * fill in @gpp_size field and let the core driver to handle the rest. If 100 * the controller has pad groups of variable size the client driver can 101 * pass custom @gpps and @ngpps instead. 102 */ 103 struct intel_community { 104 unsigned int barno; 105 unsigned int padown_offset; 106 unsigned int padcfglock_offset; 107 unsigned int hostown_offset; 108 unsigned int is_offset; 109 unsigned int ie_offset; 110 unsigned int features; 111 unsigned int pin_base; 112 unsigned int gpp_size; 113 unsigned int gpp_num_padown_regs; 114 size_t npins; 115 const struct intel_padgroup *gpps; 116 size_t ngpps; 117 const unsigned int *pad_map; 118 /* Reserved for the core driver */ 119 void __iomem *regs; 120 void __iomem *pad_regs; 121 }; 122 123 /* Additional features supported by the hardware */ 124 #define PINCTRL_FEATURE_DEBOUNCE BIT(0) 125 #define PINCTRL_FEATURE_1K_PD BIT(1) 126 127 /** 128 * PIN_GROUP - Declare a pin group 129 * @n: Name of the group 130 * @p: An array of pins this group consists 131 * @m: Mode which the pins are put when this group is active. Can be either 132 * a single integer or an array of integers in which case mode is per 133 * pin. 134 */ 135 #define PIN_GROUP(n, p, m) \ 136 { \ 137 .name = (n), \ 138 .pins = (p), \ 139 .npins = ARRAY_SIZE((p)), \ 140 .mode = __builtin_choose_expr( \ 141 __builtin_constant_p((m)), (m), 0), \ 142 .modes = __builtin_choose_expr( \ 143 __builtin_constant_p((m)), NULL, (m)), \ 144 } 145 146 #define FUNCTION(n, g) \ 147 { \ 148 .name = (n), \ 149 .groups = (g), \ 150 .ngroups = ARRAY_SIZE((g)), \ 151 } 152 153 /** 154 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration 155 * @uid: ACPI _UID for the probe driver use if needed 156 * @pins: Array if pins this pinctrl controls 157 * @npins: Number of pins in the array 158 * @groups: Array of pin groups 159 * @ngroups: Number of groups in the array 160 * @functions: Array of functions 161 * @nfunctions: Number of functions in the array 162 * @communities: Array of communities this pinctrl handles 163 * @ncommunities: Number of communities in the array 164 * 165 * The @communities is used as a template by the core driver. It will make 166 * copy of all communities and fill in rest of the information. 167 */ 168 struct intel_pinctrl_soc_data { 169 const char *uid; 170 const struct pinctrl_pin_desc *pins; 171 size_t npins; 172 const struct intel_pingroup *groups; 173 size_t ngroups; 174 const struct intel_function *functions; 175 size_t nfunctions; 176 const struct intel_community *communities; 177 size_t ncommunities; 178 }; 179 180 struct intel_pad_context; 181 struct intel_community_context; 182 183 /** 184 * struct intel_pinctrl_context - context to be saved during suspend-resume 185 * @pads: Opaque context per pad (driver dependent) 186 * @communities: Opaque context per community (driver dependent) 187 */ 188 struct intel_pinctrl_context { 189 struct intel_pad_context *pads; 190 struct intel_community_context *communities; 191 }; 192 193 /** 194 * struct intel_pinctrl - Intel pinctrl private structure 195 * @dev: Pointer to the device structure 196 * @lock: Lock to serialize register access 197 * @pctldesc: Pin controller description 198 * @pctldev: Pointer to the pin controller device 199 * @chip: GPIO chip in this pin controller 200 * @irqchip: IRQ chip in this pin controller 201 * @soc: SoC/PCH specific pin configuration data 202 * @communities: All communities in this pin controller 203 * @ncommunities: Number of communities in this pin controller 204 * @context: Configuration saved over system sleep 205 * @irq: pinctrl/GPIO chip irq number 206 */ 207 struct intel_pinctrl { 208 struct device *dev; 209 raw_spinlock_t lock; 210 struct pinctrl_desc pctldesc; 211 struct pinctrl_dev *pctldev; 212 struct gpio_chip chip; 213 struct irq_chip irqchip; 214 const struct intel_pinctrl_soc_data *soc; 215 struct intel_community *communities; 216 size_t ncommunities; 217 struct intel_pinctrl_context context; 218 int irq; 219 }; 220 221 int intel_pinctrl_probe_by_hid(struct platform_device *pdev); 222 int intel_pinctrl_probe_by_uid(struct platform_device *pdev); 223 224 #ifdef CONFIG_PM_SLEEP 225 int intel_pinctrl_suspend_noirq(struct device *dev); 226 int intel_pinctrl_resume_noirq(struct device *dev); 227 #endif 228 229 #define INTEL_PINCTRL_PM_OPS(_name) \ 230 const struct dev_pm_ops _name = { \ 231 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \ 232 intel_pinctrl_resume_noirq) \ 233 } 234 235 #endif /* PINCTRL_INTEL_H */ 236