1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Core pinctrl/GPIO driver for Intel GPIO controllers
4  *
5  * Copyright (C) 2015, Intel Corporation
6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
8  */
9 
10 #ifndef PINCTRL_INTEL_H
11 #define PINCTRL_INTEL_H
12 
13 #include <linux/bits.h>
14 #include <linux/compiler_types.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/pm.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/spinlock_types.h>
21 
22 struct platform_device;
23 struct device;
24 
25 /**
26  * struct intel_pingroup - Description about group of pins
27  * @grp: Generic data of the pin group (name and pins)
28  * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
29  * @modes: If not %NULL this will hold mode for each pin in @pins
30  */
31 struct intel_pingroup {
32 	struct pingroup grp;
33 	unsigned short mode;
34 	const unsigned int *modes;
35 };
36 
37 /**
38  * struct intel_function - Description about a function
39  * @name: Name of the function
40  * @groups: An array of groups for this function
41  * @ngroups: Number of groups in @groups
42  */
43 struct intel_function {
44 	const char *name;
45 	const char * const *groups;
46 	size_t ngroups;
47 };
48 
49 /**
50  * struct intel_padgroup - Hardware pad group information
51  * @reg_num: GPI_IS register number
52  * @base: Starting pin of this group
53  * @size: Size of this group (maximum is 32).
54  * @gpio_base: Starting GPIO base of this group
55  * @padown_num: PAD_OWN register number (assigned by the core driver)
56  *
57  * If pad groups of a community are not the same size, use this structure
58  * to specify them.
59  */
60 struct intel_padgroup {
61 	unsigned int reg_num;
62 	unsigned int base;
63 	unsigned int size;
64 	int gpio_base;
65 	unsigned int padown_num;
66 };
67 
68 /**
69  * enum - Special treatment for GPIO base in pad group
70  *
71  * @INTEL_GPIO_BASE_ZERO:	force GPIO base to be 0
72  * @INTEL_GPIO_BASE_NOMAP:	no GPIO mapping should be created
73  * @INTEL_GPIO_BASE_MATCH:	matches with starting pin number
74  */
75 enum {
76 	INTEL_GPIO_BASE_ZERO	= -2,
77 	INTEL_GPIO_BASE_NOMAP	= -1,
78 	INTEL_GPIO_BASE_MATCH	= 0,
79 };
80 
81 /**
82  * struct intel_community - Intel pin community description
83  * @barno: MMIO BAR number where registers for this community reside
84  * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
85  *                 then there is no support for owner.
86  * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
87  *                     locking is not supported.
88  * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
89  *                  is assumed that the host owns the pin (rather than
90  *                  ACPI).
91  * @is_offset: Register offset of GPI_IS from @regs.
92  * @ie_offset: Register offset of GPI_IE from @regs.
93  * @features: Additional features supported by the hardware
94  * @pin_base: Starting pin of pins in this community
95  * @npins: Number of pins in this community
96  * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
97  *            HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
98  * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
99  *			 minimum. Use %0 if the number of registers can be
100  *			 determined by the size of the group.
101  * @gpps: Pad groups if the controller has variable size pad groups
102  * @ngpps: Number of pad groups in this community
103  * @pad_map: Optional non-linear mapping of the pads
104  * @nirqs: Optional total number of IRQs this community can generate
105  * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
106  * @regs: Community specific common registers (reserved for core driver)
107  * @pad_regs: Community specific pad registers (reserved for core driver)
108  *
109  * In some of Intel GPIO host controllers this driver supports each pad group
110  * is of equal size (except the last one). In that case the driver can just
111  * fill in @gpp_size field and let the core driver to handle the rest. If
112  * the controller has pad groups of variable size the client driver can
113  * pass custom @gpps and @ngpps instead.
114  */
115 struct intel_community {
116 	unsigned int barno;
117 	unsigned int padown_offset;
118 	unsigned int padcfglock_offset;
119 	unsigned int hostown_offset;
120 	unsigned int is_offset;
121 	unsigned int ie_offset;
122 	unsigned int features;
123 	unsigned int pin_base;
124 	size_t npins;
125 	unsigned int gpp_size;
126 	unsigned int gpp_num_padown_regs;
127 	const struct intel_padgroup *gpps;
128 	size_t ngpps;
129 	const unsigned int *pad_map;
130 	unsigned short nirqs;
131 	unsigned short acpi_space_id;
132 
133 	/* Reserved for the core driver */
134 	void __iomem *regs;
135 	void __iomem *pad_regs;
136 };
137 
138 /* Additional features supported by the hardware */
139 #define PINCTRL_FEATURE_DEBOUNCE	BIT(0)
140 #define PINCTRL_FEATURE_1K_PD		BIT(1)
141 #define PINCTRL_FEATURE_GPIO_HW_INFO	BIT(2)
142 #define PINCTRL_FEATURE_PWM		BIT(3)
143 #define PINCTRL_FEATURE_BLINK		BIT(4)
144 #define PINCTRL_FEATURE_EXP		BIT(5)
145 
146 /**
147  * PIN_GROUP - Declare a pin group
148  * @n: Name of the group
149  * @p: An array of pins this group consists
150  * @m: Mode which the pins are put when this group is active. Can be either
151  *     a single integer or an array of integers in which case mode is per
152  *     pin.
153  */
154 #define PIN_GROUP(n, p, m)								\
155 	{										\
156 		.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))),			\
157 		.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0),	\
158 		.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)),	\
159 	}
160 
161 #define FUNCTION(n, g)				\
162 	{					\
163 		.name = (n),			\
164 		.groups = (g),			\
165 		.ngroups = ARRAY_SIZE((g)),	\
166 	}
167 
168 /**
169  * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
170  * @uid: ACPI _UID for the probe driver use if needed
171  * @pins: Array if pins this pinctrl controls
172  * @npins: Number of pins in the array
173  * @groups: Array of pin groups
174  * @ngroups: Number of groups in the array
175  * @functions: Array of functions
176  * @nfunctions: Number of functions in the array
177  * @communities: Array of communities this pinctrl handles
178  * @ncommunities: Number of communities in the array
179  *
180  * The @communities is used as a template by the core driver. It will make
181  * copy of all communities and fill in rest of the information.
182  */
183 struct intel_pinctrl_soc_data {
184 	const char *uid;
185 	const struct pinctrl_pin_desc *pins;
186 	size_t npins;
187 	const struct intel_pingroup *groups;
188 	size_t ngroups;
189 	const struct intel_function *functions;
190 	size_t nfunctions;
191 	const struct intel_community *communities;
192 	size_t ncommunities;
193 };
194 
195 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
196 
197 struct intel_pad_context;
198 struct intel_community_context;
199 
200 /**
201  * struct intel_pinctrl_context - context to be saved during suspend-resume
202  * @pads: Opaque context per pad (driver dependent)
203  * @communities: Opaque context per community (driver dependent)
204  */
205 struct intel_pinctrl_context {
206 	struct intel_pad_context *pads;
207 	struct intel_community_context *communities;
208 };
209 
210 /**
211  * struct intel_pinctrl - Intel pinctrl private structure
212  * @dev: Pointer to the device structure
213  * @lock: Lock to serialize register access
214  * @pctldesc: Pin controller description
215  * @pctldev: Pointer to the pin controller device
216  * @chip: GPIO chip in this pin controller
217  * @soc: SoC/PCH specific pin configuration data
218  * @communities: All communities in this pin controller
219  * @ncommunities: Number of communities in this pin controller
220  * @context: Configuration saved over system sleep
221  * @irq: pinctrl/GPIO chip irq number
222  */
223 struct intel_pinctrl {
224 	struct device *dev;
225 	raw_spinlock_t lock;
226 	struct pinctrl_desc pctldesc;
227 	struct pinctrl_dev *pctldev;
228 	struct gpio_chip chip;
229 	const struct intel_pinctrl_soc_data *soc;
230 	struct intel_community *communities;
231 	size_t ncommunities;
232 	struct intel_pinctrl_context context;
233 	int irq;
234 };
235 
236 int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
237 int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
238 
239 #ifdef CONFIG_PM_SLEEP
240 int intel_pinctrl_suspend_noirq(struct device *dev);
241 int intel_pinctrl_resume_noirq(struct device *dev);
242 #endif
243 
244 #define INTEL_PINCTRL_PM_OPS(_name)					\
245 const struct dev_pm_ops _name = {					\
246 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq,	\
247 				      intel_pinctrl_resume_noirq)	\
248 }
249 
250 #endif /* PINCTRL_INTEL_H */
251