1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Core pinctrl/GPIO driver for Intel GPIO controllers
4  *
5  * Copyright (C) 2015, Intel Corporation
6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
8  */
9 
10 #ifndef PINCTRL_INTEL_H
11 #define PINCTRL_INTEL_H
12 
13 #include <linux/pm.h>
14 
15 struct pinctrl_pin_desc;
16 struct platform_device;
17 struct device;
18 
19 /**
20  * struct intel_pingroup - Description about group of pins
21  * @name: Name of the groups
22  * @pins: All pins in this group
23  * @npins: Number of pins in this groups
24  * @mode: Native mode in which the group is muxed out @pins. Used if @modes
25  *        is %NULL.
26  * @modes: If not %NULL this will hold mode for each pin in @pins
27  */
28 struct intel_pingroup {
29 	const char *name;
30 	const unsigned int *pins;
31 	size_t npins;
32 	unsigned short mode;
33 	const unsigned int *modes;
34 };
35 
36 /**
37  * struct intel_function - Description about a function
38  * @name: Name of the function
39  * @groups: An array of groups for this function
40  * @ngroups: Number of groups in @groups
41  */
42 struct intel_function {
43 	const char *name;
44 	const char * const *groups;
45 	size_t ngroups;
46 };
47 
48 /**
49  * struct intel_padgroup - Hardware pad group information
50  * @reg_num: GPI_IS register number
51  * @base: Starting pin of this group
52  * @size: Size of this group (maximum is 32).
53  * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
54  *	       and %-1 if no GPIO mapping should be created)
55  * @padown_num: PAD_OWN register number (assigned by the core driver)
56  *
57  * If pad groups of a community are not the same size, use this structure
58  * to specify them.
59  */
60 struct intel_padgroup {
61 	unsigned int reg_num;
62 	unsigned int base;
63 	unsigned int size;
64 	int gpio_base;
65 	unsigned int padown_num;
66 };
67 
68 /**
69  * struct intel_community - Intel pin community description
70  * @barno: MMIO BAR number where registers for this community reside
71  * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
72  *                 then there is no support for owner.
73  * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
74  *                     locking is not supported.
75  * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
76  *                  is assumed that the host owns the pin (rather than
77  *                  ACPI).
78  * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
79  *             default (%0x100).
80  * @ie_offset: Register offset of GPI_IE from @regs.
81  * @pin_base: Starting pin of pins in this community
82  * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
83  *            HOSTSW_OWN,  GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
84  * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
85  *			 minimum. Use %0 if the number of registers can be
86  *			 determined by the size of the group.
87  * @npins: Number of pins in this community
88  * @features: Additional features supported by the hardware
89  * @gpps: Pad groups if the controller has variable size pad groups
90  * @ngpps: Number of pad groups in this community
91  * @regs: Community specific common registers (reserved for core driver)
92  * @pad_regs: Community specific pad registers (reserved for core driver)
93  *
94  * Most Intel GPIO host controllers this driver supports each pad group is
95  * of equal size (except the last one). In that case the driver can just
96  * fill in @gpp_size field and let the core driver to handle the rest. If
97  * the controller has pad groups of variable size the client driver can
98  * pass custom @gpps and @ngpps instead.
99  */
100 struct intel_community {
101 	unsigned int barno;
102 	unsigned int padown_offset;
103 	unsigned int padcfglock_offset;
104 	unsigned int hostown_offset;
105 	unsigned int is_offset;
106 	unsigned int ie_offset;
107 	unsigned int pin_base;
108 	unsigned int gpp_size;
109 	unsigned int gpp_num_padown_regs;
110 	size_t npins;
111 	unsigned int features;
112 	const struct intel_padgroup *gpps;
113 	size_t ngpps;
114 	/* Reserved for the core driver */
115 	void __iomem *regs;
116 	void __iomem *pad_regs;
117 };
118 
119 /* Additional features supported by the hardware */
120 #define PINCTRL_FEATURE_DEBOUNCE	BIT(0)
121 #define PINCTRL_FEATURE_1K_PD		BIT(1)
122 
123 /**
124  * PIN_GROUP - Declare a pin group
125  * @n: Name of the group
126  * @p: An array of pins this group consists
127  * @m: Mode which the pins are put when this group is active. Can be either
128  *     a single integer or an array of integers in which case mode is per
129  *     pin.
130  */
131 #define PIN_GROUP(n, p, m)					\
132 	{							\
133 		.name = (n),					\
134 		.pins = (p),					\
135 		.npins = ARRAY_SIZE((p)),			\
136 		.mode = __builtin_choose_expr(			\
137 			__builtin_constant_p((m)), (m), 0),	\
138 		.modes = __builtin_choose_expr(			\
139 			__builtin_constant_p((m)), NULL, (m)),	\
140 	}
141 
142 #define FUNCTION(n, g)				\
143 	{					\
144 		.name = (n),			\
145 		.groups = (g),			\
146 		.ngroups = ARRAY_SIZE((g)),	\
147 	}
148 
149 /**
150  * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
151  * @uid: ACPI _UID for the probe driver use if needed
152  * @pins: Array if pins this pinctrl controls
153  * @npins: Number of pins in the array
154  * @groups: Array of pin groups
155  * @ngroups: Number of groups in the array
156  * @functions: Array of functions
157  * @nfunctions: Number of functions in the array
158  * @communities: Array of communities this pinctrl handles
159  * @ncommunities: Number of communities in the array
160  *
161  * The @communities is used as a template by the core driver. It will make
162  * copy of all communities and fill in rest of the information.
163  */
164 struct intel_pinctrl_soc_data {
165 	const char *uid;
166 	const struct pinctrl_pin_desc *pins;
167 	size_t npins;
168 	const struct intel_pingroup *groups;
169 	size_t ngroups;
170 	const struct intel_function *functions;
171 	size_t nfunctions;
172 	const struct intel_community *communities;
173 	size_t ncommunities;
174 };
175 
176 int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
177 int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
178 
179 #ifdef CONFIG_PM_SLEEP
180 int intel_pinctrl_suspend_noirq(struct device *dev);
181 int intel_pinctrl_resume_noirq(struct device *dev);
182 #endif
183 
184 #define INTEL_PINCTRL_PM_OPS(_name)					\
185 const struct dev_pm_ops _name = {					\
186 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq,	\
187 				      intel_pinctrl_resume_noirq)	\
188 }
189 
190 #endif /* PINCTRL_INTEL_H */
191