1 /* 2 * Intel pinctrl/GPIO core driver. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/platform_device.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 22 #include "pinctrl-intel.h" 23 24 /* Offset from regs */ 25 #define PADBAR 0x00c 26 #define GPI_IS 0x100 27 #define GPI_GPE_STS 0x140 28 #define GPI_GPE_EN 0x160 29 30 #define PADOWN_BITS 4 31 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 32 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 33 #define PADOWN_GPP(p) ((p) / 8) 34 35 /* Offset from pad_regs */ 36 #define PADCFG0 0x000 37 #define PADCFG0_RXEVCFG_SHIFT 25 38 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 39 #define PADCFG0_RXEVCFG_LEVEL 0 40 #define PADCFG0_RXEVCFG_EDGE 1 41 #define PADCFG0_RXEVCFG_DISABLED 2 42 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 43 #define PADCFG0_RXINV BIT(23) 44 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 45 #define PADCFG0_GPIROUTSCI BIT(19) 46 #define PADCFG0_GPIROUTSMI BIT(18) 47 #define PADCFG0_GPIROUTNMI BIT(17) 48 #define PADCFG0_PMODE_SHIFT 10 49 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 50 #define PADCFG0_GPIORXDIS BIT(9) 51 #define PADCFG0_GPIOTXDIS BIT(8) 52 #define PADCFG0_GPIORXSTATE BIT(1) 53 #define PADCFG0_GPIOTXSTATE BIT(0) 54 55 #define PADCFG1 0x004 56 #define PADCFG1_TERM_UP BIT(13) 57 #define PADCFG1_TERM_SHIFT 10 58 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 59 #define PADCFG1_TERM_20K 4 60 #define PADCFG1_TERM_2K 3 61 #define PADCFG1_TERM_5K 2 62 #define PADCFG1_TERM_1K 1 63 64 struct intel_pad_context { 65 u32 padcfg0; 66 u32 padcfg1; 67 }; 68 69 struct intel_community_context { 70 u32 *intmask; 71 }; 72 73 struct intel_pinctrl_context { 74 struct intel_pad_context *pads; 75 struct intel_community_context *communities; 76 }; 77 78 /** 79 * struct intel_pinctrl - Intel pinctrl private structure 80 * @dev: Pointer to the device structure 81 * @lock: Lock to serialize register access 82 * @pctldesc: Pin controller description 83 * @pctldev: Pointer to the pin controller device 84 * @chip: GPIO chip in this pin controller 85 * @soc: SoC/PCH specific pin configuration data 86 * @communities: All communities in this pin controller 87 * @ncommunities: Number of communities in this pin controller 88 * @context: Configuration saved over system sleep 89 * @irq: pinctrl/GPIO chip irq number 90 */ 91 struct intel_pinctrl { 92 struct device *dev; 93 raw_spinlock_t lock; 94 struct pinctrl_desc pctldesc; 95 struct pinctrl_dev *pctldev; 96 struct gpio_chip chip; 97 const struct intel_pinctrl_soc_data *soc; 98 struct intel_community *communities; 99 size_t ncommunities; 100 struct intel_pinctrl_context context; 101 int irq; 102 }; 103 104 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 105 106 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 107 unsigned pin) 108 { 109 struct intel_community *community; 110 int i; 111 112 for (i = 0; i < pctrl->ncommunities; i++) { 113 community = &pctrl->communities[i]; 114 if (pin >= community->pin_base && 115 pin < community->pin_base + community->npins) 116 return community; 117 } 118 119 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 120 return NULL; 121 } 122 123 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 124 unsigned reg) 125 { 126 const struct intel_community *community; 127 unsigned padno; 128 129 community = intel_get_community(pctrl, pin); 130 if (!community) 131 return NULL; 132 133 padno = pin_to_padno(community, pin); 134 return community->pad_regs + reg + padno * 8; 135 } 136 137 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 138 { 139 const struct intel_community *community; 140 unsigned padno, gpp, offset, group; 141 void __iomem *padown; 142 143 community = intel_get_community(pctrl, pin); 144 if (!community) 145 return false; 146 if (!community->padown_offset) 147 return true; 148 149 padno = pin_to_padno(community, pin); 150 group = padno / community->gpp_size; 151 gpp = PADOWN_GPP(padno % community->gpp_size); 152 offset = community->padown_offset + 0x10 * group + gpp * 4; 153 padown = community->regs + offset; 154 155 return !(readl(padown) & PADOWN_MASK(padno)); 156 } 157 158 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 159 { 160 const struct intel_community *community; 161 unsigned padno, gpp, offset; 162 void __iomem *hostown; 163 164 community = intel_get_community(pctrl, pin); 165 if (!community) 166 return true; 167 if (!community->hostown_offset) 168 return false; 169 170 padno = pin_to_padno(community, pin); 171 gpp = padno / community->gpp_size; 172 offset = community->hostown_offset + gpp * 4; 173 hostown = community->regs + offset; 174 175 return !(readl(hostown) & BIT(padno % community->gpp_size)); 176 } 177 178 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 179 { 180 struct intel_community *community; 181 unsigned padno, gpp, offset; 182 u32 value; 183 184 community = intel_get_community(pctrl, pin); 185 if (!community) 186 return true; 187 if (!community->padcfglock_offset) 188 return false; 189 190 padno = pin_to_padno(community, pin); 191 gpp = padno / community->gpp_size; 192 193 /* 194 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 195 * the pad is considered unlocked. Any other case means that it is 196 * either fully or partially locked and we don't touch it. 197 */ 198 offset = community->padcfglock_offset + gpp * 8; 199 value = readl(community->regs + offset); 200 if (value & BIT(pin % community->gpp_size)) 201 return true; 202 203 offset = community->padcfglock_offset + 4 + gpp * 8; 204 value = readl(community->regs + offset); 205 if (value & BIT(pin % community->gpp_size)) 206 return true; 207 208 return false; 209 } 210 211 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 212 { 213 return intel_pad_owned_by_host(pctrl, pin) && 214 !intel_pad_locked(pctrl, pin); 215 } 216 217 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 218 { 219 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 220 221 return pctrl->soc->ngroups; 222 } 223 224 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 225 unsigned group) 226 { 227 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 228 229 return pctrl->soc->groups[group].name; 230 } 231 232 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 233 const unsigned **pins, unsigned *npins) 234 { 235 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 236 237 *pins = pctrl->soc->groups[group].pins; 238 *npins = pctrl->soc->groups[group].npins; 239 return 0; 240 } 241 242 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 243 unsigned pin) 244 { 245 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 246 u32 cfg0, cfg1, mode; 247 bool locked, acpi; 248 249 if (!intel_pad_owned_by_host(pctrl, pin)) { 250 seq_puts(s, "not available"); 251 return; 252 } 253 254 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 255 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 256 257 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 258 if (!mode) 259 seq_puts(s, "GPIO "); 260 else 261 seq_printf(s, "mode %d ", mode); 262 263 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 264 265 locked = intel_pad_locked(pctrl, pin); 266 acpi = intel_pad_acpi_mode(pctrl, pin); 267 268 if (locked || acpi) { 269 seq_puts(s, " ["); 270 if (locked) { 271 seq_puts(s, "LOCKED"); 272 if (acpi) 273 seq_puts(s, ", "); 274 } 275 if (acpi) 276 seq_puts(s, "ACPI"); 277 seq_puts(s, "]"); 278 } 279 } 280 281 static const struct pinctrl_ops intel_pinctrl_ops = { 282 .get_groups_count = intel_get_groups_count, 283 .get_group_name = intel_get_group_name, 284 .get_group_pins = intel_get_group_pins, 285 .pin_dbg_show = intel_pin_dbg_show, 286 }; 287 288 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 289 { 290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 291 292 return pctrl->soc->nfunctions; 293 } 294 295 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 296 unsigned function) 297 { 298 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 299 300 return pctrl->soc->functions[function].name; 301 } 302 303 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 304 unsigned function, 305 const char * const **groups, 306 unsigned * const ngroups) 307 { 308 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 309 310 *groups = pctrl->soc->functions[function].groups; 311 *ngroups = pctrl->soc->functions[function].ngroups; 312 return 0; 313 } 314 315 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 316 unsigned group) 317 { 318 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 319 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 320 unsigned long flags; 321 int i; 322 323 raw_spin_lock_irqsave(&pctrl->lock, flags); 324 325 /* 326 * All pins in the groups needs to be accessible and writable 327 * before we can enable the mux for this group. 328 */ 329 for (i = 0; i < grp->npins; i++) { 330 if (!intel_pad_usable(pctrl, grp->pins[i])) { 331 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 332 return -EBUSY; 333 } 334 } 335 336 /* Now enable the mux setting for each pin in the group */ 337 for (i = 0; i < grp->npins; i++) { 338 void __iomem *padcfg0; 339 u32 value; 340 341 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 342 value = readl(padcfg0); 343 344 value &= ~PADCFG0_PMODE_MASK; 345 value |= grp->mode << PADCFG0_PMODE_SHIFT; 346 347 writel(value, padcfg0); 348 } 349 350 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 351 352 return 0; 353 } 354 355 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 356 struct pinctrl_gpio_range *range, 357 unsigned pin) 358 { 359 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 360 void __iomem *padcfg0; 361 unsigned long flags; 362 u32 value; 363 364 raw_spin_lock_irqsave(&pctrl->lock, flags); 365 366 if (!intel_pad_usable(pctrl, pin)) { 367 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 368 return -EBUSY; 369 } 370 371 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 372 /* Put the pad into GPIO mode */ 373 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 374 /* Disable SCI/SMI/NMI generation */ 375 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 376 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 377 /* Disable TX buffer and enable RX (this will be input) */ 378 value &= ~PADCFG0_GPIORXDIS; 379 value |= PADCFG0_GPIOTXDIS; 380 writel(value, padcfg0); 381 382 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 383 384 return 0; 385 } 386 387 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 388 struct pinctrl_gpio_range *range, 389 unsigned pin, bool input) 390 { 391 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 392 void __iomem *padcfg0; 393 unsigned long flags; 394 u32 value; 395 396 raw_spin_lock_irqsave(&pctrl->lock, flags); 397 398 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 399 400 value = readl(padcfg0); 401 if (input) 402 value |= PADCFG0_GPIOTXDIS; 403 else 404 value &= ~PADCFG0_GPIOTXDIS; 405 writel(value, padcfg0); 406 407 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 408 409 return 0; 410 } 411 412 static const struct pinmux_ops intel_pinmux_ops = { 413 .get_functions_count = intel_get_functions_count, 414 .get_function_name = intel_get_function_name, 415 .get_function_groups = intel_get_function_groups, 416 .set_mux = intel_pinmux_set_mux, 417 .gpio_request_enable = intel_gpio_request_enable, 418 .gpio_set_direction = intel_gpio_set_direction, 419 }; 420 421 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 422 unsigned long *config) 423 { 424 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 425 enum pin_config_param param = pinconf_to_config_param(*config); 426 u32 value, term; 427 u16 arg = 0; 428 429 if (!intel_pad_owned_by_host(pctrl, pin)) 430 return -ENOTSUPP; 431 432 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 433 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 434 435 switch (param) { 436 case PIN_CONFIG_BIAS_DISABLE: 437 if (term) 438 return -EINVAL; 439 break; 440 441 case PIN_CONFIG_BIAS_PULL_UP: 442 if (!term || !(value & PADCFG1_TERM_UP)) 443 return -EINVAL; 444 445 switch (term) { 446 case PADCFG1_TERM_1K: 447 arg = 1000; 448 break; 449 case PADCFG1_TERM_2K: 450 arg = 2000; 451 break; 452 case PADCFG1_TERM_5K: 453 arg = 5000; 454 break; 455 case PADCFG1_TERM_20K: 456 arg = 20000; 457 break; 458 } 459 460 break; 461 462 case PIN_CONFIG_BIAS_PULL_DOWN: 463 if (!term || value & PADCFG1_TERM_UP) 464 return -EINVAL; 465 466 switch (term) { 467 case PADCFG1_TERM_5K: 468 arg = 5000; 469 break; 470 case PADCFG1_TERM_20K: 471 arg = 20000; 472 break; 473 } 474 475 break; 476 477 default: 478 return -ENOTSUPP; 479 } 480 481 *config = pinconf_to_config_packed(param, arg); 482 return 0; 483 } 484 485 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 486 unsigned long config) 487 { 488 unsigned param = pinconf_to_config_param(config); 489 unsigned arg = pinconf_to_config_argument(config); 490 void __iomem *padcfg1; 491 unsigned long flags; 492 int ret = 0; 493 u32 value; 494 495 raw_spin_lock_irqsave(&pctrl->lock, flags); 496 497 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 498 value = readl(padcfg1); 499 500 switch (param) { 501 case PIN_CONFIG_BIAS_DISABLE: 502 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 503 break; 504 505 case PIN_CONFIG_BIAS_PULL_UP: 506 value &= ~PADCFG1_TERM_MASK; 507 508 value |= PADCFG1_TERM_UP; 509 510 switch (arg) { 511 case 20000: 512 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 513 break; 514 case 5000: 515 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 516 break; 517 case 2000: 518 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 519 break; 520 case 1000: 521 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 522 break; 523 default: 524 ret = -EINVAL; 525 } 526 527 break; 528 529 case PIN_CONFIG_BIAS_PULL_DOWN: 530 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 531 532 switch (arg) { 533 case 20000: 534 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 535 break; 536 case 5000: 537 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 538 break; 539 default: 540 ret = -EINVAL; 541 } 542 543 break; 544 } 545 546 if (!ret) 547 writel(value, padcfg1); 548 549 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 550 551 return ret; 552 } 553 554 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 555 unsigned long *configs, unsigned nconfigs) 556 { 557 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 558 int i, ret; 559 560 if (!intel_pad_usable(pctrl, pin)) 561 return -ENOTSUPP; 562 563 for (i = 0; i < nconfigs; i++) { 564 switch (pinconf_to_config_param(configs[i])) { 565 case PIN_CONFIG_BIAS_DISABLE: 566 case PIN_CONFIG_BIAS_PULL_UP: 567 case PIN_CONFIG_BIAS_PULL_DOWN: 568 ret = intel_config_set_pull(pctrl, pin, configs[i]); 569 if (ret) 570 return ret; 571 break; 572 573 default: 574 return -ENOTSUPP; 575 } 576 } 577 578 return 0; 579 } 580 581 static const struct pinconf_ops intel_pinconf_ops = { 582 .is_generic = true, 583 .pin_config_get = intel_config_get, 584 .pin_config_set = intel_config_set, 585 }; 586 587 static const struct pinctrl_desc intel_pinctrl_desc = { 588 .pctlops = &intel_pinctrl_ops, 589 .pmxops = &intel_pinmux_ops, 590 .confops = &intel_pinconf_ops, 591 .owner = THIS_MODULE, 592 }; 593 594 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 595 { 596 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 597 void __iomem *reg; 598 599 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 600 if (!reg) 601 return -EINVAL; 602 603 return !!(readl(reg) & PADCFG0_GPIORXSTATE); 604 } 605 606 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 607 { 608 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 609 void __iomem *reg; 610 611 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 612 if (reg) { 613 unsigned long flags; 614 u32 padcfg0; 615 616 raw_spin_lock_irqsave(&pctrl->lock, flags); 617 padcfg0 = readl(reg); 618 if (value) 619 padcfg0 |= PADCFG0_GPIOTXSTATE; 620 else 621 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 622 writel(padcfg0, reg); 623 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 624 } 625 } 626 627 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 628 { 629 return pinctrl_gpio_direction_input(chip->base + offset); 630 } 631 632 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 633 int value) 634 { 635 intel_gpio_set(chip, offset, value); 636 return pinctrl_gpio_direction_output(chip->base + offset); 637 } 638 639 static const struct gpio_chip intel_gpio_chip = { 640 .owner = THIS_MODULE, 641 .request = gpiochip_generic_request, 642 .free = gpiochip_generic_free, 643 .direction_input = intel_gpio_direction_input, 644 .direction_output = intel_gpio_direction_output, 645 .get = intel_gpio_get, 646 .set = intel_gpio_set, 647 }; 648 649 static void intel_gpio_irq_ack(struct irq_data *d) 650 { 651 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 652 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 653 const struct intel_community *community; 654 unsigned pin = irqd_to_hwirq(d); 655 656 raw_spin_lock(&pctrl->lock); 657 658 community = intel_get_community(pctrl, pin); 659 if (community) { 660 unsigned padno = pin_to_padno(community, pin); 661 unsigned gpp_offset = padno % community->gpp_size; 662 unsigned gpp = padno / community->gpp_size; 663 664 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 665 } 666 667 raw_spin_unlock(&pctrl->lock); 668 } 669 670 static void intel_gpio_irq_enable(struct irq_data *d) 671 { 672 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 673 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 674 const struct intel_community *community; 675 unsigned pin = irqd_to_hwirq(d); 676 unsigned long flags; 677 678 raw_spin_lock_irqsave(&pctrl->lock, flags); 679 680 community = intel_get_community(pctrl, pin); 681 if (community) { 682 unsigned padno = pin_to_padno(community, pin); 683 unsigned gpp_size = community->gpp_size; 684 unsigned gpp_offset = padno % gpp_size; 685 unsigned gpp = padno / gpp_size; 686 u32 value; 687 688 /* Clear interrupt status first to avoid unexpected interrupt */ 689 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 690 691 value = readl(community->regs + community->ie_offset + gpp * 4); 692 value |= BIT(gpp_offset); 693 writel(value, community->regs + community->ie_offset + gpp * 4); 694 } 695 696 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 697 } 698 699 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 700 { 701 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 702 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 703 const struct intel_community *community; 704 unsigned pin = irqd_to_hwirq(d); 705 unsigned long flags; 706 707 raw_spin_lock_irqsave(&pctrl->lock, flags); 708 709 community = intel_get_community(pctrl, pin); 710 if (community) { 711 unsigned padno = pin_to_padno(community, pin); 712 unsigned gpp_offset = padno % community->gpp_size; 713 unsigned gpp = padno / community->gpp_size; 714 void __iomem *reg; 715 u32 value; 716 717 reg = community->regs + community->ie_offset + gpp * 4; 718 value = readl(reg); 719 if (mask) 720 value &= ~BIT(gpp_offset); 721 else 722 value |= BIT(gpp_offset); 723 writel(value, reg); 724 } 725 726 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 727 } 728 729 static void intel_gpio_irq_mask(struct irq_data *d) 730 { 731 intel_gpio_irq_mask_unmask(d, true); 732 } 733 734 static void intel_gpio_irq_unmask(struct irq_data *d) 735 { 736 intel_gpio_irq_mask_unmask(d, false); 737 } 738 739 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 740 { 741 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 742 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 743 unsigned pin = irqd_to_hwirq(d); 744 unsigned long flags; 745 void __iomem *reg; 746 u32 value; 747 748 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 749 if (!reg) 750 return -EINVAL; 751 752 /* 753 * If the pin is in ACPI mode it is still usable as a GPIO but it 754 * cannot be used as IRQ because GPI_IS status bit will not be 755 * updated by the host controller hardware. 756 */ 757 if (intel_pad_acpi_mode(pctrl, pin)) { 758 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 759 return -EPERM; 760 } 761 762 raw_spin_lock_irqsave(&pctrl->lock, flags); 763 764 value = readl(reg); 765 766 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 767 768 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 769 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 770 } else if (type & IRQ_TYPE_EDGE_FALLING) { 771 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 772 value |= PADCFG0_RXINV; 773 } else if (type & IRQ_TYPE_EDGE_RISING) { 774 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 775 } else if (type & IRQ_TYPE_LEVEL_MASK) { 776 if (type & IRQ_TYPE_LEVEL_LOW) 777 value |= PADCFG0_RXINV; 778 } else { 779 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 780 } 781 782 writel(value, reg); 783 784 if (type & IRQ_TYPE_EDGE_BOTH) 785 irq_set_handler_locked(d, handle_edge_irq); 786 else if (type & IRQ_TYPE_LEVEL_MASK) 787 irq_set_handler_locked(d, handle_level_irq); 788 789 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 790 791 return 0; 792 } 793 794 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 795 { 796 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 797 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 798 unsigned pin = irqd_to_hwirq(d); 799 800 if (on) 801 enable_irq_wake(pctrl->irq); 802 else 803 disable_irq_wake(pctrl->irq); 804 805 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 806 return 0; 807 } 808 809 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 810 const struct intel_community *community) 811 { 812 struct gpio_chip *gc = &pctrl->chip; 813 irqreturn_t ret = IRQ_NONE; 814 int gpp; 815 816 for (gpp = 0; gpp < community->ngpps; gpp++) { 817 unsigned long pending, enabled, gpp_offset; 818 819 pending = readl(community->regs + GPI_IS + gpp * 4); 820 enabled = readl(community->regs + community->ie_offset + 821 gpp * 4); 822 823 /* Only interrupts that are enabled */ 824 pending &= enabled; 825 826 for_each_set_bit(gpp_offset, &pending, community->gpp_size) { 827 unsigned padno, irq; 828 829 /* 830 * The last group in community can have less pins 831 * than NPADS_IN_GPP. 832 */ 833 padno = gpp_offset + gpp * community->gpp_size; 834 if (padno >= community->npins) 835 break; 836 837 irq = irq_find_mapping(gc->irqdomain, 838 community->pin_base + padno); 839 generic_handle_irq(irq); 840 841 ret |= IRQ_HANDLED; 842 } 843 } 844 845 return ret; 846 } 847 848 static irqreturn_t intel_gpio_irq(int irq, void *data) 849 { 850 const struct intel_community *community; 851 struct intel_pinctrl *pctrl = data; 852 irqreturn_t ret = IRQ_NONE; 853 int i; 854 855 /* Need to check all communities for pending interrupts */ 856 for (i = 0; i < pctrl->ncommunities; i++) { 857 community = &pctrl->communities[i]; 858 ret |= intel_gpio_community_irq_handler(pctrl, community); 859 } 860 861 return ret; 862 } 863 864 static struct irq_chip intel_gpio_irqchip = { 865 .name = "intel-gpio", 866 .irq_enable = intel_gpio_irq_enable, 867 .irq_ack = intel_gpio_irq_ack, 868 .irq_mask = intel_gpio_irq_mask, 869 .irq_unmask = intel_gpio_irq_unmask, 870 .irq_set_type = intel_gpio_irq_type, 871 .irq_set_wake = intel_gpio_irq_wake, 872 }; 873 874 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 875 { 876 int ret; 877 878 pctrl->chip = intel_gpio_chip; 879 880 pctrl->chip.ngpio = pctrl->soc->npins; 881 pctrl->chip.label = dev_name(pctrl->dev); 882 pctrl->chip.parent = pctrl->dev; 883 pctrl->chip.base = -1; 884 pctrl->irq = irq; 885 886 ret = gpiochip_add_data(&pctrl->chip, pctrl); 887 if (ret) { 888 dev_err(pctrl->dev, "failed to register gpiochip\n"); 889 return ret; 890 } 891 892 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 893 0, 0, pctrl->soc->npins); 894 if (ret) { 895 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 896 goto fail; 897 } 898 899 /* 900 * We need to request the interrupt here (instead of providing chip 901 * to the irq directly) because on some platforms several GPIO 902 * controllers share the same interrupt line. 903 */ 904 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 905 IRQF_SHARED | IRQF_NO_THREAD, 906 dev_name(pctrl->dev), pctrl); 907 if (ret) { 908 dev_err(pctrl->dev, "failed to request interrupt\n"); 909 goto fail; 910 } 911 912 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 913 handle_simple_irq, IRQ_TYPE_NONE); 914 if (ret) { 915 dev_err(pctrl->dev, "failed to add irqchip\n"); 916 goto fail; 917 } 918 919 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 920 NULL); 921 return 0; 922 923 fail: 924 gpiochip_remove(&pctrl->chip); 925 926 return ret; 927 } 928 929 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 930 { 931 #ifdef CONFIG_PM_SLEEP 932 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 933 struct intel_community_context *communities; 934 struct intel_pad_context *pads; 935 int i; 936 937 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 938 if (!pads) 939 return -ENOMEM; 940 941 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 942 sizeof(*communities), GFP_KERNEL); 943 if (!communities) 944 return -ENOMEM; 945 946 947 for (i = 0; i < pctrl->ncommunities; i++) { 948 struct intel_community *community = &pctrl->communities[i]; 949 u32 *intmask; 950 951 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 952 sizeof(*intmask), GFP_KERNEL); 953 if (!intmask) 954 return -ENOMEM; 955 956 communities[i].intmask = intmask; 957 } 958 959 pctrl->context.pads = pads; 960 pctrl->context.communities = communities; 961 #endif 962 963 return 0; 964 } 965 966 int intel_pinctrl_probe(struct platform_device *pdev, 967 const struct intel_pinctrl_soc_data *soc_data) 968 { 969 struct intel_pinctrl *pctrl; 970 int i, ret, irq; 971 972 if (!soc_data) 973 return -EINVAL; 974 975 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 976 if (!pctrl) 977 return -ENOMEM; 978 979 pctrl->dev = &pdev->dev; 980 pctrl->soc = soc_data; 981 raw_spin_lock_init(&pctrl->lock); 982 983 /* 984 * Make a copy of the communities which we can use to hold pointers 985 * to the registers. 986 */ 987 pctrl->ncommunities = pctrl->soc->ncommunities; 988 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 989 sizeof(*pctrl->communities), GFP_KERNEL); 990 if (!pctrl->communities) 991 return -ENOMEM; 992 993 for (i = 0; i < pctrl->ncommunities; i++) { 994 struct intel_community *community = &pctrl->communities[i]; 995 struct resource *res; 996 void __iomem *regs; 997 u32 padbar; 998 999 *community = pctrl->soc->communities[i]; 1000 1001 res = platform_get_resource(pdev, IORESOURCE_MEM, 1002 community->barno); 1003 regs = devm_ioremap_resource(&pdev->dev, res); 1004 if (IS_ERR(regs)) 1005 return PTR_ERR(regs); 1006 1007 /* Read offset of the pad configuration registers */ 1008 padbar = readl(regs + PADBAR); 1009 1010 community->regs = regs; 1011 community->pad_regs = regs + padbar; 1012 community->ngpps = DIV_ROUND_UP(community->npins, 1013 community->gpp_size); 1014 } 1015 1016 irq = platform_get_irq(pdev, 0); 1017 if (irq < 0) { 1018 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1019 return irq; 1020 } 1021 1022 ret = intel_pinctrl_pm_init(pctrl); 1023 if (ret) 1024 return ret; 1025 1026 pctrl->pctldesc = intel_pinctrl_desc; 1027 pctrl->pctldesc.name = dev_name(&pdev->dev); 1028 pctrl->pctldesc.pins = pctrl->soc->pins; 1029 pctrl->pctldesc.npins = pctrl->soc->npins; 1030 1031 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1032 pctrl); 1033 if (IS_ERR(pctrl->pctldev)) { 1034 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1035 return PTR_ERR(pctrl->pctldev); 1036 } 1037 1038 ret = intel_gpio_probe(pctrl, irq); 1039 if (ret) 1040 return ret; 1041 1042 platform_set_drvdata(pdev, pctrl); 1043 1044 return 0; 1045 } 1046 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1047 1048 int intel_pinctrl_remove(struct platform_device *pdev) 1049 { 1050 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1051 1052 gpiochip_remove(&pctrl->chip); 1053 1054 return 0; 1055 } 1056 EXPORT_SYMBOL_GPL(intel_pinctrl_remove); 1057 1058 #ifdef CONFIG_PM_SLEEP 1059 int intel_pinctrl_suspend(struct device *dev) 1060 { 1061 struct platform_device *pdev = to_platform_device(dev); 1062 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1063 struct intel_community_context *communities; 1064 struct intel_pad_context *pads; 1065 int i; 1066 1067 pads = pctrl->context.pads; 1068 for (i = 0; i < pctrl->soc->npins; i++) { 1069 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1070 u32 val; 1071 1072 if (!intel_pad_usable(pctrl, desc->number)) 1073 continue; 1074 1075 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1076 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1077 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1078 pads[i].padcfg1 = val; 1079 } 1080 1081 communities = pctrl->context.communities; 1082 for (i = 0; i < pctrl->ncommunities; i++) { 1083 struct intel_community *community = &pctrl->communities[i]; 1084 void __iomem *base; 1085 unsigned gpp; 1086 1087 base = community->regs + community->ie_offset; 1088 for (gpp = 0; gpp < community->ngpps; gpp++) 1089 communities[i].intmask[gpp] = readl(base + gpp * 4); 1090 } 1091 1092 return 0; 1093 } 1094 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1095 1096 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1097 { 1098 size_t i; 1099 1100 for (i = 0; i < pctrl->ncommunities; i++) { 1101 const struct intel_community *community; 1102 void __iomem *base; 1103 unsigned gpp; 1104 1105 community = &pctrl->communities[i]; 1106 base = community->regs; 1107 1108 for (gpp = 0; gpp < community->ngpps; gpp++) { 1109 /* Mask and clear all interrupts */ 1110 writel(0, base + community->ie_offset + gpp * 4); 1111 writel(0xffff, base + GPI_IS + gpp * 4); 1112 } 1113 } 1114 } 1115 1116 int intel_pinctrl_resume(struct device *dev) 1117 { 1118 struct platform_device *pdev = to_platform_device(dev); 1119 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1120 const struct intel_community_context *communities; 1121 const struct intel_pad_context *pads; 1122 int i; 1123 1124 /* Mask all interrupts */ 1125 intel_gpio_irq_init(pctrl); 1126 1127 pads = pctrl->context.pads; 1128 for (i = 0; i < pctrl->soc->npins; i++) { 1129 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1130 void __iomem *padcfg; 1131 u32 val; 1132 1133 if (!intel_pad_usable(pctrl, desc->number)) 1134 continue; 1135 1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1137 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1138 if (val != pads[i].padcfg0) { 1139 writel(pads[i].padcfg0, padcfg); 1140 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1141 desc->number, readl(padcfg)); 1142 } 1143 1144 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1145 val = readl(padcfg); 1146 if (val != pads[i].padcfg1) { 1147 writel(pads[i].padcfg1, padcfg); 1148 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1149 desc->number, readl(padcfg)); 1150 } 1151 } 1152 1153 communities = pctrl->context.communities; 1154 for (i = 0; i < pctrl->ncommunities; i++) { 1155 struct intel_community *community = &pctrl->communities[i]; 1156 void __iomem *base; 1157 unsigned gpp; 1158 1159 base = community->regs + community->ie_offset; 1160 for (gpp = 0; gpp < community->ngpps; gpp++) { 1161 writel(communities[i].intmask[gpp], base + gpp * 4); 1162 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1163 readl(base + gpp * 4)); 1164 } 1165 } 1166 1167 return 0; 1168 } 1169 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1170 #endif 1171 1172 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1173 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1174 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1175 MODULE_LICENSE("GPL v2"); 1176