1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/interrupt.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/time.h> 18 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 24 #include "../core.h" 25 #include "pinctrl-intel.h" 26 27 /* Offset from regs */ 28 #define REVID 0x000 29 #define REVID_SHIFT 16 30 #define REVID_MASK GENMASK(31, 16) 31 32 #define PADBAR 0x00c 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_PREGFRXSEL BIT(24) 48 #define PADCFG0_RXINV BIT(23) 49 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 50 #define PADCFG0_GPIROUTSCI BIT(19) 51 #define PADCFG0_GPIROUTSMI BIT(18) 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 #define PADCFG0_PMODE_SHIFT 10 54 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 55 #define PADCFG0_GPIORXDIS BIT(9) 56 #define PADCFG0_GPIOTXDIS BIT(8) 57 #define PADCFG0_GPIORXSTATE BIT(1) 58 #define PADCFG0_GPIOTXSTATE BIT(0) 59 60 #define PADCFG1 0x004 61 #define PADCFG1_TERM_UP BIT(13) 62 #define PADCFG1_TERM_SHIFT 10 63 #define PADCFG1_TERM_MASK GENMASK(12, 10) 64 #define PADCFG1_TERM_20K 4 65 #define PADCFG1_TERM_2K 3 66 #define PADCFG1_TERM_5K 2 67 #define PADCFG1_TERM_1K 1 68 69 #define PADCFG2 0x008 70 #define PADCFG2_DEBEN BIT(0) 71 #define PADCFG2_DEBOUNCE_SHIFT 1 72 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 73 74 #define DEBOUNCE_PERIOD_NSEC 31250 75 76 struct intel_pad_context { 77 u32 padcfg0; 78 u32 padcfg1; 79 u32 padcfg2; 80 }; 81 82 struct intel_community_context { 83 u32 *intmask; 84 u32 *hostown; 85 }; 86 87 struct intel_pinctrl_context { 88 struct intel_pad_context *pads; 89 struct intel_community_context *communities; 90 }; 91 92 /** 93 * struct intel_pinctrl - Intel pinctrl private structure 94 * @dev: Pointer to the device structure 95 * @lock: Lock to serialize register access 96 * @pctldesc: Pin controller description 97 * @pctldev: Pointer to the pin controller device 98 * @chip: GPIO chip in this pin controller 99 * @soc: SoC/PCH specific pin configuration data 100 * @communities: All communities in this pin controller 101 * @ncommunities: Number of communities in this pin controller 102 * @context: Configuration saved over system sleep 103 * @irq: pinctrl/GPIO chip irq number 104 */ 105 struct intel_pinctrl { 106 struct device *dev; 107 raw_spinlock_t lock; 108 struct pinctrl_desc pctldesc; 109 struct pinctrl_dev *pctldev; 110 struct gpio_chip chip; 111 const struct intel_pinctrl_soc_data *soc; 112 struct intel_community *communities; 113 size_t ncommunities; 114 struct intel_pinctrl_context context; 115 int irq; 116 }; 117 118 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 119 #define padgroup_offset(g, p) ((p) - (g)->base) 120 121 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 122 unsigned int pin) 123 { 124 struct intel_community *community; 125 int i; 126 127 for (i = 0; i < pctrl->ncommunities; i++) { 128 community = &pctrl->communities[i]; 129 if (pin >= community->pin_base && 130 pin < community->pin_base + community->npins) 131 return community; 132 } 133 134 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 135 return NULL; 136 } 137 138 static const struct intel_padgroup * 139 intel_community_get_padgroup(const struct intel_community *community, 140 unsigned int pin) 141 { 142 int i; 143 144 for (i = 0; i < community->ngpps; i++) { 145 const struct intel_padgroup *padgrp = &community->gpps[i]; 146 147 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 148 return padgrp; 149 } 150 151 return NULL; 152 } 153 154 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 155 unsigned int pin, unsigned int reg) 156 { 157 const struct intel_community *community; 158 unsigned int padno; 159 size_t nregs; 160 161 community = intel_get_community(pctrl, pin); 162 if (!community) 163 return NULL; 164 165 padno = pin_to_padno(community, pin); 166 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 167 168 if (reg >= nregs * 4) 169 return NULL; 170 171 return community->pad_regs + reg + padno * nregs * 4; 172 } 173 174 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 175 { 176 const struct intel_community *community; 177 const struct intel_padgroup *padgrp; 178 unsigned int gpp, offset, gpp_offset; 179 void __iomem *padown; 180 181 community = intel_get_community(pctrl, pin); 182 if (!community) 183 return false; 184 if (!community->padown_offset) 185 return true; 186 187 padgrp = intel_community_get_padgroup(community, pin); 188 if (!padgrp) 189 return false; 190 191 gpp_offset = padgroup_offset(padgrp, pin); 192 gpp = PADOWN_GPP(gpp_offset); 193 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 194 padown = community->regs + offset; 195 196 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 197 } 198 199 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 200 { 201 const struct intel_community *community; 202 const struct intel_padgroup *padgrp; 203 unsigned int offset, gpp_offset; 204 void __iomem *hostown; 205 206 community = intel_get_community(pctrl, pin); 207 if (!community) 208 return true; 209 if (!community->hostown_offset) 210 return false; 211 212 padgrp = intel_community_get_padgroup(community, pin); 213 if (!padgrp) 214 return true; 215 216 gpp_offset = padgroup_offset(padgrp, pin); 217 offset = community->hostown_offset + padgrp->reg_num * 4; 218 hostown = community->regs + offset; 219 220 return !(readl(hostown) & BIT(gpp_offset)); 221 } 222 223 /** 224 * enum - Locking variants of the pad configuration 225 * 226 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 227 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 228 * @PAD_LOCKED_TX: pad configuration TX state is locked 229 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 230 * 231 * Locking is considered as read-only mode for corresponding registers and 232 * their respective fields. That said, TX state bit is locked separately from 233 * the main locking scheme. 234 */ 235 enum { 236 PAD_UNLOCKED = 0, 237 PAD_LOCKED = 1, 238 PAD_LOCKED_TX = 2, 239 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 240 }; 241 242 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 243 { 244 struct intel_community *community; 245 const struct intel_padgroup *padgrp; 246 unsigned int offset, gpp_offset; 247 u32 value; 248 int ret = PAD_UNLOCKED; 249 250 community = intel_get_community(pctrl, pin); 251 if (!community) 252 return PAD_LOCKED_FULL; 253 if (!community->padcfglock_offset) 254 return PAD_UNLOCKED; 255 256 padgrp = intel_community_get_padgroup(community, pin); 257 if (!padgrp) 258 return PAD_LOCKED_FULL; 259 260 gpp_offset = padgroup_offset(padgrp, pin); 261 262 /* 263 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 264 * the pad is considered unlocked. Any other case means that it is 265 * either fully or partially locked. 266 */ 267 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 268 value = readl(community->regs + offset); 269 if (value & BIT(gpp_offset)) 270 ret |= PAD_LOCKED; 271 272 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 273 value = readl(community->regs + offset); 274 if (value & BIT(gpp_offset)) 275 ret |= PAD_LOCKED_TX; 276 277 return ret; 278 } 279 280 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 281 { 282 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 283 } 284 285 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 286 { 287 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 288 } 289 290 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 291 { 292 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 293 294 return pctrl->soc->ngroups; 295 } 296 297 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 298 unsigned int group) 299 { 300 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 301 302 return pctrl->soc->groups[group].name; 303 } 304 305 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 306 const unsigned int **pins, unsigned int *npins) 307 { 308 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 309 310 *pins = pctrl->soc->groups[group].pins; 311 *npins = pctrl->soc->groups[group].npins; 312 return 0; 313 } 314 315 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 316 unsigned int pin) 317 { 318 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 319 void __iomem *padcfg; 320 u32 cfg0, cfg1, mode; 321 int locked; 322 bool acpi; 323 324 if (!intel_pad_owned_by_host(pctrl, pin)) { 325 seq_puts(s, "not available"); 326 return; 327 } 328 329 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 330 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 331 332 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 333 if (!mode) 334 seq_puts(s, "GPIO "); 335 else 336 seq_printf(s, "mode %d ", mode); 337 338 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 339 340 /* Dump the additional PADCFG registers if available */ 341 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 342 if (padcfg) 343 seq_printf(s, " 0x%08x", readl(padcfg)); 344 345 locked = intel_pad_locked(pctrl, pin); 346 acpi = intel_pad_acpi_mode(pctrl, pin); 347 348 if (locked || acpi) { 349 seq_puts(s, " ["); 350 if (locked) 351 seq_puts(s, "LOCKED"); 352 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 353 seq_puts(s, " tx"); 354 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 355 seq_puts(s, " full"); 356 357 if (locked && acpi) 358 seq_puts(s, ", "); 359 360 if (acpi) 361 seq_puts(s, "ACPI"); 362 seq_puts(s, "]"); 363 } 364 } 365 366 static const struct pinctrl_ops intel_pinctrl_ops = { 367 .get_groups_count = intel_get_groups_count, 368 .get_group_name = intel_get_group_name, 369 .get_group_pins = intel_get_group_pins, 370 .pin_dbg_show = intel_pin_dbg_show, 371 }; 372 373 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 374 { 375 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 376 377 return pctrl->soc->nfunctions; 378 } 379 380 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 381 unsigned int function) 382 { 383 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 384 385 return pctrl->soc->functions[function].name; 386 } 387 388 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 389 unsigned int function, 390 const char * const **groups, 391 unsigned int * const ngroups) 392 { 393 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 394 395 *groups = pctrl->soc->functions[function].groups; 396 *ngroups = pctrl->soc->functions[function].ngroups; 397 return 0; 398 } 399 400 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 401 unsigned int function, unsigned int group) 402 { 403 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 404 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 405 unsigned long flags; 406 int i; 407 408 raw_spin_lock_irqsave(&pctrl->lock, flags); 409 410 /* 411 * All pins in the groups needs to be accessible and writable 412 * before we can enable the mux for this group. 413 */ 414 for (i = 0; i < grp->npins; i++) { 415 if (!intel_pad_usable(pctrl, grp->pins[i])) { 416 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 417 return -EBUSY; 418 } 419 } 420 421 /* Now enable the mux setting for each pin in the group */ 422 for (i = 0; i < grp->npins; i++) { 423 void __iomem *padcfg0; 424 u32 value; 425 426 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 427 value = readl(padcfg0); 428 429 value &= ~PADCFG0_PMODE_MASK; 430 431 if (grp->modes) 432 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 433 else 434 value |= grp->mode << PADCFG0_PMODE_SHIFT; 435 436 writel(value, padcfg0); 437 } 438 439 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 440 441 return 0; 442 } 443 444 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 445 { 446 u32 value; 447 448 value = readl(padcfg0); 449 if (input) { 450 value &= ~PADCFG0_GPIORXDIS; 451 value |= PADCFG0_GPIOTXDIS; 452 } else { 453 value &= ~PADCFG0_GPIOTXDIS; 454 value |= PADCFG0_GPIORXDIS; 455 } 456 writel(value, padcfg0); 457 } 458 459 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 460 { 461 u32 value; 462 463 /* Put the pad into GPIO mode */ 464 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 465 /* Disable SCI/SMI/NMI generation */ 466 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 467 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 468 writel(value, padcfg0); 469 } 470 471 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 472 struct pinctrl_gpio_range *range, 473 unsigned int pin) 474 { 475 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 476 void __iomem *padcfg0; 477 unsigned long flags; 478 479 raw_spin_lock_irqsave(&pctrl->lock, flags); 480 481 if (!intel_pad_owned_by_host(pctrl, pin)) { 482 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 483 return -EBUSY; 484 } 485 486 if (!intel_pad_is_unlocked(pctrl, pin)) { 487 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 488 return 0; 489 } 490 491 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 492 intel_gpio_set_gpio_mode(padcfg0); 493 /* Disable TX buffer and enable RX (this will be input) */ 494 __intel_gpio_set_direction(padcfg0, true); 495 496 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 497 498 return 0; 499 } 500 501 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 502 struct pinctrl_gpio_range *range, 503 unsigned int pin, bool input) 504 { 505 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 506 void __iomem *padcfg0; 507 unsigned long flags; 508 509 raw_spin_lock_irqsave(&pctrl->lock, flags); 510 511 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 512 __intel_gpio_set_direction(padcfg0, input); 513 514 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 515 516 return 0; 517 } 518 519 static const struct pinmux_ops intel_pinmux_ops = { 520 .get_functions_count = intel_get_functions_count, 521 .get_function_name = intel_get_function_name, 522 .get_function_groups = intel_get_function_groups, 523 .set_mux = intel_pinmux_set_mux, 524 .gpio_request_enable = intel_gpio_request_enable, 525 .gpio_set_direction = intel_gpio_set_direction, 526 }; 527 528 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 529 unsigned long *config) 530 { 531 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 532 enum pin_config_param param = pinconf_to_config_param(*config); 533 const struct intel_community *community; 534 u32 value, term; 535 u32 arg = 0; 536 537 if (!intel_pad_owned_by_host(pctrl, pin)) 538 return -ENOTSUPP; 539 540 community = intel_get_community(pctrl, pin); 541 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 542 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 543 544 switch (param) { 545 case PIN_CONFIG_BIAS_DISABLE: 546 if (term) 547 return -EINVAL; 548 break; 549 550 case PIN_CONFIG_BIAS_PULL_UP: 551 if (!term || !(value & PADCFG1_TERM_UP)) 552 return -EINVAL; 553 554 switch (term) { 555 case PADCFG1_TERM_1K: 556 arg = 1000; 557 break; 558 case PADCFG1_TERM_2K: 559 arg = 2000; 560 break; 561 case PADCFG1_TERM_5K: 562 arg = 5000; 563 break; 564 case PADCFG1_TERM_20K: 565 arg = 20000; 566 break; 567 } 568 569 break; 570 571 case PIN_CONFIG_BIAS_PULL_DOWN: 572 if (!term || value & PADCFG1_TERM_UP) 573 return -EINVAL; 574 575 switch (term) { 576 case PADCFG1_TERM_1K: 577 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 578 return -EINVAL; 579 arg = 1000; 580 break; 581 case PADCFG1_TERM_5K: 582 arg = 5000; 583 break; 584 case PADCFG1_TERM_20K: 585 arg = 20000; 586 break; 587 } 588 589 break; 590 591 case PIN_CONFIG_INPUT_DEBOUNCE: { 592 void __iomem *padcfg2; 593 u32 v; 594 595 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 596 if (!padcfg2) 597 return -ENOTSUPP; 598 599 v = readl(padcfg2); 600 if (!(v & PADCFG2_DEBEN)) 601 return -EINVAL; 602 603 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 604 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 605 606 break; 607 } 608 609 default: 610 return -ENOTSUPP; 611 } 612 613 *config = pinconf_to_config_packed(param, arg); 614 return 0; 615 } 616 617 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 618 unsigned long config) 619 { 620 unsigned int param = pinconf_to_config_param(config); 621 unsigned int arg = pinconf_to_config_argument(config); 622 const struct intel_community *community; 623 void __iomem *padcfg1; 624 unsigned long flags; 625 int ret = 0; 626 u32 value; 627 628 raw_spin_lock_irqsave(&pctrl->lock, flags); 629 630 community = intel_get_community(pctrl, pin); 631 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 632 value = readl(padcfg1); 633 634 switch (param) { 635 case PIN_CONFIG_BIAS_DISABLE: 636 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 637 break; 638 639 case PIN_CONFIG_BIAS_PULL_UP: 640 value &= ~PADCFG1_TERM_MASK; 641 642 value |= PADCFG1_TERM_UP; 643 644 switch (arg) { 645 case 20000: 646 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 647 break; 648 case 5000: 649 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 650 break; 651 case 2000: 652 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 653 break; 654 case 1000: 655 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 656 break; 657 default: 658 ret = -EINVAL; 659 } 660 661 break; 662 663 case PIN_CONFIG_BIAS_PULL_DOWN: 664 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 665 666 switch (arg) { 667 case 20000: 668 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 669 break; 670 case 5000: 671 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 672 break; 673 case 1000: 674 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 675 ret = -EINVAL; 676 break; 677 } 678 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 679 break; 680 default: 681 ret = -EINVAL; 682 } 683 684 break; 685 } 686 687 if (!ret) 688 writel(value, padcfg1); 689 690 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 691 692 return ret; 693 } 694 695 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 696 unsigned int pin, unsigned int debounce) 697 { 698 void __iomem *padcfg0, *padcfg2; 699 unsigned long flags; 700 u32 value0, value2; 701 int ret = 0; 702 703 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 704 if (!padcfg2) 705 return -ENOTSUPP; 706 707 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 708 709 raw_spin_lock_irqsave(&pctrl->lock, flags); 710 711 value0 = readl(padcfg0); 712 value2 = readl(padcfg2); 713 714 /* Disable glitch filter and debouncer */ 715 value0 &= ~PADCFG0_PREGFRXSEL; 716 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 717 718 if (debounce) { 719 unsigned long v; 720 721 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 722 if (v < 3 || v > 15) { 723 ret = -EINVAL; 724 goto exit_unlock; 725 } else { 726 /* Enable glitch filter and debouncer */ 727 value0 |= PADCFG0_PREGFRXSEL; 728 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 729 value2 |= PADCFG2_DEBEN; 730 } 731 } 732 733 writel(value0, padcfg0); 734 writel(value2, padcfg2); 735 736 exit_unlock: 737 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 738 739 return ret; 740 } 741 742 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 743 unsigned long *configs, unsigned int nconfigs) 744 { 745 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 746 int i, ret; 747 748 if (!intel_pad_usable(pctrl, pin)) 749 return -ENOTSUPP; 750 751 for (i = 0; i < nconfigs; i++) { 752 switch (pinconf_to_config_param(configs[i])) { 753 case PIN_CONFIG_BIAS_DISABLE: 754 case PIN_CONFIG_BIAS_PULL_UP: 755 case PIN_CONFIG_BIAS_PULL_DOWN: 756 ret = intel_config_set_pull(pctrl, pin, configs[i]); 757 if (ret) 758 return ret; 759 break; 760 761 case PIN_CONFIG_INPUT_DEBOUNCE: 762 ret = intel_config_set_debounce(pctrl, pin, 763 pinconf_to_config_argument(configs[i])); 764 if (ret) 765 return ret; 766 break; 767 768 default: 769 return -ENOTSUPP; 770 } 771 } 772 773 return 0; 774 } 775 776 static const struct pinconf_ops intel_pinconf_ops = { 777 .is_generic = true, 778 .pin_config_get = intel_config_get, 779 .pin_config_set = intel_config_set, 780 }; 781 782 static const struct pinctrl_desc intel_pinctrl_desc = { 783 .pctlops = &intel_pinctrl_ops, 784 .pmxops = &intel_pinmux_ops, 785 .confops = &intel_pinconf_ops, 786 .owner = THIS_MODULE, 787 }; 788 789 /** 790 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 791 * @pctrl: Pinctrl structure 792 * @offset: GPIO offset from gpiolib 793 * @community: Community is filled here if not %NULL 794 * @padgrp: Pad group is filled here if not %NULL 795 * 796 * When coming through gpiolib irqchip, the GPIO offset is not 797 * automatically translated to pinctrl pin number. This function can be 798 * used to find out the corresponding pinctrl pin. 799 */ 800 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 801 const struct intel_community **community, 802 const struct intel_padgroup **padgrp) 803 { 804 int i; 805 806 for (i = 0; i < pctrl->ncommunities; i++) { 807 const struct intel_community *comm = &pctrl->communities[i]; 808 int j; 809 810 for (j = 0; j < comm->ngpps; j++) { 811 const struct intel_padgroup *pgrp = &comm->gpps[j]; 812 813 if (pgrp->gpio_base < 0) 814 continue; 815 816 if (offset >= pgrp->gpio_base && 817 offset < pgrp->gpio_base + pgrp->size) { 818 int pin; 819 820 pin = pgrp->base + offset - pgrp->gpio_base; 821 if (community) 822 *community = comm; 823 if (padgrp) 824 *padgrp = pgrp; 825 826 return pin; 827 } 828 } 829 } 830 831 return -EINVAL; 832 } 833 834 /** 835 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 836 * @pctrl: Pinctrl structure 837 * @pin: pin number 838 * 839 * Translate the pin number of pinctrl to GPIO offset 840 */ 841 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 842 { 843 const struct intel_community *community; 844 const struct intel_padgroup *padgrp; 845 846 community = intel_get_community(pctrl, pin); 847 if (!community) 848 return -EINVAL; 849 850 padgrp = intel_community_get_padgroup(community, pin); 851 if (!padgrp) 852 return -EINVAL; 853 854 return pin - padgrp->base + padgrp->gpio_base; 855 } 856 857 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 858 { 859 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 860 void __iomem *reg; 861 u32 padcfg0; 862 int pin; 863 864 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 865 if (pin < 0) 866 return -EINVAL; 867 868 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 869 if (!reg) 870 return -EINVAL; 871 872 padcfg0 = readl(reg); 873 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 874 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 875 876 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 877 } 878 879 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 880 int value) 881 { 882 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 883 unsigned long flags; 884 void __iomem *reg; 885 u32 padcfg0; 886 int pin; 887 888 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 889 if (pin < 0) 890 return; 891 892 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 893 if (!reg) 894 return; 895 896 raw_spin_lock_irqsave(&pctrl->lock, flags); 897 padcfg0 = readl(reg); 898 if (value) 899 padcfg0 |= PADCFG0_GPIOTXSTATE; 900 else 901 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 902 writel(padcfg0, reg); 903 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 904 } 905 906 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 907 { 908 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 909 void __iomem *reg; 910 u32 padcfg0; 911 int pin; 912 913 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 914 if (pin < 0) 915 return -EINVAL; 916 917 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 918 if (!reg) 919 return -EINVAL; 920 921 padcfg0 = readl(reg); 922 923 if (padcfg0 & PADCFG0_PMODE_MASK) 924 return -EINVAL; 925 926 return !!(padcfg0 & PADCFG0_GPIOTXDIS); 927 } 928 929 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 930 { 931 return pinctrl_gpio_direction_input(chip->base + offset); 932 } 933 934 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 935 int value) 936 { 937 intel_gpio_set(chip, offset, value); 938 return pinctrl_gpio_direction_output(chip->base + offset); 939 } 940 941 static const struct gpio_chip intel_gpio_chip = { 942 .owner = THIS_MODULE, 943 .request = gpiochip_generic_request, 944 .free = gpiochip_generic_free, 945 .get_direction = intel_gpio_get_direction, 946 .direction_input = intel_gpio_direction_input, 947 .direction_output = intel_gpio_direction_output, 948 .get = intel_gpio_get, 949 .set = intel_gpio_set, 950 .set_config = gpiochip_generic_config, 951 }; 952 953 static void intel_gpio_irq_ack(struct irq_data *d) 954 { 955 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 956 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 957 const struct intel_community *community; 958 const struct intel_padgroup *padgrp; 959 int pin; 960 961 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 962 if (pin >= 0) { 963 unsigned int gpp, gpp_offset, is_offset; 964 965 gpp = padgrp->reg_num; 966 gpp_offset = padgroup_offset(padgrp, pin); 967 is_offset = community->is_offset + gpp * 4; 968 969 raw_spin_lock(&pctrl->lock); 970 writel(BIT(gpp_offset), community->regs + is_offset); 971 raw_spin_unlock(&pctrl->lock); 972 } 973 } 974 975 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 976 { 977 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 978 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 979 const struct intel_community *community; 980 const struct intel_padgroup *padgrp; 981 int pin; 982 983 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 984 if (pin >= 0) { 985 unsigned int gpp, gpp_offset; 986 unsigned long flags; 987 void __iomem *reg, *is; 988 u32 value; 989 990 gpp = padgrp->reg_num; 991 gpp_offset = padgroup_offset(padgrp, pin); 992 993 reg = community->regs + community->ie_offset + gpp * 4; 994 is = community->regs + community->is_offset + gpp * 4; 995 996 raw_spin_lock_irqsave(&pctrl->lock, flags); 997 998 /* Clear interrupt status first to avoid unexpected interrupt */ 999 writel(BIT(gpp_offset), is); 1000 1001 value = readl(reg); 1002 if (mask) 1003 value &= ~BIT(gpp_offset); 1004 else 1005 value |= BIT(gpp_offset); 1006 writel(value, reg); 1007 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1008 } 1009 } 1010 1011 static void intel_gpio_irq_mask(struct irq_data *d) 1012 { 1013 intel_gpio_irq_mask_unmask(d, true); 1014 } 1015 1016 static void intel_gpio_irq_unmask(struct irq_data *d) 1017 { 1018 intel_gpio_irq_mask_unmask(d, false); 1019 } 1020 1021 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1022 { 1023 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1024 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1025 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1026 unsigned long flags; 1027 void __iomem *reg; 1028 u32 value; 1029 1030 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1031 if (!reg) 1032 return -EINVAL; 1033 1034 /* 1035 * If the pin is in ACPI mode it is still usable as a GPIO but it 1036 * cannot be used as IRQ because GPI_IS status bit will not be 1037 * updated by the host controller hardware. 1038 */ 1039 if (intel_pad_acpi_mode(pctrl, pin)) { 1040 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1041 return -EPERM; 1042 } 1043 1044 raw_spin_lock_irqsave(&pctrl->lock, flags); 1045 1046 intel_gpio_set_gpio_mode(reg); 1047 1048 value = readl(reg); 1049 1050 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1051 1052 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1053 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1054 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1055 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1056 value |= PADCFG0_RXINV; 1057 } else if (type & IRQ_TYPE_EDGE_RISING) { 1058 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1059 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1060 if (type & IRQ_TYPE_LEVEL_LOW) 1061 value |= PADCFG0_RXINV; 1062 } else { 1063 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1064 } 1065 1066 writel(value, reg); 1067 1068 if (type & IRQ_TYPE_EDGE_BOTH) 1069 irq_set_handler_locked(d, handle_edge_irq); 1070 else if (type & IRQ_TYPE_LEVEL_MASK) 1071 irq_set_handler_locked(d, handle_level_irq); 1072 1073 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1074 1075 return 0; 1076 } 1077 1078 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1079 { 1080 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1081 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1082 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1083 1084 if (on) 1085 enable_irq_wake(pctrl->irq); 1086 else 1087 disable_irq_wake(pctrl->irq); 1088 1089 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1090 return 0; 1091 } 1092 1093 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1094 const struct intel_community *community) 1095 { 1096 struct gpio_chip *gc = &pctrl->chip; 1097 irqreturn_t ret = IRQ_NONE; 1098 int gpp; 1099 1100 for (gpp = 0; gpp < community->ngpps; gpp++) { 1101 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1102 unsigned long pending, enabled, gpp_offset; 1103 1104 pending = readl(community->regs + community->is_offset + 1105 padgrp->reg_num * 4); 1106 enabled = readl(community->regs + community->ie_offset + 1107 padgrp->reg_num * 4); 1108 1109 /* Only interrupts that are enabled */ 1110 pending &= enabled; 1111 1112 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1113 unsigned irq; 1114 1115 irq = irq_find_mapping(gc->irq.domain, 1116 padgrp->gpio_base + gpp_offset); 1117 generic_handle_irq(irq); 1118 1119 ret |= IRQ_HANDLED; 1120 } 1121 } 1122 1123 return ret; 1124 } 1125 1126 static irqreturn_t intel_gpio_irq(int irq, void *data) 1127 { 1128 const struct intel_community *community; 1129 struct intel_pinctrl *pctrl = data; 1130 irqreturn_t ret = IRQ_NONE; 1131 int i; 1132 1133 /* Need to check all communities for pending interrupts */ 1134 for (i = 0; i < pctrl->ncommunities; i++) { 1135 community = &pctrl->communities[i]; 1136 ret |= intel_gpio_community_irq_handler(pctrl, community); 1137 } 1138 1139 return ret; 1140 } 1141 1142 static struct irq_chip intel_gpio_irqchip = { 1143 .name = "intel-gpio", 1144 .irq_ack = intel_gpio_irq_ack, 1145 .irq_mask = intel_gpio_irq_mask, 1146 .irq_unmask = intel_gpio_irq_unmask, 1147 .irq_set_type = intel_gpio_irq_type, 1148 .irq_set_wake = intel_gpio_irq_wake, 1149 .flags = IRQCHIP_MASK_ON_SUSPEND, 1150 }; 1151 1152 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, 1153 const struct intel_community *community) 1154 { 1155 int ret = 0, i; 1156 1157 for (i = 0; i < community->ngpps; i++) { 1158 const struct intel_padgroup *gpp = &community->gpps[i]; 1159 1160 if (gpp->gpio_base < 0) 1161 continue; 1162 1163 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1164 gpp->gpio_base, gpp->base, 1165 gpp->size); 1166 if (ret) 1167 return ret; 1168 } 1169 1170 return ret; 1171 } 1172 1173 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1174 { 1175 const struct intel_community *community; 1176 unsigned int ngpio = 0; 1177 int i, j; 1178 1179 for (i = 0; i < pctrl->ncommunities; i++) { 1180 community = &pctrl->communities[i]; 1181 for (j = 0; j < community->ngpps; j++) { 1182 const struct intel_padgroup *gpp = &community->gpps[j]; 1183 1184 if (gpp->gpio_base < 0) 1185 continue; 1186 1187 if (gpp->gpio_base + gpp->size > ngpio) 1188 ngpio = gpp->gpio_base + gpp->size; 1189 } 1190 } 1191 1192 return ngpio; 1193 } 1194 1195 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1196 { 1197 int ret, i; 1198 1199 pctrl->chip = intel_gpio_chip; 1200 1201 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1202 pctrl->chip.label = dev_name(pctrl->dev); 1203 pctrl->chip.parent = pctrl->dev; 1204 pctrl->chip.base = -1; 1205 pctrl->irq = irq; 1206 1207 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1208 if (ret) { 1209 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1210 return ret; 1211 } 1212 1213 for (i = 0; i < pctrl->ncommunities; i++) { 1214 struct intel_community *community = &pctrl->communities[i]; 1215 1216 ret = intel_gpio_add_pin_ranges(pctrl, community); 1217 if (ret) { 1218 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1219 return ret; 1220 } 1221 } 1222 1223 /* 1224 * We need to request the interrupt here (instead of providing chip 1225 * to the irq directly) because on some platforms several GPIO 1226 * controllers share the same interrupt line. 1227 */ 1228 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1229 IRQF_SHARED | IRQF_NO_THREAD, 1230 dev_name(pctrl->dev), pctrl); 1231 if (ret) { 1232 dev_err(pctrl->dev, "failed to request interrupt\n"); 1233 return ret; 1234 } 1235 1236 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 1237 handle_bad_irq, IRQ_TYPE_NONE); 1238 if (ret) { 1239 dev_err(pctrl->dev, "failed to add irqchip\n"); 1240 return ret; 1241 } 1242 1243 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 1244 NULL); 1245 return 0; 1246 } 1247 1248 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1249 struct intel_community *community) 1250 { 1251 struct intel_padgroup *gpps; 1252 unsigned int npins = community->npins; 1253 unsigned int padown_num = 0; 1254 size_t ngpps, i; 1255 1256 if (community->gpps) 1257 ngpps = community->ngpps; 1258 else 1259 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1260 1261 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1262 if (!gpps) 1263 return -ENOMEM; 1264 1265 for (i = 0; i < ngpps; i++) { 1266 if (community->gpps) { 1267 gpps[i] = community->gpps[i]; 1268 } else { 1269 unsigned int gpp_size = community->gpp_size; 1270 1271 gpps[i].reg_num = i; 1272 gpps[i].base = community->pin_base + i * gpp_size; 1273 gpps[i].size = min(gpp_size, npins); 1274 npins -= gpps[i].size; 1275 } 1276 1277 if (gpps[i].size > 32) 1278 return -EINVAL; 1279 1280 if (!gpps[i].gpio_base) 1281 gpps[i].gpio_base = gpps[i].base; 1282 1283 gpps[i].padown_num = padown_num; 1284 1285 /* 1286 * In older hardware the number of padown registers per 1287 * group is fixed regardless of the group size. 1288 */ 1289 if (community->gpp_num_padown_regs) 1290 padown_num += community->gpp_num_padown_regs; 1291 else 1292 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1293 } 1294 1295 community->ngpps = ngpps; 1296 community->gpps = gpps; 1297 1298 return 0; 1299 } 1300 1301 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1302 { 1303 #ifdef CONFIG_PM_SLEEP 1304 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1305 struct intel_community_context *communities; 1306 struct intel_pad_context *pads; 1307 int i; 1308 1309 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1310 if (!pads) 1311 return -ENOMEM; 1312 1313 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1314 sizeof(*communities), GFP_KERNEL); 1315 if (!communities) 1316 return -ENOMEM; 1317 1318 1319 for (i = 0; i < pctrl->ncommunities; i++) { 1320 struct intel_community *community = &pctrl->communities[i]; 1321 u32 *intmask, *hostown; 1322 1323 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1324 sizeof(*intmask), GFP_KERNEL); 1325 if (!intmask) 1326 return -ENOMEM; 1327 1328 communities[i].intmask = intmask; 1329 1330 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1331 sizeof(*hostown), GFP_KERNEL); 1332 if (!hostown) 1333 return -ENOMEM; 1334 1335 communities[i].hostown = hostown; 1336 } 1337 1338 pctrl->context.pads = pads; 1339 pctrl->context.communities = communities; 1340 #endif 1341 1342 return 0; 1343 } 1344 1345 static int intel_pinctrl_probe(struct platform_device *pdev, 1346 const struct intel_pinctrl_soc_data *soc_data) 1347 { 1348 struct intel_pinctrl *pctrl; 1349 int i, ret, irq; 1350 1351 if (!soc_data) 1352 return -EINVAL; 1353 1354 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1355 if (!pctrl) 1356 return -ENOMEM; 1357 1358 pctrl->dev = &pdev->dev; 1359 pctrl->soc = soc_data; 1360 raw_spin_lock_init(&pctrl->lock); 1361 1362 /* 1363 * Make a copy of the communities which we can use to hold pointers 1364 * to the registers. 1365 */ 1366 pctrl->ncommunities = pctrl->soc->ncommunities; 1367 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1368 sizeof(*pctrl->communities), GFP_KERNEL); 1369 if (!pctrl->communities) 1370 return -ENOMEM; 1371 1372 for (i = 0; i < pctrl->ncommunities; i++) { 1373 struct intel_community *community = &pctrl->communities[i]; 1374 void __iomem *regs; 1375 u32 padbar; 1376 1377 *community = pctrl->soc->communities[i]; 1378 1379 regs = devm_platform_ioremap_resource(pdev, community->barno); 1380 if (IS_ERR(regs)) 1381 return PTR_ERR(regs); 1382 1383 /* 1384 * Determine community features based on the revision if 1385 * not specified already. 1386 */ 1387 if (!community->features) { 1388 u32 rev; 1389 1390 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1391 if (rev >= 0x94) { 1392 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1393 community->features |= PINCTRL_FEATURE_1K_PD; 1394 } 1395 } 1396 1397 /* Read offset of the pad configuration registers */ 1398 padbar = readl(regs + PADBAR); 1399 1400 community->regs = regs; 1401 community->pad_regs = regs + padbar; 1402 1403 ret = intel_pinctrl_add_padgroups(pctrl, community); 1404 if (ret) 1405 return ret; 1406 } 1407 1408 irq = platform_get_irq(pdev, 0); 1409 if (irq < 0) 1410 return irq; 1411 1412 ret = intel_pinctrl_pm_init(pctrl); 1413 if (ret) 1414 return ret; 1415 1416 pctrl->pctldesc = intel_pinctrl_desc; 1417 pctrl->pctldesc.name = dev_name(&pdev->dev); 1418 pctrl->pctldesc.pins = pctrl->soc->pins; 1419 pctrl->pctldesc.npins = pctrl->soc->npins; 1420 1421 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1422 pctrl); 1423 if (IS_ERR(pctrl->pctldev)) { 1424 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1425 return PTR_ERR(pctrl->pctldev); 1426 } 1427 1428 ret = intel_gpio_probe(pctrl, irq); 1429 if (ret) 1430 return ret; 1431 1432 platform_set_drvdata(pdev, pctrl); 1433 1434 return 0; 1435 } 1436 1437 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1438 { 1439 const struct intel_pinctrl_soc_data *data; 1440 1441 data = device_get_match_data(&pdev->dev); 1442 return intel_pinctrl_probe(pdev, data); 1443 } 1444 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1445 1446 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1447 { 1448 const struct intel_pinctrl_soc_data *data = NULL; 1449 const struct intel_pinctrl_soc_data **table; 1450 struct acpi_device *adev; 1451 unsigned int i; 1452 1453 adev = ACPI_COMPANION(&pdev->dev); 1454 if (adev) { 1455 const void *match = device_get_match_data(&pdev->dev); 1456 1457 table = (const struct intel_pinctrl_soc_data **)match; 1458 for (i = 0; table[i]; i++) { 1459 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1460 data = table[i]; 1461 break; 1462 } 1463 } 1464 } else { 1465 const struct platform_device_id *id; 1466 1467 id = platform_get_device_id(pdev); 1468 if (!id) 1469 return -ENODEV; 1470 1471 table = (const struct intel_pinctrl_soc_data **)id->driver_data; 1472 data = table[pdev->id]; 1473 } 1474 1475 return intel_pinctrl_probe(pdev, data); 1476 } 1477 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1478 1479 #ifdef CONFIG_PM_SLEEP 1480 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1481 { 1482 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1483 1484 if (!pd || !intel_pad_usable(pctrl, pin)) 1485 return false; 1486 1487 /* 1488 * Only restore the pin if it is actually in use by the kernel (or 1489 * by userspace). It is possible that some pins are used by the 1490 * BIOS during resume and those are not always locked down so leave 1491 * them alone. 1492 */ 1493 if (pd->mux_owner || pd->gpio_owner || 1494 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1495 return true; 1496 1497 return false; 1498 } 1499 1500 int intel_pinctrl_suspend_noirq(struct device *dev) 1501 { 1502 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1503 struct intel_community_context *communities; 1504 struct intel_pad_context *pads; 1505 int i; 1506 1507 pads = pctrl->context.pads; 1508 for (i = 0; i < pctrl->soc->npins; i++) { 1509 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1510 void __iomem *padcfg; 1511 u32 val; 1512 1513 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1514 continue; 1515 1516 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1517 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1518 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1519 pads[i].padcfg1 = val; 1520 1521 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1522 if (padcfg) 1523 pads[i].padcfg2 = readl(padcfg); 1524 } 1525 1526 communities = pctrl->context.communities; 1527 for (i = 0; i < pctrl->ncommunities; i++) { 1528 struct intel_community *community = &pctrl->communities[i]; 1529 void __iomem *base; 1530 unsigned int gpp; 1531 1532 base = community->regs + community->ie_offset; 1533 for (gpp = 0; gpp < community->ngpps; gpp++) 1534 communities[i].intmask[gpp] = readl(base + gpp * 4); 1535 1536 base = community->regs + community->hostown_offset; 1537 for (gpp = 0; gpp < community->ngpps; gpp++) 1538 communities[i].hostown[gpp] = readl(base + gpp * 4); 1539 } 1540 1541 return 0; 1542 } 1543 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1544 1545 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1546 { 1547 size_t i; 1548 1549 for (i = 0; i < pctrl->ncommunities; i++) { 1550 const struct intel_community *community; 1551 void __iomem *base; 1552 unsigned int gpp; 1553 1554 community = &pctrl->communities[i]; 1555 base = community->regs; 1556 1557 for (gpp = 0; gpp < community->ngpps; gpp++) { 1558 /* Mask and clear all interrupts */ 1559 writel(0, base + community->ie_offset + gpp * 4); 1560 writel(0xffff, base + community->is_offset + gpp * 4); 1561 } 1562 } 1563 } 1564 1565 static u32 1566 intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) 1567 { 1568 u32 requested = 0; 1569 unsigned int i; 1570 1571 for (i = 0; i < size; i++) 1572 if (gpiochip_is_requested(chip, base + i)) 1573 requested |= BIT(i); 1574 1575 return requested; 1576 } 1577 1578 static u32 1579 intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) 1580 { 1581 u32 curr, updated; 1582 1583 curr = readl(hostown); 1584 updated = (curr & ~mask) | (value & mask); 1585 writel(updated, hostown); 1586 1587 return curr; 1588 } 1589 1590 int intel_pinctrl_resume_noirq(struct device *dev) 1591 { 1592 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1593 const struct intel_community_context *communities; 1594 const struct intel_pad_context *pads; 1595 int i; 1596 1597 /* Mask all interrupts */ 1598 intel_gpio_irq_init(pctrl); 1599 1600 pads = pctrl->context.pads; 1601 for (i = 0; i < pctrl->soc->npins; i++) { 1602 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1603 void __iomem *padcfg; 1604 u32 val; 1605 1606 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1607 continue; 1608 1609 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1610 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1611 if (val != pads[i].padcfg0) { 1612 writel(pads[i].padcfg0, padcfg); 1613 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1614 desc->number, readl(padcfg)); 1615 } 1616 1617 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1618 val = readl(padcfg); 1619 if (val != pads[i].padcfg1) { 1620 writel(pads[i].padcfg1, padcfg); 1621 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1622 desc->number, readl(padcfg)); 1623 } 1624 1625 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1626 if (padcfg) { 1627 val = readl(padcfg); 1628 if (val != pads[i].padcfg2) { 1629 writel(pads[i].padcfg2, padcfg); 1630 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", 1631 desc->number, readl(padcfg)); 1632 } 1633 } 1634 } 1635 1636 communities = pctrl->context.communities; 1637 for (i = 0; i < pctrl->ncommunities; i++) { 1638 struct intel_community *community = &pctrl->communities[i]; 1639 void __iomem *base; 1640 unsigned int gpp; 1641 1642 base = community->regs + community->ie_offset; 1643 for (gpp = 0; gpp < community->ngpps; gpp++) { 1644 writel(communities[i].intmask[gpp], base + gpp * 4); 1645 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1646 readl(base + gpp * 4)); 1647 } 1648 1649 base = community->regs + community->hostown_offset; 1650 for (gpp = 0; gpp < community->ngpps; gpp++) { 1651 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1652 u32 requested = 0, value = 0; 1653 u32 saved = communities[i].hostown[gpp]; 1654 1655 if (padgrp->gpio_base < 0) 1656 continue; 1657 1658 requested = intel_gpio_is_requested(&pctrl->chip, 1659 padgrp->gpio_base, padgrp->size); 1660 value = intel_gpio_update_pad_mode(base + gpp * 4, 1661 requested, saved); 1662 if ((value ^ saved) & requested) { 1663 dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n", 1664 i, gpp, value, saved); 1665 } 1666 } 1667 } 1668 1669 return 0; 1670 } 1671 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1672 #endif 1673 1674 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1675 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1676 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1677 MODULE_LICENSE("GPL v2"); 1678