1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 #include <linux/string_helpers.h> 19 #include <linux/time.h> 20 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include <linux/platform_data/x86/pwm-lpss.h> 28 29 #include "../core.h" 30 #include "pinctrl-intel.h" 31 32 /* Offset from regs */ 33 #define REVID 0x000 34 #define REVID_SHIFT 16 35 #define REVID_MASK GENMASK(31, 16) 36 37 #define CAPLIST 0x004 38 #define CAPLIST_ID_SHIFT 16 39 #define CAPLIST_ID_MASK GENMASK(23, 16) 40 #define CAPLIST_ID_GPIO_HW_INFO 1 41 #define CAPLIST_ID_PWM 2 42 #define CAPLIST_ID_BLINK 3 43 #define CAPLIST_ID_EXP 4 44 #define CAPLIST_NEXT_SHIFT 0 45 #define CAPLIST_NEXT_MASK GENMASK(15, 0) 46 47 #define PADBAR 0x00c 48 49 #define PADOWN_BITS 4 50 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 51 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 52 #define PADOWN_GPP(p) ((p) / 8) 53 54 #define PWMC 0x204 55 56 /* Offset from pad_regs */ 57 #define PADCFG0 0x000 58 #define PADCFG0_RXEVCFG_SHIFT 25 59 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 60 #define PADCFG0_RXEVCFG_LEVEL 0 61 #define PADCFG0_RXEVCFG_EDGE 1 62 #define PADCFG0_RXEVCFG_DISABLED 2 63 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 64 #define PADCFG0_PREGFRXSEL BIT(24) 65 #define PADCFG0_RXINV BIT(23) 66 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 67 #define PADCFG0_GPIROUTSCI BIT(19) 68 #define PADCFG0_GPIROUTSMI BIT(18) 69 #define PADCFG0_GPIROUTNMI BIT(17) 70 #define PADCFG0_PMODE_SHIFT 10 71 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 72 #define PADCFG0_PMODE_GPIO 0 73 #define PADCFG0_GPIORXDIS BIT(9) 74 #define PADCFG0_GPIOTXDIS BIT(8) 75 #define PADCFG0_GPIORXSTATE BIT(1) 76 #define PADCFG0_GPIOTXSTATE BIT(0) 77 78 #define PADCFG1 0x004 79 #define PADCFG1_TERM_UP BIT(13) 80 #define PADCFG1_TERM_SHIFT 10 81 #define PADCFG1_TERM_MASK GENMASK(12, 10) 82 #define PADCFG1_TERM_20K BIT(2) 83 #define PADCFG1_TERM_5K BIT(1) 84 #define PADCFG1_TERM_1K BIT(0) 85 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 86 87 #define PADCFG2 0x008 88 #define PADCFG2_DEBEN BIT(0) 89 #define PADCFG2_DEBOUNCE_SHIFT 1 90 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 91 92 #define DEBOUNCE_PERIOD_NSEC 31250 93 94 struct intel_pad_context { 95 u32 padcfg0; 96 u32 padcfg1; 97 u32 padcfg2; 98 }; 99 100 struct intel_community_context { 101 u32 *intmask; 102 u32 *hostown; 103 }; 104 105 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 106 #define padgroup_offset(g, p) ((p) - (g)->base) 107 108 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 109 unsigned int pin) 110 { 111 struct intel_community *community; 112 int i; 113 114 for (i = 0; i < pctrl->ncommunities; i++) { 115 community = &pctrl->communities[i]; 116 if (pin >= community->pin_base && 117 pin < community->pin_base + community->npins) 118 return community; 119 } 120 121 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 122 return NULL; 123 } 124 125 static const struct intel_padgroup * 126 intel_community_get_padgroup(const struct intel_community *community, 127 unsigned int pin) 128 { 129 int i; 130 131 for (i = 0; i < community->ngpps; i++) { 132 const struct intel_padgroup *padgrp = &community->gpps[i]; 133 134 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 135 return padgrp; 136 } 137 138 return NULL; 139 } 140 141 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 142 unsigned int pin, unsigned int reg) 143 { 144 const struct intel_community *community; 145 unsigned int padno; 146 size_t nregs; 147 148 community = intel_get_community(pctrl, pin); 149 if (!community) 150 return NULL; 151 152 padno = pin_to_padno(community, pin); 153 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 154 155 if (reg >= nregs * 4) 156 return NULL; 157 158 return community->pad_regs + reg + padno * nregs * 4; 159 } 160 161 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 162 { 163 const struct intel_community *community; 164 const struct intel_padgroup *padgrp; 165 unsigned int gpp, offset, gpp_offset; 166 void __iomem *padown; 167 168 community = intel_get_community(pctrl, pin); 169 if (!community) 170 return false; 171 if (!community->padown_offset) 172 return true; 173 174 padgrp = intel_community_get_padgroup(community, pin); 175 if (!padgrp) 176 return false; 177 178 gpp_offset = padgroup_offset(padgrp, pin); 179 gpp = PADOWN_GPP(gpp_offset); 180 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 181 padown = community->regs + offset; 182 183 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 184 } 185 186 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 187 { 188 const struct intel_community *community; 189 const struct intel_padgroup *padgrp; 190 unsigned int offset, gpp_offset; 191 void __iomem *hostown; 192 193 community = intel_get_community(pctrl, pin); 194 if (!community) 195 return true; 196 if (!community->hostown_offset) 197 return false; 198 199 padgrp = intel_community_get_padgroup(community, pin); 200 if (!padgrp) 201 return true; 202 203 gpp_offset = padgroup_offset(padgrp, pin); 204 offset = community->hostown_offset + padgrp->reg_num * 4; 205 hostown = community->regs + offset; 206 207 return !(readl(hostown) & BIT(gpp_offset)); 208 } 209 210 /** 211 * enum - Locking variants of the pad configuration 212 * 213 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 214 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 215 * @PAD_LOCKED_TX: pad configuration TX state is locked 216 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 217 * 218 * Locking is considered as read-only mode for corresponding registers and 219 * their respective fields. That said, TX state bit is locked separately from 220 * the main locking scheme. 221 */ 222 enum { 223 PAD_UNLOCKED = 0, 224 PAD_LOCKED = 1, 225 PAD_LOCKED_TX = 2, 226 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 227 }; 228 229 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 230 { 231 struct intel_community *community; 232 const struct intel_padgroup *padgrp; 233 unsigned int offset, gpp_offset; 234 u32 value; 235 int ret = PAD_UNLOCKED; 236 237 community = intel_get_community(pctrl, pin); 238 if (!community) 239 return PAD_LOCKED_FULL; 240 if (!community->padcfglock_offset) 241 return PAD_UNLOCKED; 242 243 padgrp = intel_community_get_padgroup(community, pin); 244 if (!padgrp) 245 return PAD_LOCKED_FULL; 246 247 gpp_offset = padgroup_offset(padgrp, pin); 248 249 /* 250 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 251 * the pad is considered unlocked. Any other case means that it is 252 * either fully or partially locked. 253 */ 254 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 255 value = readl(community->regs + offset); 256 if (value & BIT(gpp_offset)) 257 ret |= PAD_LOCKED; 258 259 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 260 value = readl(community->regs + offset); 261 if (value & BIT(gpp_offset)) 262 ret |= PAD_LOCKED_TX; 263 264 return ret; 265 } 266 267 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 268 { 269 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 270 } 271 272 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 273 { 274 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 275 } 276 277 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 278 { 279 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 280 281 return pctrl->soc->ngroups; 282 } 283 284 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 285 unsigned int group) 286 { 287 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 288 289 return pctrl->soc->groups[group].grp.name; 290 } 291 292 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 293 const unsigned int **pins, unsigned int *npins) 294 { 295 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 296 297 *pins = pctrl->soc->groups[group].grp.pins; 298 *npins = pctrl->soc->groups[group].grp.npins; 299 return 0; 300 } 301 302 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 303 unsigned int pin) 304 { 305 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 306 void __iomem *padcfg; 307 u32 cfg0, cfg1, mode; 308 int locked; 309 bool acpi; 310 311 if (!intel_pad_owned_by_host(pctrl, pin)) { 312 seq_puts(s, "not available"); 313 return; 314 } 315 316 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 317 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 318 319 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 320 if (mode == PADCFG0_PMODE_GPIO) 321 seq_puts(s, "GPIO "); 322 else 323 seq_printf(s, "mode %d ", mode); 324 325 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 326 327 /* Dump the additional PADCFG registers if available */ 328 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 329 if (padcfg) 330 seq_printf(s, " 0x%08x", readl(padcfg)); 331 332 locked = intel_pad_locked(pctrl, pin); 333 acpi = intel_pad_acpi_mode(pctrl, pin); 334 335 if (locked || acpi) { 336 seq_puts(s, " ["); 337 if (locked) 338 seq_puts(s, "LOCKED"); 339 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 340 seq_puts(s, " tx"); 341 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 342 seq_puts(s, " full"); 343 344 if (locked && acpi) 345 seq_puts(s, ", "); 346 347 if (acpi) 348 seq_puts(s, "ACPI"); 349 seq_puts(s, "]"); 350 } 351 } 352 353 static const struct pinctrl_ops intel_pinctrl_ops = { 354 .get_groups_count = intel_get_groups_count, 355 .get_group_name = intel_get_group_name, 356 .get_group_pins = intel_get_group_pins, 357 .pin_dbg_show = intel_pin_dbg_show, 358 }; 359 360 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 361 { 362 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 363 364 return pctrl->soc->nfunctions; 365 } 366 367 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 368 unsigned int function) 369 { 370 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 371 372 return pctrl->soc->functions[function].name; 373 } 374 375 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 376 unsigned int function, 377 const char * const **groups, 378 unsigned int * const ngroups) 379 { 380 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 381 382 *groups = pctrl->soc->functions[function].groups; 383 *ngroups = pctrl->soc->functions[function].ngroups; 384 return 0; 385 } 386 387 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 388 unsigned int function, unsigned int group) 389 { 390 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 391 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 392 unsigned long flags; 393 int i; 394 395 raw_spin_lock_irqsave(&pctrl->lock, flags); 396 397 /* 398 * All pins in the groups needs to be accessible and writable 399 * before we can enable the mux for this group. 400 */ 401 for (i = 0; i < grp->grp.npins; i++) { 402 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) { 403 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 404 return -EBUSY; 405 } 406 } 407 408 /* Now enable the mux setting for each pin in the group */ 409 for (i = 0; i < grp->grp.npins; i++) { 410 void __iomem *padcfg0; 411 u32 value; 412 413 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); 414 value = readl(padcfg0); 415 416 value &= ~PADCFG0_PMODE_MASK; 417 418 if (grp->modes) 419 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 420 else 421 value |= grp->mode << PADCFG0_PMODE_SHIFT; 422 423 writel(value, padcfg0); 424 } 425 426 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 427 428 return 0; 429 } 430 431 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 432 { 433 u32 value; 434 435 value = readl(padcfg0); 436 if (input) { 437 value &= ~PADCFG0_GPIORXDIS; 438 value |= PADCFG0_GPIOTXDIS; 439 } else { 440 value &= ~PADCFG0_GPIOTXDIS; 441 value |= PADCFG0_GPIORXDIS; 442 } 443 writel(value, padcfg0); 444 } 445 446 static int __intel_gpio_get_gpio_mode(u32 value) 447 { 448 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 449 } 450 451 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 452 { 453 return __intel_gpio_get_gpio_mode(readl(padcfg0)); 454 } 455 456 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 457 { 458 u32 value; 459 460 value = readl(padcfg0); 461 462 /* Put the pad into GPIO mode */ 463 value &= ~PADCFG0_PMODE_MASK; 464 value |= PADCFG0_PMODE_GPIO; 465 466 /* Disable TX buffer and enable RX (this will be input) */ 467 value &= ~PADCFG0_GPIORXDIS; 468 value |= PADCFG0_GPIOTXDIS; 469 470 /* Disable SCI/SMI/NMI generation */ 471 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 472 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 473 474 writel(value, padcfg0); 475 } 476 477 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 478 struct pinctrl_gpio_range *range, 479 unsigned int pin) 480 { 481 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 482 void __iomem *padcfg0; 483 unsigned long flags; 484 485 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 486 487 raw_spin_lock_irqsave(&pctrl->lock, flags); 488 489 if (!intel_pad_owned_by_host(pctrl, pin)) { 490 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 491 return -EBUSY; 492 } 493 494 if (!intel_pad_is_unlocked(pctrl, pin)) { 495 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 496 return 0; 497 } 498 499 /* 500 * If pin is already configured in GPIO mode, we assume that 501 * firmware provides correct settings. In such case we avoid 502 * potential glitches on the pin. Otherwise, for the pin in 503 * alternative mode, consumer has to supply respective flags. 504 */ 505 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 506 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 507 return 0; 508 } 509 510 intel_gpio_set_gpio_mode(padcfg0); 511 512 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 513 514 return 0; 515 } 516 517 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 518 struct pinctrl_gpio_range *range, 519 unsigned int pin, bool input) 520 { 521 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 522 void __iomem *padcfg0; 523 unsigned long flags; 524 525 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 526 527 raw_spin_lock_irqsave(&pctrl->lock, flags); 528 __intel_gpio_set_direction(padcfg0, input); 529 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 530 531 return 0; 532 } 533 534 static const struct pinmux_ops intel_pinmux_ops = { 535 .get_functions_count = intel_get_functions_count, 536 .get_function_name = intel_get_function_name, 537 .get_function_groups = intel_get_function_groups, 538 .set_mux = intel_pinmux_set_mux, 539 .gpio_request_enable = intel_gpio_request_enable, 540 .gpio_set_direction = intel_gpio_set_direction, 541 }; 542 543 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 544 enum pin_config_param param, u32 *arg) 545 { 546 const struct intel_community *community; 547 void __iomem *padcfg1; 548 unsigned long flags; 549 u32 value, term; 550 551 community = intel_get_community(pctrl, pin); 552 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 553 554 raw_spin_lock_irqsave(&pctrl->lock, flags); 555 value = readl(padcfg1); 556 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 557 558 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 559 560 switch (param) { 561 case PIN_CONFIG_BIAS_DISABLE: 562 if (term) 563 return -EINVAL; 564 break; 565 566 case PIN_CONFIG_BIAS_PULL_UP: 567 if (!term || !(value & PADCFG1_TERM_UP)) 568 return -EINVAL; 569 570 switch (term) { 571 case PADCFG1_TERM_833: 572 *arg = 833; 573 break; 574 case PADCFG1_TERM_1K: 575 *arg = 1000; 576 break; 577 case PADCFG1_TERM_5K: 578 *arg = 5000; 579 break; 580 case PADCFG1_TERM_20K: 581 *arg = 20000; 582 break; 583 } 584 585 break; 586 587 case PIN_CONFIG_BIAS_PULL_DOWN: 588 if (!term || value & PADCFG1_TERM_UP) 589 return -EINVAL; 590 591 switch (term) { 592 case PADCFG1_TERM_833: 593 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 594 return -EINVAL; 595 *arg = 833; 596 break; 597 case PADCFG1_TERM_1K: 598 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 599 return -EINVAL; 600 *arg = 1000; 601 break; 602 case PADCFG1_TERM_5K: 603 *arg = 5000; 604 break; 605 case PADCFG1_TERM_20K: 606 *arg = 20000; 607 break; 608 } 609 610 break; 611 612 default: 613 return -EINVAL; 614 } 615 616 return 0; 617 } 618 619 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 620 enum pin_config_param param, u32 *arg) 621 { 622 void __iomem *padcfg2; 623 unsigned long flags; 624 unsigned long v; 625 u32 value2; 626 627 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 628 if (!padcfg2) 629 return -ENOTSUPP; 630 631 raw_spin_lock_irqsave(&pctrl->lock, flags); 632 value2 = readl(padcfg2); 633 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 634 if (!(value2 & PADCFG2_DEBEN)) 635 return -EINVAL; 636 637 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 638 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 639 640 return 0; 641 } 642 643 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 644 unsigned long *config) 645 { 646 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 647 enum pin_config_param param = pinconf_to_config_param(*config); 648 u32 arg = 0; 649 int ret; 650 651 if (!intel_pad_owned_by_host(pctrl, pin)) 652 return -ENOTSUPP; 653 654 switch (param) { 655 case PIN_CONFIG_BIAS_DISABLE: 656 case PIN_CONFIG_BIAS_PULL_UP: 657 case PIN_CONFIG_BIAS_PULL_DOWN: 658 ret = intel_config_get_pull(pctrl, pin, param, &arg); 659 if (ret) 660 return ret; 661 break; 662 663 case PIN_CONFIG_INPUT_DEBOUNCE: 664 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 665 if (ret) 666 return ret; 667 break; 668 669 default: 670 return -ENOTSUPP; 671 } 672 673 *config = pinconf_to_config_packed(param, arg); 674 return 0; 675 } 676 677 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 678 unsigned long config) 679 { 680 unsigned int param = pinconf_to_config_param(config); 681 unsigned int arg = pinconf_to_config_argument(config); 682 const struct intel_community *community; 683 void __iomem *padcfg1; 684 unsigned long flags; 685 int ret = 0; 686 u32 value; 687 688 community = intel_get_community(pctrl, pin); 689 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 690 691 raw_spin_lock_irqsave(&pctrl->lock, flags); 692 693 value = readl(padcfg1); 694 695 switch (param) { 696 case PIN_CONFIG_BIAS_DISABLE: 697 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 698 break; 699 700 case PIN_CONFIG_BIAS_PULL_UP: 701 value &= ~PADCFG1_TERM_MASK; 702 703 value |= PADCFG1_TERM_UP; 704 705 /* Set default strength value in case none is given */ 706 if (arg == 1) 707 arg = 5000; 708 709 switch (arg) { 710 case 20000: 711 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 712 break; 713 case 5000: 714 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 715 break; 716 case 1000: 717 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 718 break; 719 case 833: 720 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 721 break; 722 default: 723 ret = -EINVAL; 724 } 725 726 break; 727 728 case PIN_CONFIG_BIAS_PULL_DOWN: 729 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 730 731 /* Set default strength value in case none is given */ 732 if (arg == 1) 733 arg = 5000; 734 735 switch (arg) { 736 case 20000: 737 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 738 break; 739 case 5000: 740 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 741 break; 742 case 1000: 743 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 744 ret = -EINVAL; 745 break; 746 } 747 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 748 break; 749 case 833: 750 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 751 ret = -EINVAL; 752 break; 753 } 754 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 755 break; 756 default: 757 ret = -EINVAL; 758 } 759 760 break; 761 } 762 763 if (!ret) 764 writel(value, padcfg1); 765 766 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 767 768 return ret; 769 } 770 771 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 772 unsigned int pin, unsigned int debounce) 773 { 774 void __iomem *padcfg0, *padcfg2; 775 unsigned long flags; 776 u32 value0, value2; 777 778 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 779 if (!padcfg2) 780 return -ENOTSUPP; 781 782 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 783 784 raw_spin_lock_irqsave(&pctrl->lock, flags); 785 786 value0 = readl(padcfg0); 787 value2 = readl(padcfg2); 788 789 /* Disable glitch filter and debouncer */ 790 value0 &= ~PADCFG0_PREGFRXSEL; 791 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 792 793 if (debounce) { 794 unsigned long v; 795 796 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 797 if (v < 3 || v > 15) { 798 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 799 return -EINVAL; 800 } 801 802 /* Enable glitch filter and debouncer */ 803 value0 |= PADCFG0_PREGFRXSEL; 804 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 805 value2 |= PADCFG2_DEBEN; 806 } 807 808 writel(value0, padcfg0); 809 writel(value2, padcfg2); 810 811 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 812 813 return 0; 814 } 815 816 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 817 unsigned long *configs, unsigned int nconfigs) 818 { 819 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 820 int i, ret; 821 822 if (!intel_pad_usable(pctrl, pin)) 823 return -ENOTSUPP; 824 825 for (i = 0; i < nconfigs; i++) { 826 switch (pinconf_to_config_param(configs[i])) { 827 case PIN_CONFIG_BIAS_DISABLE: 828 case PIN_CONFIG_BIAS_PULL_UP: 829 case PIN_CONFIG_BIAS_PULL_DOWN: 830 ret = intel_config_set_pull(pctrl, pin, configs[i]); 831 if (ret) 832 return ret; 833 break; 834 835 case PIN_CONFIG_INPUT_DEBOUNCE: 836 ret = intel_config_set_debounce(pctrl, pin, 837 pinconf_to_config_argument(configs[i])); 838 if (ret) 839 return ret; 840 break; 841 842 default: 843 return -ENOTSUPP; 844 } 845 } 846 847 return 0; 848 } 849 850 static const struct pinconf_ops intel_pinconf_ops = { 851 .is_generic = true, 852 .pin_config_get = intel_config_get, 853 .pin_config_set = intel_config_set, 854 }; 855 856 static const struct pinctrl_desc intel_pinctrl_desc = { 857 .pctlops = &intel_pinctrl_ops, 858 .pmxops = &intel_pinmux_ops, 859 .confops = &intel_pinconf_ops, 860 .owner = THIS_MODULE, 861 }; 862 863 /** 864 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 865 * @pctrl: Pinctrl structure 866 * @offset: GPIO offset from gpiolib 867 * @community: Community is filled here if not %NULL 868 * @padgrp: Pad group is filled here if not %NULL 869 * 870 * When coming through gpiolib irqchip, the GPIO offset is not 871 * automatically translated to pinctrl pin number. This function can be 872 * used to find out the corresponding pinctrl pin. 873 * 874 * Return: a pin number and pointers to the community and pad group, which 875 * the pin belongs to, or negative error code if translation can't be done. 876 */ 877 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 878 const struct intel_community **community, 879 const struct intel_padgroup **padgrp) 880 { 881 int i; 882 883 for (i = 0; i < pctrl->ncommunities; i++) { 884 const struct intel_community *comm = &pctrl->communities[i]; 885 int j; 886 887 for (j = 0; j < comm->ngpps; j++) { 888 const struct intel_padgroup *pgrp = &comm->gpps[j]; 889 890 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 891 continue; 892 893 if (offset >= pgrp->gpio_base && 894 offset < pgrp->gpio_base + pgrp->size) { 895 int pin; 896 897 pin = pgrp->base + offset - pgrp->gpio_base; 898 if (community) 899 *community = comm; 900 if (padgrp) 901 *padgrp = pgrp; 902 903 return pin; 904 } 905 } 906 } 907 908 return -EINVAL; 909 } 910 911 /** 912 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 913 * @pctrl: Pinctrl structure 914 * @pin: pin number 915 * 916 * Translate the pin number of pinctrl to GPIO offset 917 * 918 * Return: a GPIO offset, or negative error code if translation can't be done. 919 */ 920 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 921 { 922 const struct intel_community *community; 923 const struct intel_padgroup *padgrp; 924 925 community = intel_get_community(pctrl, pin); 926 if (!community) 927 return -EINVAL; 928 929 padgrp = intel_community_get_padgroup(community, pin); 930 if (!padgrp) 931 return -EINVAL; 932 933 return pin - padgrp->base + padgrp->gpio_base; 934 } 935 936 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 937 { 938 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 939 void __iomem *reg; 940 u32 padcfg0; 941 int pin; 942 943 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 944 if (pin < 0) 945 return -EINVAL; 946 947 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 948 if (!reg) 949 return -EINVAL; 950 951 padcfg0 = readl(reg); 952 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 953 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 954 955 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 956 } 957 958 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 959 int value) 960 { 961 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 962 unsigned long flags; 963 void __iomem *reg; 964 u32 padcfg0; 965 int pin; 966 967 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 968 if (pin < 0) 969 return; 970 971 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 972 if (!reg) 973 return; 974 975 raw_spin_lock_irqsave(&pctrl->lock, flags); 976 padcfg0 = readl(reg); 977 if (value) 978 padcfg0 |= PADCFG0_GPIOTXSTATE; 979 else 980 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 981 writel(padcfg0, reg); 982 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 983 } 984 985 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 986 { 987 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 988 unsigned long flags; 989 void __iomem *reg; 990 u32 padcfg0; 991 int pin; 992 993 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 994 if (pin < 0) 995 return -EINVAL; 996 997 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 998 if (!reg) 999 return -EINVAL; 1000 1001 raw_spin_lock_irqsave(&pctrl->lock, flags); 1002 padcfg0 = readl(reg); 1003 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1004 if (padcfg0 & PADCFG0_PMODE_MASK) 1005 return -EINVAL; 1006 1007 if (padcfg0 & PADCFG0_GPIOTXDIS) 1008 return GPIO_LINE_DIRECTION_IN; 1009 1010 return GPIO_LINE_DIRECTION_OUT; 1011 } 1012 1013 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1014 { 1015 return pinctrl_gpio_direction_input(chip->base + offset); 1016 } 1017 1018 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1019 int value) 1020 { 1021 intel_gpio_set(chip, offset, value); 1022 return pinctrl_gpio_direction_output(chip->base + offset); 1023 } 1024 1025 static const struct gpio_chip intel_gpio_chip = { 1026 .owner = THIS_MODULE, 1027 .request = gpiochip_generic_request, 1028 .free = gpiochip_generic_free, 1029 .get_direction = intel_gpio_get_direction, 1030 .direction_input = intel_gpio_direction_input, 1031 .direction_output = intel_gpio_direction_output, 1032 .get = intel_gpio_get, 1033 .set = intel_gpio_set, 1034 .set_config = gpiochip_generic_config, 1035 }; 1036 1037 static void intel_gpio_irq_ack(struct irq_data *d) 1038 { 1039 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1040 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1041 const struct intel_community *community; 1042 const struct intel_padgroup *padgrp; 1043 int pin; 1044 1045 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1046 if (pin >= 0) { 1047 unsigned int gpp, gpp_offset, is_offset; 1048 1049 gpp = padgrp->reg_num; 1050 gpp_offset = padgroup_offset(padgrp, pin); 1051 is_offset = community->is_offset + gpp * 4; 1052 1053 raw_spin_lock(&pctrl->lock); 1054 writel(BIT(gpp_offset), community->regs + is_offset); 1055 raw_spin_unlock(&pctrl->lock); 1056 } 1057 } 1058 1059 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1060 { 1061 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1062 const struct intel_community *community; 1063 const struct intel_padgroup *padgrp; 1064 int pin; 1065 1066 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp); 1067 if (pin >= 0) { 1068 unsigned int gpp, gpp_offset; 1069 unsigned long flags; 1070 void __iomem *reg, *is; 1071 u32 value; 1072 1073 gpp = padgrp->reg_num; 1074 gpp_offset = padgroup_offset(padgrp, pin); 1075 1076 reg = community->regs + community->ie_offset + gpp * 4; 1077 is = community->regs + community->is_offset + gpp * 4; 1078 1079 raw_spin_lock_irqsave(&pctrl->lock, flags); 1080 1081 /* Clear interrupt status first to avoid unexpected interrupt */ 1082 writel(BIT(gpp_offset), is); 1083 1084 value = readl(reg); 1085 if (mask) 1086 value &= ~BIT(gpp_offset); 1087 else 1088 value |= BIT(gpp_offset); 1089 writel(value, reg); 1090 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1091 } 1092 } 1093 1094 static void intel_gpio_irq_mask(struct irq_data *d) 1095 { 1096 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1097 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1098 1099 intel_gpio_irq_mask_unmask(gc, hwirq, true); 1100 gpiochip_disable_irq(gc, hwirq); 1101 } 1102 1103 static void intel_gpio_irq_unmask(struct irq_data *d) 1104 { 1105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1106 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1107 1108 gpiochip_enable_irq(gc, hwirq); 1109 intel_gpio_irq_mask_unmask(gc, hwirq, false); 1110 } 1111 1112 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1113 { 1114 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1115 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1116 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1117 unsigned long flags; 1118 void __iomem *reg; 1119 u32 value; 1120 1121 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1122 if (!reg) 1123 return -EINVAL; 1124 1125 /* 1126 * If the pin is in ACPI mode it is still usable as a GPIO but it 1127 * cannot be used as IRQ because GPI_IS status bit will not be 1128 * updated by the host controller hardware. 1129 */ 1130 if (intel_pad_acpi_mode(pctrl, pin)) { 1131 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1132 return -EPERM; 1133 } 1134 1135 raw_spin_lock_irqsave(&pctrl->lock, flags); 1136 1137 intel_gpio_set_gpio_mode(reg); 1138 1139 value = readl(reg); 1140 1141 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1142 1143 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1144 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1145 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1146 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1147 value |= PADCFG0_RXINV; 1148 } else if (type & IRQ_TYPE_EDGE_RISING) { 1149 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1150 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1151 if (type & IRQ_TYPE_LEVEL_LOW) 1152 value |= PADCFG0_RXINV; 1153 } else { 1154 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1155 } 1156 1157 writel(value, reg); 1158 1159 if (type & IRQ_TYPE_EDGE_BOTH) 1160 irq_set_handler_locked(d, handle_edge_irq); 1161 else if (type & IRQ_TYPE_LEVEL_MASK) 1162 irq_set_handler_locked(d, handle_level_irq); 1163 1164 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1165 1166 return 0; 1167 } 1168 1169 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1170 { 1171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1172 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1173 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1174 1175 if (on) 1176 enable_irq_wake(pctrl->irq); 1177 else 1178 disable_irq_wake(pctrl->irq); 1179 1180 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); 1181 return 0; 1182 } 1183 1184 static const struct irq_chip intel_gpio_irq_chip = { 1185 .name = "intel-gpio", 1186 .irq_ack = intel_gpio_irq_ack, 1187 .irq_mask = intel_gpio_irq_mask, 1188 .irq_unmask = intel_gpio_irq_unmask, 1189 .irq_set_type = intel_gpio_irq_type, 1190 .irq_set_wake = intel_gpio_irq_wake, 1191 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 1192 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1193 }; 1194 1195 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1196 const struct intel_community *community) 1197 { 1198 struct gpio_chip *gc = &pctrl->chip; 1199 unsigned int gpp; 1200 int ret = 0; 1201 1202 for (gpp = 0; gpp < community->ngpps; gpp++) { 1203 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1204 unsigned long pending, enabled, gpp_offset; 1205 1206 raw_spin_lock(&pctrl->lock); 1207 1208 pending = readl(community->regs + community->is_offset + 1209 padgrp->reg_num * 4); 1210 enabled = readl(community->regs + community->ie_offset + 1211 padgrp->reg_num * 4); 1212 1213 raw_spin_unlock(&pctrl->lock); 1214 1215 /* Only interrupts that are enabled */ 1216 pending &= enabled; 1217 1218 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1219 unsigned int irq; 1220 1221 irq = irq_find_mapping(gc->irq.domain, 1222 padgrp->gpio_base + gpp_offset); 1223 generic_handle_irq(irq); 1224 } 1225 1226 ret += pending ? 1 : 0; 1227 } 1228 1229 return ret; 1230 } 1231 1232 static irqreturn_t intel_gpio_irq(int irq, void *data) 1233 { 1234 const struct intel_community *community; 1235 struct intel_pinctrl *pctrl = data; 1236 unsigned int i; 1237 int ret = 0; 1238 1239 /* Need to check all communities for pending interrupts */ 1240 for (i = 0; i < pctrl->ncommunities; i++) { 1241 community = &pctrl->communities[i]; 1242 ret += intel_gpio_community_irq_handler(pctrl, community); 1243 } 1244 1245 return IRQ_RETVAL(ret); 1246 } 1247 1248 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1249 { 1250 int i; 1251 1252 for (i = 0; i < pctrl->ncommunities; i++) { 1253 const struct intel_community *community; 1254 void __iomem *base; 1255 unsigned int gpp; 1256 1257 community = &pctrl->communities[i]; 1258 base = community->regs; 1259 1260 for (gpp = 0; gpp < community->ngpps; gpp++) { 1261 /* Mask and clear all interrupts */ 1262 writel(0, base + community->ie_offset + gpp * 4); 1263 writel(0xffff, base + community->is_offset + gpp * 4); 1264 } 1265 } 1266 } 1267 1268 static int intel_gpio_irq_init_hw(struct gpio_chip *gc) 1269 { 1270 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1271 1272 /* 1273 * Make sure the interrupt lines are in a proper state before 1274 * further configuration. 1275 */ 1276 intel_gpio_irq_init(pctrl); 1277 1278 return 0; 1279 } 1280 1281 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1282 const struct intel_community *community) 1283 { 1284 int ret = 0, i; 1285 1286 for (i = 0; i < community->ngpps; i++) { 1287 const struct intel_padgroup *gpp = &community->gpps[i]; 1288 1289 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1290 continue; 1291 1292 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1293 gpp->gpio_base, gpp->base, 1294 gpp->size); 1295 if (ret) 1296 return ret; 1297 } 1298 1299 return ret; 1300 } 1301 1302 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1303 { 1304 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1305 int ret, i; 1306 1307 for (i = 0; i < pctrl->ncommunities; i++) { 1308 struct intel_community *community = &pctrl->communities[i]; 1309 1310 ret = intel_gpio_add_community_ranges(pctrl, community); 1311 if (ret) { 1312 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1313 return ret; 1314 } 1315 } 1316 1317 return 0; 1318 } 1319 1320 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1321 { 1322 const struct intel_community *community; 1323 unsigned int ngpio = 0; 1324 int i, j; 1325 1326 for (i = 0; i < pctrl->ncommunities; i++) { 1327 community = &pctrl->communities[i]; 1328 for (j = 0; j < community->ngpps; j++) { 1329 const struct intel_padgroup *gpp = &community->gpps[j]; 1330 1331 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1332 continue; 1333 1334 if (gpp->gpio_base + gpp->size > ngpio) 1335 ngpio = gpp->gpio_base + gpp->size; 1336 } 1337 } 1338 1339 return ngpio; 1340 } 1341 1342 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1343 { 1344 int ret; 1345 struct gpio_irq_chip *girq; 1346 1347 pctrl->chip = intel_gpio_chip; 1348 1349 /* Setup GPIO chip */ 1350 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1351 pctrl->chip.label = dev_name(pctrl->dev); 1352 pctrl->chip.parent = pctrl->dev; 1353 pctrl->chip.base = -1; 1354 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1355 pctrl->irq = irq; 1356 1357 /* 1358 * On some platforms several GPIO controllers share the same interrupt 1359 * line. 1360 */ 1361 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1362 IRQF_SHARED | IRQF_NO_THREAD, 1363 dev_name(pctrl->dev), pctrl); 1364 if (ret) { 1365 dev_err(pctrl->dev, "failed to request interrupt\n"); 1366 return ret; 1367 } 1368 1369 /* Setup IRQ chip */ 1370 girq = &pctrl->chip.irq; 1371 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip); 1372 /* This will let us handle the IRQ in the driver */ 1373 girq->parent_handler = NULL; 1374 girq->num_parents = 0; 1375 girq->default_type = IRQ_TYPE_NONE; 1376 girq->handler = handle_bad_irq; 1377 girq->init_hw = intel_gpio_irq_init_hw; 1378 1379 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1380 if (ret) { 1381 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1382 return ret; 1383 } 1384 1385 return 0; 1386 } 1387 1388 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, 1389 struct intel_community *community) 1390 { 1391 struct intel_padgroup *gpps; 1392 unsigned int padown_num = 0; 1393 size_t i, ngpps = community->ngpps; 1394 1395 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1396 if (!gpps) 1397 return -ENOMEM; 1398 1399 for (i = 0; i < ngpps; i++) { 1400 gpps[i] = community->gpps[i]; 1401 1402 if (gpps[i].size > 32) 1403 return -EINVAL; 1404 1405 /* Special treatment for GPIO base */ 1406 switch (gpps[i].gpio_base) { 1407 case INTEL_GPIO_BASE_MATCH: 1408 gpps[i].gpio_base = gpps[i].base; 1409 break; 1410 case INTEL_GPIO_BASE_ZERO: 1411 gpps[i].gpio_base = 0; 1412 break; 1413 case INTEL_GPIO_BASE_NOMAP: 1414 break; 1415 default: 1416 break; 1417 } 1418 1419 gpps[i].padown_num = padown_num; 1420 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1421 } 1422 1423 community->gpps = gpps; 1424 1425 return 0; 1426 } 1427 1428 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, 1429 struct intel_community *community) 1430 { 1431 struct intel_padgroup *gpps; 1432 unsigned int npins = community->npins; 1433 unsigned int padown_num = 0; 1434 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); 1435 1436 if (community->gpp_size > 32) 1437 return -EINVAL; 1438 1439 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1440 if (!gpps) 1441 return -ENOMEM; 1442 1443 for (i = 0; i < ngpps; i++) { 1444 unsigned int gpp_size = community->gpp_size; 1445 1446 gpps[i].reg_num = i; 1447 gpps[i].base = community->pin_base + i * gpp_size; 1448 gpps[i].size = min(gpp_size, npins); 1449 npins -= gpps[i].size; 1450 1451 gpps[i].gpio_base = gpps[i].base; 1452 gpps[i].padown_num = padown_num; 1453 1454 /* 1455 * In older hardware the number of padown registers per 1456 * group is fixed regardless of the group size. 1457 */ 1458 if (community->gpp_num_padown_regs) 1459 padown_num += community->gpp_num_padown_regs; 1460 else 1461 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1462 } 1463 1464 community->ngpps = ngpps; 1465 community->gpps = gpps; 1466 1467 return 0; 1468 } 1469 1470 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1471 { 1472 #ifdef CONFIG_PM_SLEEP 1473 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1474 struct intel_community_context *communities; 1475 struct intel_pad_context *pads; 1476 int i; 1477 1478 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1479 if (!pads) 1480 return -ENOMEM; 1481 1482 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1483 sizeof(*communities), GFP_KERNEL); 1484 if (!communities) 1485 return -ENOMEM; 1486 1487 1488 for (i = 0; i < pctrl->ncommunities; i++) { 1489 struct intel_community *community = &pctrl->communities[i]; 1490 u32 *intmask, *hostown; 1491 1492 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1493 sizeof(*intmask), GFP_KERNEL); 1494 if (!intmask) 1495 return -ENOMEM; 1496 1497 communities[i].intmask = intmask; 1498 1499 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1500 sizeof(*hostown), GFP_KERNEL); 1501 if (!hostown) 1502 return -ENOMEM; 1503 1504 communities[i].hostown = hostown; 1505 } 1506 1507 pctrl->context.pads = pads; 1508 pctrl->context.communities = communities; 1509 #endif 1510 1511 return 0; 1512 } 1513 1514 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, 1515 struct intel_community *community) 1516 { 1517 static const struct pwm_lpss_boardinfo info = { 1518 .clk_rate = 19200000, 1519 .npwm = 1, 1520 .base_unit_bits = 22, 1521 .bypass = true, 1522 }; 1523 struct pwm_lpss_chip *pwm; 1524 1525 if (!(community->features & PINCTRL_FEATURE_PWM)) 1526 return 0; 1527 1528 if (!IS_REACHABLE(CONFIG_PWM_LPSS)) 1529 return 0; 1530 1531 pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); 1532 return PTR_ERR_OR_ZERO(pwm); 1533 } 1534 1535 static int intel_pinctrl_probe(struct platform_device *pdev, 1536 const struct intel_pinctrl_soc_data *soc_data) 1537 { 1538 struct device *dev = &pdev->dev; 1539 struct intel_pinctrl *pctrl; 1540 int i, ret, irq; 1541 1542 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1543 if (!pctrl) 1544 return -ENOMEM; 1545 1546 pctrl->dev = dev; 1547 pctrl->soc = soc_data; 1548 raw_spin_lock_init(&pctrl->lock); 1549 1550 /* 1551 * Make a copy of the communities which we can use to hold pointers 1552 * to the registers. 1553 */ 1554 pctrl->ncommunities = pctrl->soc->ncommunities; 1555 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, 1556 sizeof(*pctrl->communities), GFP_KERNEL); 1557 if (!pctrl->communities) 1558 return -ENOMEM; 1559 1560 for (i = 0; i < pctrl->ncommunities; i++) { 1561 struct intel_community *community = &pctrl->communities[i]; 1562 void __iomem *regs; 1563 u32 offset; 1564 u32 value; 1565 1566 *community = pctrl->soc->communities[i]; 1567 1568 regs = devm_platform_ioremap_resource(pdev, community->barno); 1569 if (IS_ERR(regs)) 1570 return PTR_ERR(regs); 1571 1572 /* 1573 * Determine community features based on the revision. 1574 * A value of all ones means the device is not present. 1575 */ 1576 value = readl(regs + REVID); 1577 if (value == ~0u) 1578 return -ENODEV; 1579 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { 1580 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1581 community->features |= PINCTRL_FEATURE_1K_PD; 1582 } 1583 1584 /* Determine community features based on the capabilities */ 1585 offset = CAPLIST; 1586 do { 1587 value = readl(regs + offset); 1588 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { 1589 case CAPLIST_ID_GPIO_HW_INFO: 1590 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; 1591 break; 1592 case CAPLIST_ID_PWM: 1593 community->features |= PINCTRL_FEATURE_PWM; 1594 break; 1595 case CAPLIST_ID_BLINK: 1596 community->features |= PINCTRL_FEATURE_BLINK; 1597 break; 1598 case CAPLIST_ID_EXP: 1599 community->features |= PINCTRL_FEATURE_EXP; 1600 break; 1601 default: 1602 break; 1603 } 1604 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; 1605 } while (offset); 1606 1607 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); 1608 1609 /* Read offset of the pad configuration registers */ 1610 offset = readl(regs + PADBAR); 1611 1612 community->regs = regs; 1613 community->pad_regs = regs + offset; 1614 1615 if (community->gpps) 1616 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); 1617 else 1618 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); 1619 if (ret) 1620 return ret; 1621 1622 ret = intel_pinctrl_probe_pwm(pctrl, community); 1623 if (ret) 1624 return ret; 1625 } 1626 1627 irq = platform_get_irq(pdev, 0); 1628 if (irq < 0) 1629 return irq; 1630 1631 ret = intel_pinctrl_pm_init(pctrl); 1632 if (ret) 1633 return ret; 1634 1635 pctrl->pctldesc = intel_pinctrl_desc; 1636 pctrl->pctldesc.name = dev_name(dev); 1637 pctrl->pctldesc.pins = pctrl->soc->pins; 1638 pctrl->pctldesc.npins = pctrl->soc->npins; 1639 1640 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1641 if (IS_ERR(pctrl->pctldev)) { 1642 dev_err(dev, "failed to register pinctrl driver\n"); 1643 return PTR_ERR(pctrl->pctldev); 1644 } 1645 1646 ret = intel_gpio_probe(pctrl, irq); 1647 if (ret) 1648 return ret; 1649 1650 platform_set_drvdata(pdev, pctrl); 1651 1652 return 0; 1653 } 1654 1655 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1656 { 1657 const struct intel_pinctrl_soc_data *data; 1658 1659 data = device_get_match_data(&pdev->dev); 1660 if (!data) 1661 return -ENODATA; 1662 1663 return intel_pinctrl_probe(pdev, data); 1664 } 1665 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1666 1667 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1668 { 1669 const struct intel_pinctrl_soc_data *data; 1670 1671 data = intel_pinctrl_get_soc_data(pdev); 1672 if (IS_ERR(data)) 1673 return PTR_ERR(data); 1674 1675 return intel_pinctrl_probe(pdev, data); 1676 } 1677 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1678 1679 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1680 { 1681 const struct intel_pinctrl_soc_data * const *table; 1682 const struct intel_pinctrl_soc_data *data = NULL; 1683 struct device *dev = &pdev->dev; 1684 1685 table = device_get_match_data(dev); 1686 if (table) { 1687 struct acpi_device *adev = ACPI_COMPANION(dev); 1688 unsigned int i; 1689 1690 for (i = 0; table[i]; i++) { 1691 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1692 data = table[i]; 1693 break; 1694 } 1695 } 1696 } else { 1697 const struct platform_device_id *id; 1698 1699 id = platform_get_device_id(pdev); 1700 if (!id) 1701 return ERR_PTR(-ENODEV); 1702 1703 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; 1704 data = table[pdev->id]; 1705 } 1706 1707 return data ?: ERR_PTR(-ENODATA); 1708 } 1709 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1710 1711 #ifdef CONFIG_PM_SLEEP 1712 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1713 { 1714 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1715 u32 value; 1716 1717 if (!pd || !intel_pad_usable(pctrl, pin)) 1718 return false; 1719 1720 /* 1721 * Only restore the pin if it is actually in use by the kernel (or 1722 * by userspace). It is possible that some pins are used by the 1723 * BIOS during resume and those are not always locked down so leave 1724 * them alone. 1725 */ 1726 if (pd->mux_owner || pd->gpio_owner || 1727 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1728 return true; 1729 1730 /* 1731 * The firmware on some systems may configure GPIO pins to be 1732 * an interrupt source in so called "direct IRQ" mode. In such 1733 * cases the GPIO controller driver has no idea if those pins 1734 * are being used or not. At the same time, there is a known bug 1735 * in the firmwares that don't restore the pin settings correctly 1736 * after suspend, i.e. by an unknown reason the Rx value becomes 1737 * inverted. 1738 * 1739 * Hence, let's save and restore the pins that are configured 1740 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1741 * 1742 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1743 */ 1744 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1745 if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1746 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO)) 1747 return true; 1748 1749 return false; 1750 } 1751 1752 int intel_pinctrl_suspend_noirq(struct device *dev) 1753 { 1754 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1755 struct intel_community_context *communities; 1756 struct intel_pad_context *pads; 1757 int i; 1758 1759 pads = pctrl->context.pads; 1760 for (i = 0; i < pctrl->soc->npins; i++) { 1761 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1762 void __iomem *padcfg; 1763 u32 val; 1764 1765 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1766 continue; 1767 1768 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1769 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1770 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1771 pads[i].padcfg1 = val; 1772 1773 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1774 if (padcfg) 1775 pads[i].padcfg2 = readl(padcfg); 1776 } 1777 1778 communities = pctrl->context.communities; 1779 for (i = 0; i < pctrl->ncommunities; i++) { 1780 struct intel_community *community = &pctrl->communities[i]; 1781 void __iomem *base; 1782 unsigned int gpp; 1783 1784 base = community->regs + community->ie_offset; 1785 for (gpp = 0; gpp < community->ngpps; gpp++) 1786 communities[i].intmask[gpp] = readl(base + gpp * 4); 1787 1788 base = community->regs + community->hostown_offset; 1789 for (gpp = 0; gpp < community->ngpps; gpp++) 1790 communities[i].hostown[gpp] = readl(base + gpp * 4); 1791 } 1792 1793 return 0; 1794 } 1795 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1796 1797 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1798 { 1799 u32 curr, updated; 1800 1801 curr = readl(reg); 1802 1803 updated = (curr & ~mask) | (value & mask); 1804 if (curr == updated) 1805 return false; 1806 1807 writel(updated, reg); 1808 return true; 1809 } 1810 1811 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1812 void __iomem *base, unsigned int gpp, u32 saved) 1813 { 1814 const struct intel_community *community = &pctrl->communities[c]; 1815 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1816 struct device *dev = pctrl->dev; 1817 const char *dummy; 1818 u32 requested = 0; 1819 unsigned int i; 1820 1821 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1822 return; 1823 1824 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1825 requested |= BIT(i); 1826 1827 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1828 return; 1829 1830 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1831 } 1832 1833 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1834 void __iomem *base, unsigned int gpp, u32 saved) 1835 { 1836 struct device *dev = pctrl->dev; 1837 1838 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1839 return; 1840 1841 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1842 } 1843 1844 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1845 unsigned int reg, u32 saved) 1846 { 1847 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1848 unsigned int n = reg / sizeof(u32); 1849 struct device *dev = pctrl->dev; 1850 void __iomem *padcfg; 1851 1852 padcfg = intel_get_padcfg(pctrl, pin, reg); 1853 if (!padcfg) 1854 return; 1855 1856 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1857 return; 1858 1859 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1860 } 1861 1862 int intel_pinctrl_resume_noirq(struct device *dev) 1863 { 1864 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1865 const struct intel_community_context *communities; 1866 const struct intel_pad_context *pads; 1867 int i; 1868 1869 /* Mask all interrupts */ 1870 intel_gpio_irq_init(pctrl); 1871 1872 pads = pctrl->context.pads; 1873 for (i = 0; i < pctrl->soc->npins; i++) { 1874 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1875 1876 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1877 continue; 1878 1879 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1880 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1881 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1882 } 1883 1884 communities = pctrl->context.communities; 1885 for (i = 0; i < pctrl->ncommunities; i++) { 1886 struct intel_community *community = &pctrl->communities[i]; 1887 void __iomem *base; 1888 unsigned int gpp; 1889 1890 base = community->regs + community->ie_offset; 1891 for (gpp = 0; gpp < community->ngpps; gpp++) 1892 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1893 1894 base = community->regs + community->hostown_offset; 1895 for (gpp = 0; gpp < community->ngpps; gpp++) 1896 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1897 } 1898 1899 return 0; 1900 } 1901 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1902 #endif 1903 1904 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1905 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1906 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1907 MODULE_LICENSE("GPL v2"); 1908