1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/time.h> 18 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 24 #include "../core.h" 25 #include "pinctrl-intel.h" 26 27 /* Offset from regs */ 28 #define REVID 0x000 29 #define REVID_SHIFT 16 30 #define REVID_MASK GENMASK(31, 16) 31 32 #define PADBAR 0x00c 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_PREGFRXSEL BIT(24) 48 #define PADCFG0_RXINV BIT(23) 49 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 50 #define PADCFG0_GPIROUTSCI BIT(19) 51 #define PADCFG0_GPIROUTSMI BIT(18) 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 #define PADCFG0_PMODE_SHIFT 10 54 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 55 #define PADCFG0_PMODE_GPIO 0 56 #define PADCFG0_GPIORXDIS BIT(9) 57 #define PADCFG0_GPIOTXDIS BIT(8) 58 #define PADCFG0_GPIORXSTATE BIT(1) 59 #define PADCFG0_GPIOTXSTATE BIT(0) 60 61 #define PADCFG1 0x004 62 #define PADCFG1_TERM_UP BIT(13) 63 #define PADCFG1_TERM_SHIFT 10 64 #define PADCFG1_TERM_MASK GENMASK(12, 10) 65 #define PADCFG1_TERM_20K BIT(2) 66 #define PADCFG1_TERM_5K BIT(1) 67 #define PADCFG1_TERM_1K BIT(0) 68 #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) 69 70 #define PADCFG2 0x008 71 #define PADCFG2_DEBEN BIT(0) 72 #define PADCFG2_DEBOUNCE_SHIFT 1 73 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 74 75 #define DEBOUNCE_PERIOD_NSEC 31250 76 77 struct intel_pad_context { 78 u32 padcfg0; 79 u32 padcfg1; 80 u32 padcfg2; 81 }; 82 83 struct intel_community_context { 84 u32 *intmask; 85 u32 *hostown; 86 }; 87 88 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 89 #define padgroup_offset(g, p) ((p) - (g)->base) 90 91 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 92 unsigned int pin) 93 { 94 struct intel_community *community; 95 int i; 96 97 for (i = 0; i < pctrl->ncommunities; i++) { 98 community = &pctrl->communities[i]; 99 if (pin >= community->pin_base && 100 pin < community->pin_base + community->npins) 101 return community; 102 } 103 104 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 105 return NULL; 106 } 107 108 static const struct intel_padgroup * 109 intel_community_get_padgroup(const struct intel_community *community, 110 unsigned int pin) 111 { 112 int i; 113 114 for (i = 0; i < community->ngpps; i++) { 115 const struct intel_padgroup *padgrp = &community->gpps[i]; 116 117 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 118 return padgrp; 119 } 120 121 return NULL; 122 } 123 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 125 unsigned int pin, unsigned int reg) 126 { 127 const struct intel_community *community; 128 unsigned int padno; 129 size_t nregs; 130 131 community = intel_get_community(pctrl, pin); 132 if (!community) 133 return NULL; 134 135 padno = pin_to_padno(community, pin); 136 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 137 138 if (reg >= nregs * 4) 139 return NULL; 140 141 return community->pad_regs + reg + padno * nregs * 4; 142 } 143 144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 145 { 146 const struct intel_community *community; 147 const struct intel_padgroup *padgrp; 148 unsigned int gpp, offset, gpp_offset; 149 void __iomem *padown; 150 151 community = intel_get_community(pctrl, pin); 152 if (!community) 153 return false; 154 if (!community->padown_offset) 155 return true; 156 157 padgrp = intel_community_get_padgroup(community, pin); 158 if (!padgrp) 159 return false; 160 161 gpp_offset = padgroup_offset(padgrp, pin); 162 gpp = PADOWN_GPP(gpp_offset); 163 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 164 padown = community->regs + offset; 165 166 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 167 } 168 169 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 170 { 171 const struct intel_community *community; 172 const struct intel_padgroup *padgrp; 173 unsigned int offset, gpp_offset; 174 void __iomem *hostown; 175 176 community = intel_get_community(pctrl, pin); 177 if (!community) 178 return true; 179 if (!community->hostown_offset) 180 return false; 181 182 padgrp = intel_community_get_padgroup(community, pin); 183 if (!padgrp) 184 return true; 185 186 gpp_offset = padgroup_offset(padgrp, pin); 187 offset = community->hostown_offset + padgrp->reg_num * 4; 188 hostown = community->regs + offset; 189 190 return !(readl(hostown) & BIT(gpp_offset)); 191 } 192 193 /** 194 * enum - Locking variants of the pad configuration 195 * 196 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 197 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 198 * @PAD_LOCKED_TX: pad configuration TX state is locked 199 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 200 * 201 * Locking is considered as read-only mode for corresponding registers and 202 * their respective fields. That said, TX state bit is locked separately from 203 * the main locking scheme. 204 */ 205 enum { 206 PAD_UNLOCKED = 0, 207 PAD_LOCKED = 1, 208 PAD_LOCKED_TX = 2, 209 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 210 }; 211 212 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 213 { 214 struct intel_community *community; 215 const struct intel_padgroup *padgrp; 216 unsigned int offset, gpp_offset; 217 u32 value; 218 int ret = PAD_UNLOCKED; 219 220 community = intel_get_community(pctrl, pin); 221 if (!community) 222 return PAD_LOCKED_FULL; 223 if (!community->padcfglock_offset) 224 return PAD_UNLOCKED; 225 226 padgrp = intel_community_get_padgroup(community, pin); 227 if (!padgrp) 228 return PAD_LOCKED_FULL; 229 230 gpp_offset = padgroup_offset(padgrp, pin); 231 232 /* 233 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 234 * the pad is considered unlocked. Any other case means that it is 235 * either fully or partially locked. 236 */ 237 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 238 value = readl(community->regs + offset); 239 if (value & BIT(gpp_offset)) 240 ret |= PAD_LOCKED; 241 242 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 243 value = readl(community->regs + offset); 244 if (value & BIT(gpp_offset)) 245 ret |= PAD_LOCKED_TX; 246 247 return ret; 248 } 249 250 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 251 { 252 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 253 } 254 255 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 256 { 257 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 258 } 259 260 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 261 { 262 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 263 264 return pctrl->soc->ngroups; 265 } 266 267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 268 unsigned int group) 269 { 270 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 271 272 return pctrl->soc->groups[group].name; 273 } 274 275 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 276 const unsigned int **pins, unsigned int *npins) 277 { 278 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 279 280 *pins = pctrl->soc->groups[group].pins; 281 *npins = pctrl->soc->groups[group].npins; 282 return 0; 283 } 284 285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 286 unsigned int pin) 287 { 288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 289 void __iomem *padcfg; 290 u32 cfg0, cfg1, mode; 291 int locked; 292 bool acpi; 293 294 if (!intel_pad_owned_by_host(pctrl, pin)) { 295 seq_puts(s, "not available"); 296 return; 297 } 298 299 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 300 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 301 302 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 303 if (mode == PADCFG0_PMODE_GPIO) 304 seq_puts(s, "GPIO "); 305 else 306 seq_printf(s, "mode %d ", mode); 307 308 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 309 310 /* Dump the additional PADCFG registers if available */ 311 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 312 if (padcfg) 313 seq_printf(s, " 0x%08x", readl(padcfg)); 314 315 locked = intel_pad_locked(pctrl, pin); 316 acpi = intel_pad_acpi_mode(pctrl, pin); 317 318 if (locked || acpi) { 319 seq_puts(s, " ["); 320 if (locked) 321 seq_puts(s, "LOCKED"); 322 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 323 seq_puts(s, " tx"); 324 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 325 seq_puts(s, " full"); 326 327 if (locked && acpi) 328 seq_puts(s, ", "); 329 330 if (acpi) 331 seq_puts(s, "ACPI"); 332 seq_puts(s, "]"); 333 } 334 } 335 336 static const struct pinctrl_ops intel_pinctrl_ops = { 337 .get_groups_count = intel_get_groups_count, 338 .get_group_name = intel_get_group_name, 339 .get_group_pins = intel_get_group_pins, 340 .pin_dbg_show = intel_pin_dbg_show, 341 }; 342 343 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 344 { 345 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 346 347 return pctrl->soc->nfunctions; 348 } 349 350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 351 unsigned int function) 352 { 353 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 354 355 return pctrl->soc->functions[function].name; 356 } 357 358 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 359 unsigned int function, 360 const char * const **groups, 361 unsigned int * const ngroups) 362 { 363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 364 365 *groups = pctrl->soc->functions[function].groups; 366 *ngroups = pctrl->soc->functions[function].ngroups; 367 return 0; 368 } 369 370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 371 unsigned int function, unsigned int group) 372 { 373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 374 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 375 unsigned long flags; 376 int i; 377 378 raw_spin_lock_irqsave(&pctrl->lock, flags); 379 380 /* 381 * All pins in the groups needs to be accessible and writable 382 * before we can enable the mux for this group. 383 */ 384 for (i = 0; i < grp->npins; i++) { 385 if (!intel_pad_usable(pctrl, grp->pins[i])) { 386 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 387 return -EBUSY; 388 } 389 } 390 391 /* Now enable the mux setting for each pin in the group */ 392 for (i = 0; i < grp->npins; i++) { 393 void __iomem *padcfg0; 394 u32 value; 395 396 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 397 value = readl(padcfg0); 398 399 value &= ~PADCFG0_PMODE_MASK; 400 401 if (grp->modes) 402 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 403 else 404 value |= grp->mode << PADCFG0_PMODE_SHIFT; 405 406 writel(value, padcfg0); 407 } 408 409 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 410 411 return 0; 412 } 413 414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 415 { 416 u32 value; 417 418 value = readl(padcfg0); 419 if (input) { 420 value &= ~PADCFG0_GPIORXDIS; 421 value |= PADCFG0_GPIOTXDIS; 422 } else { 423 value &= ~PADCFG0_GPIOTXDIS; 424 value |= PADCFG0_GPIORXDIS; 425 } 426 writel(value, padcfg0); 427 } 428 429 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 430 { 431 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 432 } 433 434 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 435 { 436 u32 value; 437 438 value = readl(padcfg0); 439 440 /* Put the pad into GPIO mode */ 441 value &= ~PADCFG0_PMODE_MASK; 442 value |= PADCFG0_PMODE_GPIO; 443 444 /* Disable input and output buffers */ 445 value |= PADCFG0_GPIORXDIS; 446 value |= PADCFG0_GPIOTXDIS; 447 448 /* Disable SCI/SMI/NMI generation */ 449 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 450 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 451 452 writel(value, padcfg0); 453 } 454 455 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 456 struct pinctrl_gpio_range *range, 457 unsigned int pin) 458 { 459 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 460 void __iomem *padcfg0; 461 unsigned long flags; 462 463 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 464 465 raw_spin_lock_irqsave(&pctrl->lock, flags); 466 467 if (!intel_pad_owned_by_host(pctrl, pin)) { 468 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 469 return -EBUSY; 470 } 471 472 if (!intel_pad_is_unlocked(pctrl, pin)) { 473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 474 return 0; 475 } 476 477 /* 478 * If pin is already configured in GPIO mode, we assume that 479 * firmware provides correct settings. In such case we avoid 480 * potential glitches on the pin. Otherwise, for the pin in 481 * alternative mode, consumer has to supply respective flags. 482 */ 483 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 484 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 485 return 0; 486 } 487 488 intel_gpio_set_gpio_mode(padcfg0); 489 490 /* Disable TX buffer and enable RX (this will be input) */ 491 __intel_gpio_set_direction(padcfg0, true); 492 493 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 494 495 return 0; 496 } 497 498 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 499 struct pinctrl_gpio_range *range, 500 unsigned int pin, bool input) 501 { 502 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 503 void __iomem *padcfg0; 504 unsigned long flags; 505 506 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 507 508 raw_spin_lock_irqsave(&pctrl->lock, flags); 509 __intel_gpio_set_direction(padcfg0, input); 510 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 511 512 return 0; 513 } 514 515 static const struct pinmux_ops intel_pinmux_ops = { 516 .get_functions_count = intel_get_functions_count, 517 .get_function_name = intel_get_function_name, 518 .get_function_groups = intel_get_function_groups, 519 .set_mux = intel_pinmux_set_mux, 520 .gpio_request_enable = intel_gpio_request_enable, 521 .gpio_set_direction = intel_gpio_set_direction, 522 }; 523 524 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 525 enum pin_config_param param, u32 *arg) 526 { 527 const struct intel_community *community; 528 void __iomem *padcfg1; 529 unsigned long flags; 530 u32 value, term; 531 532 community = intel_get_community(pctrl, pin); 533 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 534 535 raw_spin_lock_irqsave(&pctrl->lock, flags); 536 value = readl(padcfg1); 537 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 538 539 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 540 541 switch (param) { 542 case PIN_CONFIG_BIAS_DISABLE: 543 if (term) 544 return -EINVAL; 545 break; 546 547 case PIN_CONFIG_BIAS_PULL_UP: 548 if (!term || !(value & PADCFG1_TERM_UP)) 549 return -EINVAL; 550 551 switch (term) { 552 case PADCFG1_TERM_833: 553 *arg = 833; 554 break; 555 case PADCFG1_TERM_1K: 556 *arg = 1000; 557 break; 558 case PADCFG1_TERM_5K: 559 *arg = 5000; 560 break; 561 case PADCFG1_TERM_20K: 562 *arg = 20000; 563 break; 564 } 565 566 break; 567 568 case PIN_CONFIG_BIAS_PULL_DOWN: 569 if (!term || value & PADCFG1_TERM_UP) 570 return -EINVAL; 571 572 switch (term) { 573 case PADCFG1_TERM_833: 574 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 575 return -EINVAL; 576 *arg = 833; 577 break; 578 case PADCFG1_TERM_1K: 579 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 580 return -EINVAL; 581 *arg = 1000; 582 break; 583 case PADCFG1_TERM_5K: 584 *arg = 5000; 585 break; 586 case PADCFG1_TERM_20K: 587 *arg = 20000; 588 break; 589 } 590 591 break; 592 593 default: 594 return -EINVAL; 595 } 596 597 return 0; 598 } 599 600 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 601 enum pin_config_param param, u32 *arg) 602 { 603 void __iomem *padcfg2; 604 unsigned long flags; 605 unsigned long v; 606 u32 value2; 607 608 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 609 if (!padcfg2) 610 return -ENOTSUPP; 611 612 raw_spin_lock_irqsave(&pctrl->lock, flags); 613 value2 = readl(padcfg2); 614 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 615 if (!(value2 & PADCFG2_DEBEN)) 616 return -EINVAL; 617 618 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 619 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 620 621 return 0; 622 } 623 624 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 625 unsigned long *config) 626 { 627 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 628 enum pin_config_param param = pinconf_to_config_param(*config); 629 u32 arg = 0; 630 int ret; 631 632 if (!intel_pad_owned_by_host(pctrl, pin)) 633 return -ENOTSUPP; 634 635 switch (param) { 636 case PIN_CONFIG_BIAS_DISABLE: 637 case PIN_CONFIG_BIAS_PULL_UP: 638 case PIN_CONFIG_BIAS_PULL_DOWN: 639 ret = intel_config_get_pull(pctrl, pin, param, &arg); 640 if (ret) 641 return ret; 642 break; 643 644 case PIN_CONFIG_INPUT_DEBOUNCE: 645 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 646 if (ret) 647 return ret; 648 break; 649 650 default: 651 return -ENOTSUPP; 652 } 653 654 *config = pinconf_to_config_packed(param, arg); 655 return 0; 656 } 657 658 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 659 unsigned long config) 660 { 661 unsigned int param = pinconf_to_config_param(config); 662 unsigned int arg = pinconf_to_config_argument(config); 663 const struct intel_community *community; 664 void __iomem *padcfg1; 665 unsigned long flags; 666 int ret = 0; 667 u32 value; 668 669 community = intel_get_community(pctrl, pin); 670 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 671 672 raw_spin_lock_irqsave(&pctrl->lock, flags); 673 674 value = readl(padcfg1); 675 676 switch (param) { 677 case PIN_CONFIG_BIAS_DISABLE: 678 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 679 break; 680 681 case PIN_CONFIG_BIAS_PULL_UP: 682 value &= ~PADCFG1_TERM_MASK; 683 684 value |= PADCFG1_TERM_UP; 685 686 /* Set default strength value in case none is given */ 687 if (arg == 1) 688 arg = 5000; 689 690 switch (arg) { 691 case 20000: 692 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 693 break; 694 case 5000: 695 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 696 break; 697 case 1000: 698 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 699 break; 700 case 833: 701 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 702 break; 703 default: 704 ret = -EINVAL; 705 } 706 707 break; 708 709 case PIN_CONFIG_BIAS_PULL_DOWN: 710 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 711 712 /* Set default strength value in case none is given */ 713 if (arg == 1) 714 arg = 5000; 715 716 switch (arg) { 717 case 20000: 718 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 719 break; 720 case 5000: 721 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 722 break; 723 case 1000: 724 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 725 ret = -EINVAL; 726 break; 727 } 728 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 729 break; 730 case 833: 731 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 732 ret = -EINVAL; 733 break; 734 } 735 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; 736 break; 737 default: 738 ret = -EINVAL; 739 } 740 741 break; 742 } 743 744 if (!ret) 745 writel(value, padcfg1); 746 747 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 748 749 return ret; 750 } 751 752 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 753 unsigned int pin, unsigned int debounce) 754 { 755 void __iomem *padcfg0, *padcfg2; 756 unsigned long flags; 757 u32 value0, value2; 758 759 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 760 if (!padcfg2) 761 return -ENOTSUPP; 762 763 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 764 765 raw_spin_lock_irqsave(&pctrl->lock, flags); 766 767 value0 = readl(padcfg0); 768 value2 = readl(padcfg2); 769 770 /* Disable glitch filter and debouncer */ 771 value0 &= ~PADCFG0_PREGFRXSEL; 772 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 773 774 if (debounce) { 775 unsigned long v; 776 777 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 778 if (v < 3 || v > 15) { 779 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 780 return -EINVAL; 781 } 782 783 /* Enable glitch filter and debouncer */ 784 value0 |= PADCFG0_PREGFRXSEL; 785 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 786 value2 |= PADCFG2_DEBEN; 787 } 788 789 writel(value0, padcfg0); 790 writel(value2, padcfg2); 791 792 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 793 794 return 0; 795 } 796 797 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 798 unsigned long *configs, unsigned int nconfigs) 799 { 800 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 801 int i, ret; 802 803 if (!intel_pad_usable(pctrl, pin)) 804 return -ENOTSUPP; 805 806 for (i = 0; i < nconfigs; i++) { 807 switch (pinconf_to_config_param(configs[i])) { 808 case PIN_CONFIG_BIAS_DISABLE: 809 case PIN_CONFIG_BIAS_PULL_UP: 810 case PIN_CONFIG_BIAS_PULL_DOWN: 811 ret = intel_config_set_pull(pctrl, pin, configs[i]); 812 if (ret) 813 return ret; 814 break; 815 816 case PIN_CONFIG_INPUT_DEBOUNCE: 817 ret = intel_config_set_debounce(pctrl, pin, 818 pinconf_to_config_argument(configs[i])); 819 if (ret) 820 return ret; 821 break; 822 823 default: 824 return -ENOTSUPP; 825 } 826 } 827 828 return 0; 829 } 830 831 static const struct pinconf_ops intel_pinconf_ops = { 832 .is_generic = true, 833 .pin_config_get = intel_config_get, 834 .pin_config_set = intel_config_set, 835 }; 836 837 static const struct pinctrl_desc intel_pinctrl_desc = { 838 .pctlops = &intel_pinctrl_ops, 839 .pmxops = &intel_pinmux_ops, 840 .confops = &intel_pinconf_ops, 841 .owner = THIS_MODULE, 842 }; 843 844 /** 845 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 846 * @pctrl: Pinctrl structure 847 * @offset: GPIO offset from gpiolib 848 * @community: Community is filled here if not %NULL 849 * @padgrp: Pad group is filled here if not %NULL 850 * 851 * When coming through gpiolib irqchip, the GPIO offset is not 852 * automatically translated to pinctrl pin number. This function can be 853 * used to find out the corresponding pinctrl pin. 854 */ 855 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 856 const struct intel_community **community, 857 const struct intel_padgroup **padgrp) 858 { 859 int i; 860 861 for (i = 0; i < pctrl->ncommunities; i++) { 862 const struct intel_community *comm = &pctrl->communities[i]; 863 int j; 864 865 for (j = 0; j < comm->ngpps; j++) { 866 const struct intel_padgroup *pgrp = &comm->gpps[j]; 867 868 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 869 continue; 870 871 if (offset >= pgrp->gpio_base && 872 offset < pgrp->gpio_base + pgrp->size) { 873 int pin; 874 875 pin = pgrp->base + offset - pgrp->gpio_base; 876 if (community) 877 *community = comm; 878 if (padgrp) 879 *padgrp = pgrp; 880 881 return pin; 882 } 883 } 884 } 885 886 return -EINVAL; 887 } 888 889 /** 890 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 891 * @pctrl: Pinctrl structure 892 * @pin: pin number 893 * 894 * Translate the pin number of pinctrl to GPIO offset 895 */ 896 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 897 { 898 const struct intel_community *community; 899 const struct intel_padgroup *padgrp; 900 901 community = intel_get_community(pctrl, pin); 902 if (!community) 903 return -EINVAL; 904 905 padgrp = intel_community_get_padgroup(community, pin); 906 if (!padgrp) 907 return -EINVAL; 908 909 return pin - padgrp->base + padgrp->gpio_base; 910 } 911 912 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 913 { 914 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 915 void __iomem *reg; 916 u32 padcfg0; 917 int pin; 918 919 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 920 if (pin < 0) 921 return -EINVAL; 922 923 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 924 if (!reg) 925 return -EINVAL; 926 927 padcfg0 = readl(reg); 928 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 929 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 930 931 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 932 } 933 934 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 935 int value) 936 { 937 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 938 unsigned long flags; 939 void __iomem *reg; 940 u32 padcfg0; 941 int pin; 942 943 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 944 if (pin < 0) 945 return; 946 947 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 948 if (!reg) 949 return; 950 951 raw_spin_lock_irqsave(&pctrl->lock, flags); 952 padcfg0 = readl(reg); 953 if (value) 954 padcfg0 |= PADCFG0_GPIOTXSTATE; 955 else 956 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 957 writel(padcfg0, reg); 958 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 959 } 960 961 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 962 { 963 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 964 unsigned long flags; 965 void __iomem *reg; 966 u32 padcfg0; 967 int pin; 968 969 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 970 if (pin < 0) 971 return -EINVAL; 972 973 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 974 if (!reg) 975 return -EINVAL; 976 977 raw_spin_lock_irqsave(&pctrl->lock, flags); 978 padcfg0 = readl(reg); 979 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 980 if (padcfg0 & PADCFG0_PMODE_MASK) 981 return -EINVAL; 982 983 if (padcfg0 & PADCFG0_GPIOTXDIS) 984 return GPIO_LINE_DIRECTION_IN; 985 986 return GPIO_LINE_DIRECTION_OUT; 987 } 988 989 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 990 { 991 return pinctrl_gpio_direction_input(chip->base + offset); 992 } 993 994 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 995 int value) 996 { 997 intel_gpio_set(chip, offset, value); 998 return pinctrl_gpio_direction_output(chip->base + offset); 999 } 1000 1001 static const struct gpio_chip intel_gpio_chip = { 1002 .owner = THIS_MODULE, 1003 .request = gpiochip_generic_request, 1004 .free = gpiochip_generic_free, 1005 .get_direction = intel_gpio_get_direction, 1006 .direction_input = intel_gpio_direction_input, 1007 .direction_output = intel_gpio_direction_output, 1008 .get = intel_gpio_get, 1009 .set = intel_gpio_set, 1010 .set_config = gpiochip_generic_config, 1011 }; 1012 1013 static void intel_gpio_irq_ack(struct irq_data *d) 1014 { 1015 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1016 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1017 const struct intel_community *community; 1018 const struct intel_padgroup *padgrp; 1019 int pin; 1020 1021 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1022 if (pin >= 0) { 1023 unsigned int gpp, gpp_offset, is_offset; 1024 1025 gpp = padgrp->reg_num; 1026 gpp_offset = padgroup_offset(padgrp, pin); 1027 is_offset = community->is_offset + gpp * 4; 1028 1029 raw_spin_lock(&pctrl->lock); 1030 writel(BIT(gpp_offset), community->regs + is_offset); 1031 raw_spin_unlock(&pctrl->lock); 1032 } 1033 } 1034 1035 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1036 { 1037 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1038 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1039 const struct intel_community *community; 1040 const struct intel_padgroup *padgrp; 1041 int pin; 1042 1043 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1044 if (pin >= 0) { 1045 unsigned int gpp, gpp_offset; 1046 unsigned long flags; 1047 void __iomem *reg, *is; 1048 u32 value; 1049 1050 gpp = padgrp->reg_num; 1051 gpp_offset = padgroup_offset(padgrp, pin); 1052 1053 reg = community->regs + community->ie_offset + gpp * 4; 1054 is = community->regs + community->is_offset + gpp * 4; 1055 1056 raw_spin_lock_irqsave(&pctrl->lock, flags); 1057 1058 /* Clear interrupt status first to avoid unexpected interrupt */ 1059 writel(BIT(gpp_offset), is); 1060 1061 value = readl(reg); 1062 if (mask) 1063 value &= ~BIT(gpp_offset); 1064 else 1065 value |= BIT(gpp_offset); 1066 writel(value, reg); 1067 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1068 } 1069 } 1070 1071 static void intel_gpio_irq_mask(struct irq_data *d) 1072 { 1073 intel_gpio_irq_mask_unmask(d, true); 1074 } 1075 1076 static void intel_gpio_irq_unmask(struct irq_data *d) 1077 { 1078 intel_gpio_irq_mask_unmask(d, false); 1079 } 1080 1081 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1082 { 1083 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1084 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1085 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1086 unsigned long flags; 1087 void __iomem *reg; 1088 u32 value; 1089 1090 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1091 if (!reg) 1092 return -EINVAL; 1093 1094 /* 1095 * If the pin is in ACPI mode it is still usable as a GPIO but it 1096 * cannot be used as IRQ because GPI_IS status bit will not be 1097 * updated by the host controller hardware. 1098 */ 1099 if (intel_pad_acpi_mode(pctrl, pin)) { 1100 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1101 return -EPERM; 1102 } 1103 1104 raw_spin_lock_irqsave(&pctrl->lock, flags); 1105 1106 intel_gpio_set_gpio_mode(reg); 1107 1108 /* Disable TX buffer and enable RX (this will be input) */ 1109 __intel_gpio_set_direction(reg, true); 1110 1111 value = readl(reg); 1112 1113 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1114 1115 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1116 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1117 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1118 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1119 value |= PADCFG0_RXINV; 1120 } else if (type & IRQ_TYPE_EDGE_RISING) { 1121 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1122 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1123 if (type & IRQ_TYPE_LEVEL_LOW) 1124 value |= PADCFG0_RXINV; 1125 } else { 1126 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1127 } 1128 1129 writel(value, reg); 1130 1131 if (type & IRQ_TYPE_EDGE_BOTH) 1132 irq_set_handler_locked(d, handle_edge_irq); 1133 else if (type & IRQ_TYPE_LEVEL_MASK) 1134 irq_set_handler_locked(d, handle_level_irq); 1135 1136 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1137 1138 return 0; 1139 } 1140 1141 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1142 { 1143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1144 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1145 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1146 1147 if (on) 1148 enable_irq_wake(pctrl->irq); 1149 else 1150 disable_irq_wake(pctrl->irq); 1151 1152 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1153 return 0; 1154 } 1155 1156 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1157 const struct intel_community *community) 1158 { 1159 struct gpio_chip *gc = &pctrl->chip; 1160 unsigned int gpp; 1161 int ret = 0; 1162 1163 for (gpp = 0; gpp < community->ngpps; gpp++) { 1164 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1165 unsigned long pending, enabled, gpp_offset; 1166 unsigned long flags; 1167 1168 raw_spin_lock_irqsave(&pctrl->lock, flags); 1169 1170 pending = readl(community->regs + community->is_offset + 1171 padgrp->reg_num * 4); 1172 enabled = readl(community->regs + community->ie_offset + 1173 padgrp->reg_num * 4); 1174 1175 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1176 1177 /* Only interrupts that are enabled */ 1178 pending &= enabled; 1179 1180 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1181 unsigned int irq; 1182 1183 irq = irq_find_mapping(gc->irq.domain, 1184 padgrp->gpio_base + gpp_offset); 1185 generic_handle_irq(irq); 1186 } 1187 1188 ret += pending ? 1 : 0; 1189 } 1190 1191 return ret; 1192 } 1193 1194 static irqreturn_t intel_gpio_irq(int irq, void *data) 1195 { 1196 const struct intel_community *community; 1197 struct intel_pinctrl *pctrl = data; 1198 unsigned int i; 1199 int ret = 0; 1200 1201 /* Need to check all communities for pending interrupts */ 1202 for (i = 0; i < pctrl->ncommunities; i++) { 1203 community = &pctrl->communities[i]; 1204 ret += intel_gpio_community_irq_handler(pctrl, community); 1205 } 1206 1207 return IRQ_RETVAL(ret); 1208 } 1209 1210 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1211 const struct intel_community *community) 1212 { 1213 int ret = 0, i; 1214 1215 for (i = 0; i < community->ngpps; i++) { 1216 const struct intel_padgroup *gpp = &community->gpps[i]; 1217 1218 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1219 continue; 1220 1221 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1222 gpp->gpio_base, gpp->base, 1223 gpp->size); 1224 if (ret) 1225 return ret; 1226 } 1227 1228 return ret; 1229 } 1230 1231 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1232 { 1233 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1234 int ret, i; 1235 1236 for (i = 0; i < pctrl->ncommunities; i++) { 1237 struct intel_community *community = &pctrl->communities[i]; 1238 1239 ret = intel_gpio_add_community_ranges(pctrl, community); 1240 if (ret) { 1241 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1242 return ret; 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1250 { 1251 const struct intel_community *community; 1252 unsigned int ngpio = 0; 1253 int i, j; 1254 1255 for (i = 0; i < pctrl->ncommunities; i++) { 1256 community = &pctrl->communities[i]; 1257 for (j = 0; j < community->ngpps; j++) { 1258 const struct intel_padgroup *gpp = &community->gpps[j]; 1259 1260 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1261 continue; 1262 1263 if (gpp->gpio_base + gpp->size > ngpio) 1264 ngpio = gpp->gpio_base + gpp->size; 1265 } 1266 } 1267 1268 return ngpio; 1269 } 1270 1271 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1272 { 1273 int ret; 1274 struct gpio_irq_chip *girq; 1275 1276 pctrl->chip = intel_gpio_chip; 1277 1278 /* Setup GPIO chip */ 1279 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1280 pctrl->chip.label = dev_name(pctrl->dev); 1281 pctrl->chip.parent = pctrl->dev; 1282 pctrl->chip.base = -1; 1283 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1284 pctrl->irq = irq; 1285 1286 /* Setup IRQ chip */ 1287 pctrl->irqchip.name = dev_name(pctrl->dev); 1288 pctrl->irqchip.irq_ack = intel_gpio_irq_ack; 1289 pctrl->irqchip.irq_mask = intel_gpio_irq_mask; 1290 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask; 1291 pctrl->irqchip.irq_set_type = intel_gpio_irq_type; 1292 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake; 1293 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; 1294 1295 /* 1296 * On some platforms several GPIO controllers share the same interrupt 1297 * line. 1298 */ 1299 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1300 IRQF_SHARED | IRQF_NO_THREAD, 1301 dev_name(pctrl->dev), pctrl); 1302 if (ret) { 1303 dev_err(pctrl->dev, "failed to request interrupt\n"); 1304 return ret; 1305 } 1306 1307 girq = &pctrl->chip.irq; 1308 girq->chip = &pctrl->irqchip; 1309 /* This will let us handle the IRQ in the driver */ 1310 girq->parent_handler = NULL; 1311 girq->num_parents = 0; 1312 girq->default_type = IRQ_TYPE_NONE; 1313 girq->handler = handle_bad_irq; 1314 1315 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1316 if (ret) { 1317 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1318 return ret; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1325 struct intel_community *community) 1326 { 1327 struct intel_padgroup *gpps; 1328 unsigned int npins = community->npins; 1329 unsigned int padown_num = 0; 1330 size_t ngpps, i; 1331 1332 if (community->gpps) 1333 ngpps = community->ngpps; 1334 else 1335 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1336 1337 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1338 if (!gpps) 1339 return -ENOMEM; 1340 1341 for (i = 0; i < ngpps; i++) { 1342 if (community->gpps) { 1343 gpps[i] = community->gpps[i]; 1344 } else { 1345 unsigned int gpp_size = community->gpp_size; 1346 1347 gpps[i].reg_num = i; 1348 gpps[i].base = community->pin_base + i * gpp_size; 1349 gpps[i].size = min(gpp_size, npins); 1350 npins -= gpps[i].size; 1351 } 1352 1353 if (gpps[i].size > 32) 1354 return -EINVAL; 1355 1356 /* Special treatment for GPIO base */ 1357 switch (gpps[i].gpio_base) { 1358 case INTEL_GPIO_BASE_MATCH: 1359 gpps[i].gpio_base = gpps[i].base; 1360 break; 1361 case INTEL_GPIO_BASE_ZERO: 1362 gpps[i].gpio_base = 0; 1363 break; 1364 case INTEL_GPIO_BASE_NOMAP: 1365 default: 1366 break; 1367 } 1368 1369 gpps[i].padown_num = padown_num; 1370 1371 /* 1372 * In older hardware the number of padown registers per 1373 * group is fixed regardless of the group size. 1374 */ 1375 if (community->gpp_num_padown_regs) 1376 padown_num += community->gpp_num_padown_regs; 1377 else 1378 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1379 } 1380 1381 community->ngpps = ngpps; 1382 community->gpps = gpps; 1383 1384 return 0; 1385 } 1386 1387 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1388 { 1389 #ifdef CONFIG_PM_SLEEP 1390 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1391 struct intel_community_context *communities; 1392 struct intel_pad_context *pads; 1393 int i; 1394 1395 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1396 if (!pads) 1397 return -ENOMEM; 1398 1399 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1400 sizeof(*communities), GFP_KERNEL); 1401 if (!communities) 1402 return -ENOMEM; 1403 1404 1405 for (i = 0; i < pctrl->ncommunities; i++) { 1406 struct intel_community *community = &pctrl->communities[i]; 1407 u32 *intmask, *hostown; 1408 1409 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1410 sizeof(*intmask), GFP_KERNEL); 1411 if (!intmask) 1412 return -ENOMEM; 1413 1414 communities[i].intmask = intmask; 1415 1416 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1417 sizeof(*hostown), GFP_KERNEL); 1418 if (!hostown) 1419 return -ENOMEM; 1420 1421 communities[i].hostown = hostown; 1422 } 1423 1424 pctrl->context.pads = pads; 1425 pctrl->context.communities = communities; 1426 #endif 1427 1428 return 0; 1429 } 1430 1431 static int intel_pinctrl_probe(struct platform_device *pdev, 1432 const struct intel_pinctrl_soc_data *soc_data) 1433 { 1434 struct intel_pinctrl *pctrl; 1435 int i, ret, irq; 1436 1437 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1438 if (!pctrl) 1439 return -ENOMEM; 1440 1441 pctrl->dev = &pdev->dev; 1442 pctrl->soc = soc_data; 1443 raw_spin_lock_init(&pctrl->lock); 1444 1445 /* 1446 * Make a copy of the communities which we can use to hold pointers 1447 * to the registers. 1448 */ 1449 pctrl->ncommunities = pctrl->soc->ncommunities; 1450 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1451 sizeof(*pctrl->communities), GFP_KERNEL); 1452 if (!pctrl->communities) 1453 return -ENOMEM; 1454 1455 for (i = 0; i < pctrl->ncommunities; i++) { 1456 struct intel_community *community = &pctrl->communities[i]; 1457 void __iomem *regs; 1458 u32 padbar; 1459 1460 *community = pctrl->soc->communities[i]; 1461 1462 regs = devm_platform_ioremap_resource(pdev, community->barno); 1463 if (IS_ERR(regs)) 1464 return PTR_ERR(regs); 1465 1466 /* 1467 * Determine community features based on the revision if 1468 * not specified already. 1469 */ 1470 if (!community->features) { 1471 u32 rev; 1472 1473 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1474 if (rev >= 0x94) { 1475 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1476 community->features |= PINCTRL_FEATURE_1K_PD; 1477 } 1478 } 1479 1480 /* Read offset of the pad configuration registers */ 1481 padbar = readl(regs + PADBAR); 1482 1483 community->regs = regs; 1484 community->pad_regs = regs + padbar; 1485 1486 ret = intel_pinctrl_add_padgroups(pctrl, community); 1487 if (ret) 1488 return ret; 1489 } 1490 1491 irq = platform_get_irq(pdev, 0); 1492 if (irq < 0) 1493 return irq; 1494 1495 ret = intel_pinctrl_pm_init(pctrl); 1496 if (ret) 1497 return ret; 1498 1499 pctrl->pctldesc = intel_pinctrl_desc; 1500 pctrl->pctldesc.name = dev_name(&pdev->dev); 1501 pctrl->pctldesc.pins = pctrl->soc->pins; 1502 pctrl->pctldesc.npins = pctrl->soc->npins; 1503 1504 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1505 pctrl); 1506 if (IS_ERR(pctrl->pctldev)) { 1507 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1508 return PTR_ERR(pctrl->pctldev); 1509 } 1510 1511 ret = intel_gpio_probe(pctrl, irq); 1512 if (ret) 1513 return ret; 1514 1515 platform_set_drvdata(pdev, pctrl); 1516 1517 return 0; 1518 } 1519 1520 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1521 { 1522 const struct intel_pinctrl_soc_data *data; 1523 1524 data = device_get_match_data(&pdev->dev); 1525 if (!data) 1526 return -ENODATA; 1527 1528 return intel_pinctrl_probe(pdev, data); 1529 } 1530 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1531 1532 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1533 { 1534 const struct intel_pinctrl_soc_data *data; 1535 1536 data = intel_pinctrl_get_soc_data(pdev); 1537 if (IS_ERR(data)) 1538 return PTR_ERR(data); 1539 1540 return intel_pinctrl_probe(pdev, data); 1541 } 1542 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1543 1544 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) 1545 { 1546 const struct intel_pinctrl_soc_data *data = NULL; 1547 const struct intel_pinctrl_soc_data **table; 1548 struct acpi_device *adev; 1549 unsigned int i; 1550 1551 adev = ACPI_COMPANION(&pdev->dev); 1552 if (adev) { 1553 const void *match = device_get_match_data(&pdev->dev); 1554 1555 table = (const struct intel_pinctrl_soc_data **)match; 1556 for (i = 0; table[i]; i++) { 1557 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1558 data = table[i]; 1559 break; 1560 } 1561 } 1562 } else { 1563 const struct platform_device_id *id; 1564 1565 id = platform_get_device_id(pdev); 1566 if (!id) 1567 return ERR_PTR(-ENODEV); 1568 1569 table = (const struct intel_pinctrl_soc_data **)id->driver_data; 1570 data = table[pdev->id]; 1571 } 1572 1573 return data ?: ERR_PTR(-ENODATA); 1574 } 1575 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); 1576 1577 #ifdef CONFIG_PM_SLEEP 1578 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1579 { 1580 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1581 1582 if (!pd || !intel_pad_usable(pctrl, pin)) 1583 return false; 1584 1585 /* 1586 * Only restore the pin if it is actually in use by the kernel (or 1587 * by userspace). It is possible that some pins are used by the 1588 * BIOS during resume and those are not always locked down so leave 1589 * them alone. 1590 */ 1591 if (pd->mux_owner || pd->gpio_owner || 1592 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1593 return true; 1594 1595 return false; 1596 } 1597 1598 int intel_pinctrl_suspend_noirq(struct device *dev) 1599 { 1600 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1601 struct intel_community_context *communities; 1602 struct intel_pad_context *pads; 1603 int i; 1604 1605 pads = pctrl->context.pads; 1606 for (i = 0; i < pctrl->soc->npins; i++) { 1607 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1608 void __iomem *padcfg; 1609 u32 val; 1610 1611 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1612 continue; 1613 1614 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1615 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1616 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1617 pads[i].padcfg1 = val; 1618 1619 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1620 if (padcfg) 1621 pads[i].padcfg2 = readl(padcfg); 1622 } 1623 1624 communities = pctrl->context.communities; 1625 for (i = 0; i < pctrl->ncommunities; i++) { 1626 struct intel_community *community = &pctrl->communities[i]; 1627 void __iomem *base; 1628 unsigned int gpp; 1629 1630 base = community->regs + community->ie_offset; 1631 for (gpp = 0; gpp < community->ngpps; gpp++) 1632 communities[i].intmask[gpp] = readl(base + gpp * 4); 1633 1634 base = community->regs + community->hostown_offset; 1635 for (gpp = 0; gpp < community->ngpps; gpp++) 1636 communities[i].hostown[gpp] = readl(base + gpp * 4); 1637 } 1638 1639 return 0; 1640 } 1641 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1642 1643 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1644 { 1645 size_t i; 1646 1647 for (i = 0; i < pctrl->ncommunities; i++) { 1648 const struct intel_community *community; 1649 void __iomem *base; 1650 unsigned int gpp; 1651 1652 community = &pctrl->communities[i]; 1653 base = community->regs; 1654 1655 for (gpp = 0; gpp < community->ngpps; gpp++) { 1656 /* Mask and clear all interrupts */ 1657 writel(0, base + community->ie_offset + gpp * 4); 1658 writel(0xffff, base + community->is_offset + gpp * 4); 1659 } 1660 } 1661 } 1662 1663 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1664 { 1665 u32 curr, updated; 1666 1667 curr = readl(reg); 1668 1669 updated = (curr & ~mask) | (value & mask); 1670 if (curr == updated) 1671 return false; 1672 1673 writel(updated, reg); 1674 return true; 1675 } 1676 1677 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1678 void __iomem *base, unsigned int gpp, u32 saved) 1679 { 1680 const struct intel_community *community = &pctrl->communities[c]; 1681 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1682 struct device *dev = pctrl->dev; 1683 const char *dummy; 1684 u32 requested = 0; 1685 unsigned int i; 1686 1687 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1688 return; 1689 1690 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1691 requested |= BIT(i); 1692 1693 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1694 return; 1695 1696 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1697 } 1698 1699 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1700 void __iomem *base, unsigned int gpp, u32 saved) 1701 { 1702 struct device *dev = pctrl->dev; 1703 1704 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1705 return; 1706 1707 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1708 } 1709 1710 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1711 unsigned int reg, u32 saved) 1712 { 1713 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1714 unsigned int n = reg / sizeof(u32); 1715 struct device *dev = pctrl->dev; 1716 void __iomem *padcfg; 1717 1718 padcfg = intel_get_padcfg(pctrl, pin, reg); 1719 if (!padcfg) 1720 return; 1721 1722 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1723 return; 1724 1725 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1726 } 1727 1728 int intel_pinctrl_resume_noirq(struct device *dev) 1729 { 1730 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1731 const struct intel_community_context *communities; 1732 const struct intel_pad_context *pads; 1733 int i; 1734 1735 /* Mask all interrupts */ 1736 intel_gpio_irq_init(pctrl); 1737 1738 pads = pctrl->context.pads; 1739 for (i = 0; i < pctrl->soc->npins; i++) { 1740 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1741 1742 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1743 continue; 1744 1745 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1746 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1747 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1748 } 1749 1750 communities = pctrl->context.communities; 1751 for (i = 0; i < pctrl->ncommunities; i++) { 1752 struct intel_community *community = &pctrl->communities[i]; 1753 void __iomem *base; 1754 unsigned int gpp; 1755 1756 base = community->regs + community->ie_offset; 1757 for (gpp = 0; gpp < community->ngpps; gpp++) 1758 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1759 1760 base = community->regs + community->hostown_offset; 1761 for (gpp = 0; gpp < community->ngpps; gpp++) 1762 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1763 } 1764 1765 return 0; 1766 } 1767 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1768 #endif 1769 1770 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1771 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1772 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1773 MODULE_LICENSE("GPL v2"); 1774