1 /* 2 * Intel pinctrl/GPIO core driver. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/acpi.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 26 #include "pinctrl-intel.h" 27 28 /* Offset from regs */ 29 #define PADBAR 0x00c 30 #define GPI_IS 0x100 31 #define GPI_GPE_STS 0x140 32 #define GPI_GPE_EN 0x160 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_RXINV BIT(23) 48 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 49 #define PADCFG0_GPIROUTSCI BIT(19) 50 #define PADCFG0_GPIROUTSMI BIT(18) 51 #define PADCFG0_GPIROUTNMI BIT(17) 52 #define PADCFG0_PMODE_SHIFT 10 53 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 54 #define PADCFG0_GPIORXDIS BIT(9) 55 #define PADCFG0_GPIOTXDIS BIT(8) 56 #define PADCFG0_GPIORXSTATE BIT(1) 57 #define PADCFG0_GPIOTXSTATE BIT(0) 58 59 #define PADCFG1 0x004 60 #define PADCFG1_TERM_UP BIT(13) 61 #define PADCFG1_TERM_SHIFT 10 62 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 63 #define PADCFG1_TERM_20K 4 64 #define PADCFG1_TERM_2K 3 65 #define PADCFG1_TERM_5K 2 66 #define PADCFG1_TERM_1K 1 67 68 struct intel_pad_context { 69 u32 padcfg0; 70 u32 padcfg1; 71 }; 72 73 struct intel_community_context { 74 u32 *intmask; 75 }; 76 77 struct intel_pinctrl_context { 78 struct intel_pad_context *pads; 79 struct intel_community_context *communities; 80 }; 81 82 /** 83 * struct intel_pinctrl - Intel pinctrl private structure 84 * @dev: Pointer to the device structure 85 * @lock: Lock to serialize register access 86 * @pctldesc: Pin controller description 87 * @pctldev: Pointer to the pin controller device 88 * @chip: GPIO chip in this pin controller 89 * @soc: SoC/PCH specific pin configuration data 90 * @communities: All communities in this pin controller 91 * @ncommunities: Number of communities in this pin controller 92 * @context: Configuration saved over system sleep 93 */ 94 struct intel_pinctrl { 95 struct device *dev; 96 spinlock_t lock; 97 struct pinctrl_desc pctldesc; 98 struct pinctrl_dev *pctldev; 99 struct gpio_chip chip; 100 const struct intel_pinctrl_soc_data *soc; 101 struct intel_community *communities; 102 size_t ncommunities; 103 struct intel_pinctrl_context context; 104 }; 105 106 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 107 108 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 109 unsigned pin) 110 { 111 struct intel_community *community; 112 int i; 113 114 for (i = 0; i < pctrl->ncommunities; i++) { 115 community = &pctrl->communities[i]; 116 if (pin >= community->pin_base && 117 pin < community->pin_base + community->npins) 118 return community; 119 } 120 121 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 122 return NULL; 123 } 124 125 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 126 unsigned reg) 127 { 128 const struct intel_community *community; 129 unsigned padno; 130 131 community = intel_get_community(pctrl, pin); 132 if (!community) 133 return NULL; 134 135 padno = pin_to_padno(community, pin); 136 return community->pad_regs + reg + padno * 8; 137 } 138 139 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 140 { 141 const struct intel_community *community; 142 unsigned padno, gpp, offset, group; 143 void __iomem *padown; 144 145 community = intel_get_community(pctrl, pin); 146 if (!community) 147 return false; 148 if (!community->padown_offset) 149 return true; 150 151 padno = pin_to_padno(community, pin); 152 group = padno / community->gpp_size; 153 gpp = PADOWN_GPP(padno % community->gpp_size); 154 offset = community->padown_offset + 0x10 * group + gpp * 4; 155 padown = community->regs + offset; 156 157 return !(readl(padown) & PADOWN_MASK(padno)); 158 } 159 160 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 161 { 162 const struct intel_community *community; 163 unsigned padno, gpp, offset; 164 void __iomem *hostown; 165 166 community = intel_get_community(pctrl, pin); 167 if (!community) 168 return true; 169 if (!community->hostown_offset) 170 return false; 171 172 padno = pin_to_padno(community, pin); 173 gpp = padno / community->gpp_size; 174 offset = community->hostown_offset + gpp * 4; 175 hostown = community->regs + offset; 176 177 return !(readl(hostown) & BIT(padno % community->gpp_size)); 178 } 179 180 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 181 { 182 struct intel_community *community; 183 unsigned padno, gpp, offset; 184 u32 value; 185 186 community = intel_get_community(pctrl, pin); 187 if (!community) 188 return true; 189 if (!community->padcfglock_offset) 190 return false; 191 192 padno = pin_to_padno(community, pin); 193 gpp = padno / community->gpp_size; 194 195 /* 196 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 197 * the pad is considered unlocked. Any other case means that it is 198 * either fully or partially locked and we don't touch it. 199 */ 200 offset = community->padcfglock_offset + gpp * 8; 201 value = readl(community->regs + offset); 202 if (value & BIT(pin % community->gpp_size)) 203 return true; 204 205 offset = community->padcfglock_offset + 4 + gpp * 8; 206 value = readl(community->regs + offset); 207 if (value & BIT(pin % community->gpp_size)) 208 return true; 209 210 return false; 211 } 212 213 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 214 { 215 return intel_pad_owned_by_host(pctrl, pin) && 216 !intel_pad_locked(pctrl, pin); 217 } 218 219 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 220 { 221 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 222 223 return pctrl->soc->ngroups; 224 } 225 226 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 227 unsigned group) 228 { 229 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 230 231 return pctrl->soc->groups[group].name; 232 } 233 234 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 235 const unsigned **pins, unsigned *npins) 236 { 237 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 238 239 *pins = pctrl->soc->groups[group].pins; 240 *npins = pctrl->soc->groups[group].npins; 241 return 0; 242 } 243 244 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 245 unsigned pin) 246 { 247 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 248 u32 cfg0, cfg1, mode; 249 bool locked, acpi; 250 251 if (!intel_pad_owned_by_host(pctrl, pin)) { 252 seq_puts(s, "not available"); 253 return; 254 } 255 256 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 257 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 258 259 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 260 if (!mode) 261 seq_puts(s, "GPIO "); 262 else 263 seq_printf(s, "mode %d ", mode); 264 265 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 266 267 locked = intel_pad_locked(pctrl, pin); 268 acpi = intel_pad_acpi_mode(pctrl, pin); 269 270 if (locked || acpi) { 271 seq_puts(s, " ["); 272 if (locked) { 273 seq_puts(s, "LOCKED"); 274 if (acpi) 275 seq_puts(s, ", "); 276 } 277 if (acpi) 278 seq_puts(s, "ACPI"); 279 seq_puts(s, "]"); 280 } 281 } 282 283 static const struct pinctrl_ops intel_pinctrl_ops = { 284 .get_groups_count = intel_get_groups_count, 285 .get_group_name = intel_get_group_name, 286 .get_group_pins = intel_get_group_pins, 287 .pin_dbg_show = intel_pin_dbg_show, 288 }; 289 290 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 291 { 292 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 293 294 return pctrl->soc->nfunctions; 295 } 296 297 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 298 unsigned function) 299 { 300 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 301 302 return pctrl->soc->functions[function].name; 303 } 304 305 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 306 unsigned function, 307 const char * const **groups, 308 unsigned * const ngroups) 309 { 310 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 311 312 *groups = pctrl->soc->functions[function].groups; 313 *ngroups = pctrl->soc->functions[function].ngroups; 314 return 0; 315 } 316 317 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 318 unsigned group) 319 { 320 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 321 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 322 unsigned long flags; 323 int i; 324 325 spin_lock_irqsave(&pctrl->lock, flags); 326 327 /* 328 * All pins in the groups needs to be accessible and writable 329 * before we can enable the mux for this group. 330 */ 331 for (i = 0; i < grp->npins; i++) { 332 if (!intel_pad_usable(pctrl, grp->pins[i])) { 333 spin_unlock_irqrestore(&pctrl->lock, flags); 334 return -EBUSY; 335 } 336 } 337 338 /* Now enable the mux setting for each pin in the group */ 339 for (i = 0; i < grp->npins; i++) { 340 void __iomem *padcfg0; 341 u32 value; 342 343 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 344 value = readl(padcfg0); 345 346 value &= ~PADCFG0_PMODE_MASK; 347 value |= grp->mode << PADCFG0_PMODE_SHIFT; 348 349 writel(value, padcfg0); 350 } 351 352 spin_unlock_irqrestore(&pctrl->lock, flags); 353 354 return 0; 355 } 356 357 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 358 struct pinctrl_gpio_range *range, 359 unsigned pin) 360 { 361 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 362 void __iomem *padcfg0; 363 unsigned long flags; 364 u32 value; 365 366 spin_lock_irqsave(&pctrl->lock, flags); 367 368 if (!intel_pad_usable(pctrl, pin)) { 369 spin_unlock_irqrestore(&pctrl->lock, flags); 370 return -EBUSY; 371 } 372 373 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 374 /* Put the pad into GPIO mode */ 375 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 376 /* Disable SCI/SMI/NMI generation */ 377 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 378 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 379 /* Disable TX buffer and enable RX (this will be input) */ 380 value &= ~PADCFG0_GPIORXDIS; 381 value |= PADCFG0_GPIOTXDIS; 382 writel(value, padcfg0); 383 384 spin_unlock_irqrestore(&pctrl->lock, flags); 385 386 return 0; 387 } 388 389 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 390 struct pinctrl_gpio_range *range, 391 unsigned pin, bool input) 392 { 393 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 394 void __iomem *padcfg0; 395 unsigned long flags; 396 u32 value; 397 398 spin_lock_irqsave(&pctrl->lock, flags); 399 400 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 401 402 value = readl(padcfg0); 403 if (input) 404 value |= PADCFG0_GPIOTXDIS; 405 else 406 value &= ~PADCFG0_GPIOTXDIS; 407 writel(value, padcfg0); 408 409 spin_unlock_irqrestore(&pctrl->lock, flags); 410 411 return 0; 412 } 413 414 static const struct pinmux_ops intel_pinmux_ops = { 415 .get_functions_count = intel_get_functions_count, 416 .get_function_name = intel_get_function_name, 417 .get_function_groups = intel_get_function_groups, 418 .set_mux = intel_pinmux_set_mux, 419 .gpio_request_enable = intel_gpio_request_enable, 420 .gpio_set_direction = intel_gpio_set_direction, 421 }; 422 423 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 424 unsigned long *config) 425 { 426 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 427 enum pin_config_param param = pinconf_to_config_param(*config); 428 u32 value, term; 429 u16 arg = 0; 430 431 if (!intel_pad_owned_by_host(pctrl, pin)) 432 return -ENOTSUPP; 433 434 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 435 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 436 437 switch (param) { 438 case PIN_CONFIG_BIAS_DISABLE: 439 if (term) 440 return -EINVAL; 441 break; 442 443 case PIN_CONFIG_BIAS_PULL_UP: 444 if (!term || !(value & PADCFG1_TERM_UP)) 445 return -EINVAL; 446 447 switch (term) { 448 case PADCFG1_TERM_1K: 449 arg = 1000; 450 break; 451 case PADCFG1_TERM_2K: 452 arg = 2000; 453 break; 454 case PADCFG1_TERM_5K: 455 arg = 5000; 456 break; 457 case PADCFG1_TERM_20K: 458 arg = 20000; 459 break; 460 } 461 462 break; 463 464 case PIN_CONFIG_BIAS_PULL_DOWN: 465 if (!term || value & PADCFG1_TERM_UP) 466 return -EINVAL; 467 468 switch (term) { 469 case PADCFG1_TERM_5K: 470 arg = 5000; 471 break; 472 case PADCFG1_TERM_20K: 473 arg = 20000; 474 break; 475 } 476 477 break; 478 479 default: 480 return -ENOTSUPP; 481 } 482 483 *config = pinconf_to_config_packed(param, arg); 484 return 0; 485 } 486 487 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 488 unsigned long config) 489 { 490 unsigned param = pinconf_to_config_param(config); 491 unsigned arg = pinconf_to_config_argument(config); 492 void __iomem *padcfg1; 493 unsigned long flags; 494 int ret = 0; 495 u32 value; 496 497 spin_lock_irqsave(&pctrl->lock, flags); 498 499 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 500 value = readl(padcfg1); 501 502 switch (param) { 503 case PIN_CONFIG_BIAS_DISABLE: 504 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 505 break; 506 507 case PIN_CONFIG_BIAS_PULL_UP: 508 value &= ~PADCFG1_TERM_MASK; 509 510 value |= PADCFG1_TERM_UP; 511 512 switch (arg) { 513 case 20000: 514 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 515 break; 516 case 5000: 517 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 518 break; 519 case 2000: 520 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 521 break; 522 case 1000: 523 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 524 break; 525 default: 526 ret = -EINVAL; 527 } 528 529 break; 530 531 case PIN_CONFIG_BIAS_PULL_DOWN: 532 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 533 534 switch (arg) { 535 case 20000: 536 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 537 break; 538 case 5000: 539 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 540 break; 541 default: 542 ret = -EINVAL; 543 } 544 545 break; 546 } 547 548 if (!ret) 549 writel(value, padcfg1); 550 551 spin_unlock_irqrestore(&pctrl->lock, flags); 552 553 return ret; 554 } 555 556 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 557 unsigned long *configs, unsigned nconfigs) 558 { 559 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 560 int i, ret; 561 562 if (!intel_pad_usable(pctrl, pin)) 563 return -ENOTSUPP; 564 565 for (i = 0; i < nconfigs; i++) { 566 switch (pinconf_to_config_param(configs[i])) { 567 case PIN_CONFIG_BIAS_DISABLE: 568 case PIN_CONFIG_BIAS_PULL_UP: 569 case PIN_CONFIG_BIAS_PULL_DOWN: 570 ret = intel_config_set_pull(pctrl, pin, configs[i]); 571 if (ret) 572 return ret; 573 break; 574 575 default: 576 return -ENOTSUPP; 577 } 578 } 579 580 return 0; 581 } 582 583 static const struct pinconf_ops intel_pinconf_ops = { 584 .is_generic = true, 585 .pin_config_get = intel_config_get, 586 .pin_config_set = intel_config_set, 587 }; 588 589 static const struct pinctrl_desc intel_pinctrl_desc = { 590 .pctlops = &intel_pinctrl_ops, 591 .pmxops = &intel_pinmux_ops, 592 .confops = &intel_pinconf_ops, 593 .owner = THIS_MODULE, 594 }; 595 596 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 597 { 598 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 599 void __iomem *reg; 600 601 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 602 if (!reg) 603 return -EINVAL; 604 605 return !!(readl(reg) & PADCFG0_GPIORXSTATE); 606 } 607 608 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 609 { 610 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 611 void __iomem *reg; 612 613 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 614 if (reg) { 615 unsigned long flags; 616 u32 padcfg0; 617 618 spin_lock_irqsave(&pctrl->lock, flags); 619 padcfg0 = readl(reg); 620 if (value) 621 padcfg0 |= PADCFG0_GPIOTXSTATE; 622 else 623 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 624 writel(padcfg0, reg); 625 spin_unlock_irqrestore(&pctrl->lock, flags); 626 } 627 } 628 629 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 630 { 631 return pinctrl_gpio_direction_input(chip->base + offset); 632 } 633 634 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 635 int value) 636 { 637 intel_gpio_set(chip, offset, value); 638 return pinctrl_gpio_direction_output(chip->base + offset); 639 } 640 641 static const struct gpio_chip intel_gpio_chip = { 642 .owner = THIS_MODULE, 643 .request = gpiochip_generic_request, 644 .free = gpiochip_generic_free, 645 .direction_input = intel_gpio_direction_input, 646 .direction_output = intel_gpio_direction_output, 647 .get = intel_gpio_get, 648 .set = intel_gpio_set, 649 }; 650 651 static void intel_gpio_irq_ack(struct irq_data *d) 652 { 653 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 654 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 655 const struct intel_community *community; 656 unsigned pin = irqd_to_hwirq(d); 657 658 spin_lock(&pctrl->lock); 659 660 community = intel_get_community(pctrl, pin); 661 if (community) { 662 unsigned padno = pin_to_padno(community, pin); 663 unsigned gpp_offset = padno % community->gpp_size; 664 unsigned gpp = padno / community->gpp_size; 665 666 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 667 } 668 669 spin_unlock(&pctrl->lock); 670 } 671 672 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 673 { 674 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 675 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 676 const struct intel_community *community; 677 unsigned pin = irqd_to_hwirq(d); 678 unsigned long flags; 679 680 spin_lock_irqsave(&pctrl->lock, flags); 681 682 community = intel_get_community(pctrl, pin); 683 if (community) { 684 unsigned padno = pin_to_padno(community, pin); 685 unsigned gpp_offset = padno % community->gpp_size; 686 unsigned gpp = padno / community->gpp_size; 687 void __iomem *reg; 688 u32 value; 689 690 reg = community->regs + community->ie_offset + gpp * 4; 691 value = readl(reg); 692 if (mask) 693 value &= ~BIT(gpp_offset); 694 else 695 value |= BIT(gpp_offset); 696 writel(value, reg); 697 } 698 699 spin_unlock_irqrestore(&pctrl->lock, flags); 700 } 701 702 static void intel_gpio_irq_mask(struct irq_data *d) 703 { 704 intel_gpio_irq_mask_unmask(d, true); 705 } 706 707 static void intel_gpio_irq_unmask(struct irq_data *d) 708 { 709 intel_gpio_irq_mask_unmask(d, false); 710 } 711 712 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 713 { 714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 715 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 716 unsigned pin = irqd_to_hwirq(d); 717 unsigned long flags; 718 void __iomem *reg; 719 u32 value; 720 721 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 722 if (!reg) 723 return -EINVAL; 724 725 /* 726 * If the pin is in ACPI mode it is still usable as a GPIO but it 727 * cannot be used as IRQ because GPI_IS status bit will not be 728 * updated by the host controller hardware. 729 */ 730 if (intel_pad_acpi_mode(pctrl, pin)) { 731 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 732 return -EPERM; 733 } 734 735 spin_lock_irqsave(&pctrl->lock, flags); 736 737 value = readl(reg); 738 739 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 740 741 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 742 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 743 } else if (type & IRQ_TYPE_EDGE_FALLING) { 744 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 745 value |= PADCFG0_RXINV; 746 } else if (type & IRQ_TYPE_EDGE_RISING) { 747 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 748 } else if (type & IRQ_TYPE_LEVEL_LOW) { 749 value |= PADCFG0_RXINV; 750 } else { 751 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 752 } 753 754 writel(value, reg); 755 756 if (type & IRQ_TYPE_EDGE_BOTH) 757 irq_set_handler_locked(d, handle_edge_irq); 758 else if (type & IRQ_TYPE_LEVEL_MASK) 759 irq_set_handler_locked(d, handle_level_irq); 760 761 spin_unlock_irqrestore(&pctrl->lock, flags); 762 763 return 0; 764 } 765 766 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 767 { 768 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 769 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 770 const struct intel_community *community; 771 unsigned pin = irqd_to_hwirq(d); 772 unsigned padno, gpp, gpp_offset; 773 u32 gpe_en; 774 775 community = intel_get_community(pctrl, pin); 776 if (!community) 777 return -EINVAL; 778 779 padno = pin_to_padno(community, pin); 780 gpp = padno / community->gpp_size; 781 gpp_offset = padno % community->gpp_size; 782 783 /* Clear the existing wake status */ 784 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); 785 786 /* 787 * The controller will generate wake when GPE of the corresponding 788 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not 789 * set). 790 */ 791 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); 792 if (on) 793 gpe_en |= BIT(gpp_offset); 794 else 795 gpe_en &= ~BIT(gpp_offset); 796 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); 797 798 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 799 return 0; 800 } 801 802 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 803 const struct intel_community *community) 804 { 805 struct gpio_chip *gc = &pctrl->chip; 806 irqreturn_t ret = IRQ_NONE; 807 int gpp; 808 809 for (gpp = 0; gpp < community->ngpps; gpp++) { 810 unsigned long pending, enabled, gpp_offset; 811 812 pending = readl(community->regs + GPI_IS + gpp * 4); 813 enabled = readl(community->regs + community->ie_offset + 814 gpp * 4); 815 816 /* Only interrupts that are enabled */ 817 pending &= enabled; 818 819 for_each_set_bit(gpp_offset, &pending, community->gpp_size) { 820 unsigned padno, irq; 821 822 /* 823 * The last group in community can have less pins 824 * than NPADS_IN_GPP. 825 */ 826 padno = gpp_offset + gpp * community->gpp_size; 827 if (padno >= community->npins) 828 break; 829 830 irq = irq_find_mapping(gc->irqdomain, 831 community->pin_base + padno); 832 generic_handle_irq(irq); 833 834 ret |= IRQ_HANDLED; 835 } 836 } 837 838 return ret; 839 } 840 841 static irqreturn_t intel_gpio_irq(int irq, void *data) 842 { 843 const struct intel_community *community; 844 struct intel_pinctrl *pctrl = data; 845 irqreturn_t ret = IRQ_NONE; 846 int i; 847 848 /* Need to check all communities for pending interrupts */ 849 for (i = 0; i < pctrl->ncommunities; i++) { 850 community = &pctrl->communities[i]; 851 ret |= intel_gpio_community_irq_handler(pctrl, community); 852 } 853 854 return ret; 855 } 856 857 static struct irq_chip intel_gpio_irqchip = { 858 .name = "intel-gpio", 859 .irq_ack = intel_gpio_irq_ack, 860 .irq_mask = intel_gpio_irq_mask, 861 .irq_unmask = intel_gpio_irq_unmask, 862 .irq_set_type = intel_gpio_irq_type, 863 .irq_set_wake = intel_gpio_irq_wake, 864 }; 865 866 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 867 { 868 int ret; 869 870 pctrl->chip = intel_gpio_chip; 871 872 pctrl->chip.ngpio = pctrl->soc->npins; 873 pctrl->chip.label = dev_name(pctrl->dev); 874 pctrl->chip.parent = pctrl->dev; 875 pctrl->chip.base = -1; 876 877 ret = gpiochip_add_data(&pctrl->chip, pctrl); 878 if (ret) { 879 dev_err(pctrl->dev, "failed to register gpiochip\n"); 880 return ret; 881 } 882 883 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 884 0, 0, pctrl->soc->npins); 885 if (ret) { 886 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 887 goto fail; 888 } 889 890 /* 891 * We need to request the interrupt here (instead of providing chip 892 * to the irq directly) because on some platforms several GPIO 893 * controllers share the same interrupt line. 894 */ 895 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED, 896 dev_name(pctrl->dev), pctrl); 897 if (ret) { 898 dev_err(pctrl->dev, "failed to request interrupt\n"); 899 goto fail; 900 } 901 902 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 903 handle_simple_irq, IRQ_TYPE_NONE); 904 if (ret) { 905 dev_err(pctrl->dev, "failed to add irqchip\n"); 906 goto fail; 907 } 908 909 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 910 NULL); 911 return 0; 912 913 fail: 914 gpiochip_remove(&pctrl->chip); 915 916 return ret; 917 } 918 919 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 920 { 921 #ifdef CONFIG_PM_SLEEP 922 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 923 struct intel_community_context *communities; 924 struct intel_pad_context *pads; 925 int i; 926 927 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 928 if (!pads) 929 return -ENOMEM; 930 931 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 932 sizeof(*communities), GFP_KERNEL); 933 if (!communities) 934 return -ENOMEM; 935 936 937 for (i = 0; i < pctrl->ncommunities; i++) { 938 struct intel_community *community = &pctrl->communities[i]; 939 u32 *intmask; 940 941 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 942 sizeof(*intmask), GFP_KERNEL); 943 if (!intmask) 944 return -ENOMEM; 945 946 communities[i].intmask = intmask; 947 } 948 949 pctrl->context.pads = pads; 950 pctrl->context.communities = communities; 951 #endif 952 953 return 0; 954 } 955 956 int intel_pinctrl_probe(struct platform_device *pdev, 957 const struct intel_pinctrl_soc_data *soc_data) 958 { 959 struct intel_pinctrl *pctrl; 960 int i, ret, irq; 961 962 if (!soc_data) 963 return -EINVAL; 964 965 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 966 if (!pctrl) 967 return -ENOMEM; 968 969 pctrl->dev = &pdev->dev; 970 pctrl->soc = soc_data; 971 spin_lock_init(&pctrl->lock); 972 973 /* 974 * Make a copy of the communities which we can use to hold pointers 975 * to the registers. 976 */ 977 pctrl->ncommunities = pctrl->soc->ncommunities; 978 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 979 sizeof(*pctrl->communities), GFP_KERNEL); 980 if (!pctrl->communities) 981 return -ENOMEM; 982 983 for (i = 0; i < pctrl->ncommunities; i++) { 984 struct intel_community *community = &pctrl->communities[i]; 985 struct resource *res; 986 void __iomem *regs; 987 u32 padbar; 988 989 *community = pctrl->soc->communities[i]; 990 991 res = platform_get_resource(pdev, IORESOURCE_MEM, 992 community->barno); 993 regs = devm_ioremap_resource(&pdev->dev, res); 994 if (IS_ERR(regs)) 995 return PTR_ERR(regs); 996 997 /* Read offset of the pad configuration registers */ 998 padbar = readl(regs + PADBAR); 999 1000 community->regs = regs; 1001 community->pad_regs = regs + padbar; 1002 community->ngpps = DIV_ROUND_UP(community->npins, 1003 community->gpp_size); 1004 } 1005 1006 irq = platform_get_irq(pdev, 0); 1007 if (irq < 0) { 1008 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1009 return irq; 1010 } 1011 1012 ret = intel_pinctrl_pm_init(pctrl); 1013 if (ret) 1014 return ret; 1015 1016 pctrl->pctldesc = intel_pinctrl_desc; 1017 pctrl->pctldesc.name = dev_name(&pdev->dev); 1018 pctrl->pctldesc.pins = pctrl->soc->pins; 1019 pctrl->pctldesc.npins = pctrl->soc->npins; 1020 1021 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); 1022 if (IS_ERR(pctrl->pctldev)) { 1023 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1024 return PTR_ERR(pctrl->pctldev); 1025 } 1026 1027 ret = intel_gpio_probe(pctrl, irq); 1028 if (ret) { 1029 pinctrl_unregister(pctrl->pctldev); 1030 return ret; 1031 } 1032 1033 platform_set_drvdata(pdev, pctrl); 1034 1035 return 0; 1036 } 1037 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1038 1039 int intel_pinctrl_remove(struct platform_device *pdev) 1040 { 1041 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1042 1043 gpiochip_remove(&pctrl->chip); 1044 pinctrl_unregister(pctrl->pctldev); 1045 1046 return 0; 1047 } 1048 EXPORT_SYMBOL_GPL(intel_pinctrl_remove); 1049 1050 #ifdef CONFIG_PM_SLEEP 1051 int intel_pinctrl_suspend(struct device *dev) 1052 { 1053 struct platform_device *pdev = to_platform_device(dev); 1054 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1055 struct intel_community_context *communities; 1056 struct intel_pad_context *pads; 1057 int i; 1058 1059 pads = pctrl->context.pads; 1060 for (i = 0; i < pctrl->soc->npins; i++) { 1061 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1062 u32 val; 1063 1064 if (!intel_pad_usable(pctrl, desc->number)) 1065 continue; 1066 1067 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1068 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1069 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1070 pads[i].padcfg1 = val; 1071 } 1072 1073 communities = pctrl->context.communities; 1074 for (i = 0; i < pctrl->ncommunities; i++) { 1075 struct intel_community *community = &pctrl->communities[i]; 1076 void __iomem *base; 1077 unsigned gpp; 1078 1079 base = community->regs + community->ie_offset; 1080 for (gpp = 0; gpp < community->ngpps; gpp++) 1081 communities[i].intmask[gpp] = readl(base + gpp * 4); 1082 } 1083 1084 return 0; 1085 } 1086 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1087 1088 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1089 { 1090 size_t i; 1091 1092 for (i = 0; i < pctrl->ncommunities; i++) { 1093 const struct intel_community *community; 1094 void __iomem *base; 1095 unsigned gpp; 1096 1097 community = &pctrl->communities[i]; 1098 base = community->regs; 1099 1100 for (gpp = 0; gpp < community->ngpps; gpp++) { 1101 /* Mask and clear all interrupts */ 1102 writel(0, base + community->ie_offset + gpp * 4); 1103 writel(0xffff, base + GPI_IS + gpp * 4); 1104 } 1105 } 1106 } 1107 1108 int intel_pinctrl_resume(struct device *dev) 1109 { 1110 struct platform_device *pdev = to_platform_device(dev); 1111 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1112 const struct intel_community_context *communities; 1113 const struct intel_pad_context *pads; 1114 int i; 1115 1116 /* Mask all interrupts */ 1117 intel_gpio_irq_init(pctrl); 1118 1119 pads = pctrl->context.pads; 1120 for (i = 0; i < pctrl->soc->npins; i++) { 1121 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1122 void __iomem *padcfg; 1123 u32 val; 1124 1125 if (!intel_pad_usable(pctrl, desc->number)) 1126 continue; 1127 1128 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1129 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1130 if (val != pads[i].padcfg0) { 1131 writel(pads[i].padcfg0, padcfg); 1132 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1133 desc->number, readl(padcfg)); 1134 } 1135 1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1137 val = readl(padcfg); 1138 if (val != pads[i].padcfg1) { 1139 writel(pads[i].padcfg1, padcfg); 1140 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1141 desc->number, readl(padcfg)); 1142 } 1143 } 1144 1145 communities = pctrl->context.communities; 1146 for (i = 0; i < pctrl->ncommunities; i++) { 1147 struct intel_community *community = &pctrl->communities[i]; 1148 void __iomem *base; 1149 unsigned gpp; 1150 1151 base = community->regs + community->ie_offset; 1152 for (gpp = 0; gpp < community->ngpps; gpp++) { 1153 writel(communities[i].intmask[gpp], base + gpp * 4); 1154 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1155 readl(base + gpp * 4)); 1156 } 1157 } 1158 1159 return 0; 1160 } 1161 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1162 #endif 1163 1164 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1165 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1166 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1167 MODULE_LICENSE("GPL v2"); 1168