1 /*
2  * Intel pinctrl/GPIO core driver.
3  *
4  * Copyright (C) 2015, Intel Corporation
5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/log2.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 
23 #include "../core.h"
24 #include "pinctrl-intel.h"
25 
26 /* Offset from regs */
27 #define REVID				0x000
28 #define REVID_SHIFT			16
29 #define REVID_MASK			GENMASK(31, 16)
30 
31 #define PADBAR				0x00c
32 #define GPI_IS				0x100
33 #define GPI_GPE_STS			0x140
34 #define GPI_GPE_EN			0x160
35 
36 #define PADOWN_BITS			4
37 #define PADOWN_SHIFT(p)			((p) % 8 * PADOWN_BITS)
38 #define PADOWN_MASK(p)			(0xf << PADOWN_SHIFT(p))
39 #define PADOWN_GPP(p)			((p) / 8)
40 
41 /* Offset from pad_regs */
42 #define PADCFG0				0x000
43 #define PADCFG0_RXEVCFG_SHIFT		25
44 #define PADCFG0_RXEVCFG_MASK		(3 << PADCFG0_RXEVCFG_SHIFT)
45 #define PADCFG0_RXEVCFG_LEVEL		0
46 #define PADCFG0_RXEVCFG_EDGE		1
47 #define PADCFG0_RXEVCFG_DISABLED	2
48 #define PADCFG0_RXEVCFG_EDGE_BOTH	3
49 #define PADCFG0_PREGFRXSEL		BIT(24)
50 #define PADCFG0_RXINV			BIT(23)
51 #define PADCFG0_GPIROUTIOXAPIC		BIT(20)
52 #define PADCFG0_GPIROUTSCI		BIT(19)
53 #define PADCFG0_GPIROUTSMI		BIT(18)
54 #define PADCFG0_GPIROUTNMI		BIT(17)
55 #define PADCFG0_PMODE_SHIFT		10
56 #define PADCFG0_PMODE_MASK		(0xf << PADCFG0_PMODE_SHIFT)
57 #define PADCFG0_GPIORXDIS		BIT(9)
58 #define PADCFG0_GPIOTXDIS		BIT(8)
59 #define PADCFG0_GPIORXSTATE		BIT(1)
60 #define PADCFG0_GPIOTXSTATE		BIT(0)
61 
62 #define PADCFG1				0x004
63 #define PADCFG1_TERM_UP			BIT(13)
64 #define PADCFG1_TERM_SHIFT		10
65 #define PADCFG1_TERM_MASK		(7 << PADCFG1_TERM_SHIFT)
66 #define PADCFG1_TERM_20K		4
67 #define PADCFG1_TERM_2K			3
68 #define PADCFG1_TERM_5K			2
69 #define PADCFG1_TERM_1K			1
70 
71 #define PADCFG2				0x008
72 #define PADCFG2_DEBEN			BIT(0)
73 #define PADCFG2_DEBOUNCE_SHIFT		1
74 #define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)
75 
76 #define DEBOUNCE_PERIOD			31250 /* ns */
77 
78 struct intel_pad_context {
79 	u32 padcfg0;
80 	u32 padcfg1;
81 	u32 padcfg2;
82 };
83 
84 struct intel_community_context {
85 	u32 *intmask;
86 };
87 
88 struct intel_pinctrl_context {
89 	struct intel_pad_context *pads;
90 	struct intel_community_context *communities;
91 };
92 
93 /**
94  * struct intel_pinctrl - Intel pinctrl private structure
95  * @dev: Pointer to the device structure
96  * @lock: Lock to serialize register access
97  * @pctldesc: Pin controller description
98  * @pctldev: Pointer to the pin controller device
99  * @chip: GPIO chip in this pin controller
100  * @soc: SoC/PCH specific pin configuration data
101  * @communities: All communities in this pin controller
102  * @ncommunities: Number of communities in this pin controller
103  * @context: Configuration saved over system sleep
104  * @irq: pinctrl/GPIO chip irq number
105  */
106 struct intel_pinctrl {
107 	struct device *dev;
108 	raw_spinlock_t lock;
109 	struct pinctrl_desc pctldesc;
110 	struct pinctrl_dev *pctldev;
111 	struct gpio_chip chip;
112 	const struct intel_pinctrl_soc_data *soc;
113 	struct intel_community *communities;
114 	size_t ncommunities;
115 	struct intel_pinctrl_context context;
116 	int irq;
117 };
118 
119 #define pin_to_padno(c, p)	((p) - (c)->pin_base)
120 #define padgroup_offset(g, p)	((p) - (g)->base)
121 
122 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
123 						   unsigned pin)
124 {
125 	struct intel_community *community;
126 	int i;
127 
128 	for (i = 0; i < pctrl->ncommunities; i++) {
129 		community = &pctrl->communities[i];
130 		if (pin >= community->pin_base &&
131 		    pin < community->pin_base + community->npins)
132 			return community;
133 	}
134 
135 	dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
136 	return NULL;
137 }
138 
139 static const struct intel_padgroup *
140 intel_community_get_padgroup(const struct intel_community *community,
141 			     unsigned pin)
142 {
143 	int i;
144 
145 	for (i = 0; i < community->ngpps; i++) {
146 		const struct intel_padgroup *padgrp = &community->gpps[i];
147 
148 		if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
149 			return padgrp;
150 	}
151 
152 	return NULL;
153 }
154 
155 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
156 				      unsigned reg)
157 {
158 	const struct intel_community *community;
159 	unsigned padno;
160 	size_t nregs;
161 
162 	community = intel_get_community(pctrl, pin);
163 	if (!community)
164 		return NULL;
165 
166 	padno = pin_to_padno(community, pin);
167 	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
168 
169 	if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
170 		return NULL;
171 
172 	return community->pad_regs + reg + padno * nregs * 4;
173 }
174 
175 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
176 {
177 	const struct intel_community *community;
178 	const struct intel_padgroup *padgrp;
179 	unsigned gpp, offset, gpp_offset;
180 	void __iomem *padown;
181 
182 	community = intel_get_community(pctrl, pin);
183 	if (!community)
184 		return false;
185 	if (!community->padown_offset)
186 		return true;
187 
188 	padgrp = intel_community_get_padgroup(community, pin);
189 	if (!padgrp)
190 		return false;
191 
192 	gpp_offset = padgroup_offset(padgrp, pin);
193 	gpp = PADOWN_GPP(gpp_offset);
194 	offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
195 	padown = community->regs + offset;
196 
197 	return !(readl(padown) & PADOWN_MASK(gpp_offset));
198 }
199 
200 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
201 {
202 	const struct intel_community *community;
203 	const struct intel_padgroup *padgrp;
204 	unsigned offset, gpp_offset;
205 	void __iomem *hostown;
206 
207 	community = intel_get_community(pctrl, pin);
208 	if (!community)
209 		return true;
210 	if (!community->hostown_offset)
211 		return false;
212 
213 	padgrp = intel_community_get_padgroup(community, pin);
214 	if (!padgrp)
215 		return true;
216 
217 	gpp_offset = padgroup_offset(padgrp, pin);
218 	offset = community->hostown_offset + padgrp->reg_num * 4;
219 	hostown = community->regs + offset;
220 
221 	return !(readl(hostown) & BIT(gpp_offset));
222 }
223 
224 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
225 {
226 	struct intel_community *community;
227 	const struct intel_padgroup *padgrp;
228 	unsigned offset, gpp_offset;
229 	u32 value;
230 
231 	community = intel_get_community(pctrl, pin);
232 	if (!community)
233 		return true;
234 	if (!community->padcfglock_offset)
235 		return false;
236 
237 	padgrp = intel_community_get_padgroup(community, pin);
238 	if (!padgrp)
239 		return true;
240 
241 	gpp_offset = padgroup_offset(padgrp, pin);
242 
243 	/*
244 	 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
245 	 * the pad is considered unlocked. Any other case means that it is
246 	 * either fully or partially locked and we don't touch it.
247 	 */
248 	offset = community->padcfglock_offset + padgrp->reg_num * 8;
249 	value = readl(community->regs + offset);
250 	if (value & BIT(gpp_offset))
251 		return true;
252 
253 	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
254 	value = readl(community->regs + offset);
255 	if (value & BIT(gpp_offset))
256 		return true;
257 
258 	return false;
259 }
260 
261 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
262 {
263 	return intel_pad_owned_by_host(pctrl, pin) &&
264 		!intel_pad_locked(pctrl, pin);
265 }
266 
267 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
268 {
269 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
270 
271 	return pctrl->soc->ngroups;
272 }
273 
274 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
275 				      unsigned group)
276 {
277 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
278 
279 	return pctrl->soc->groups[group].name;
280 }
281 
282 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
283 			      const unsigned **pins, unsigned *npins)
284 {
285 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
286 
287 	*pins = pctrl->soc->groups[group].pins;
288 	*npins = pctrl->soc->groups[group].npins;
289 	return 0;
290 }
291 
292 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
293 			       unsigned pin)
294 {
295 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
296 	void __iomem *padcfg;
297 	u32 cfg0, cfg1, mode;
298 	bool locked, acpi;
299 
300 	if (!intel_pad_owned_by_host(pctrl, pin)) {
301 		seq_puts(s, "not available");
302 		return;
303 	}
304 
305 	cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
306 	cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
307 
308 	mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
309 	if (!mode)
310 		seq_puts(s, "GPIO ");
311 	else
312 		seq_printf(s, "mode %d ", mode);
313 
314 	seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
315 
316 	/* Dump the additional PADCFG registers if available */
317 	padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
318 	if (padcfg)
319 		seq_printf(s, " 0x%08x", readl(padcfg));
320 
321 	locked = intel_pad_locked(pctrl, pin);
322 	acpi = intel_pad_acpi_mode(pctrl, pin);
323 
324 	if (locked || acpi) {
325 		seq_puts(s, " [");
326 		if (locked) {
327 			seq_puts(s, "LOCKED");
328 			if (acpi)
329 				seq_puts(s, ", ");
330 		}
331 		if (acpi)
332 			seq_puts(s, "ACPI");
333 		seq_puts(s, "]");
334 	}
335 }
336 
337 static const struct pinctrl_ops intel_pinctrl_ops = {
338 	.get_groups_count = intel_get_groups_count,
339 	.get_group_name = intel_get_group_name,
340 	.get_group_pins = intel_get_group_pins,
341 	.pin_dbg_show = intel_pin_dbg_show,
342 };
343 
344 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
345 {
346 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
347 
348 	return pctrl->soc->nfunctions;
349 }
350 
351 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
352 					   unsigned function)
353 {
354 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
355 
356 	return pctrl->soc->functions[function].name;
357 }
358 
359 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
360 				     unsigned function,
361 				     const char * const **groups,
362 				     unsigned * const ngroups)
363 {
364 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
365 
366 	*groups = pctrl->soc->functions[function].groups;
367 	*ngroups = pctrl->soc->functions[function].ngroups;
368 	return 0;
369 }
370 
371 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
372 				unsigned group)
373 {
374 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
375 	const struct intel_pingroup *grp = &pctrl->soc->groups[group];
376 	unsigned long flags;
377 	int i;
378 
379 	raw_spin_lock_irqsave(&pctrl->lock, flags);
380 
381 	/*
382 	 * All pins in the groups needs to be accessible and writable
383 	 * before we can enable the mux for this group.
384 	 */
385 	for (i = 0; i < grp->npins; i++) {
386 		if (!intel_pad_usable(pctrl, grp->pins[i])) {
387 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
388 			return -EBUSY;
389 		}
390 	}
391 
392 	/* Now enable the mux setting for each pin in the group */
393 	for (i = 0; i < grp->npins; i++) {
394 		void __iomem *padcfg0;
395 		u32 value;
396 
397 		padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
398 		value = readl(padcfg0);
399 
400 		value &= ~PADCFG0_PMODE_MASK;
401 
402 		if (grp->modes)
403 			value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
404 		else
405 			value |= grp->mode << PADCFG0_PMODE_SHIFT;
406 
407 		writel(value, padcfg0);
408 	}
409 
410 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
411 
412 	return 0;
413 }
414 
415 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
416 {
417 	u32 value;
418 
419 	value = readl(padcfg0);
420 	if (input) {
421 		value &= ~PADCFG0_GPIORXDIS;
422 		value |= PADCFG0_GPIOTXDIS;
423 	} else {
424 		value &= ~PADCFG0_GPIOTXDIS;
425 		value |= PADCFG0_GPIORXDIS;
426 	}
427 	writel(value, padcfg0);
428 }
429 
430 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
431 				     struct pinctrl_gpio_range *range,
432 				     unsigned pin)
433 {
434 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
435 	void __iomem *padcfg0;
436 	unsigned long flags;
437 	u32 value;
438 
439 	raw_spin_lock_irqsave(&pctrl->lock, flags);
440 
441 	if (!intel_pad_usable(pctrl, pin)) {
442 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
443 		return -EBUSY;
444 	}
445 
446 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
447 	/* Put the pad into GPIO mode */
448 	value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
449 	/* Disable SCI/SMI/NMI generation */
450 	value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
451 	value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
452 	writel(value, padcfg0);
453 
454 	/* Disable TX buffer and enable RX (this will be input) */
455 	__intel_gpio_set_direction(padcfg0, true);
456 
457 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
458 
459 	return 0;
460 }
461 
462 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
463 				    struct pinctrl_gpio_range *range,
464 				    unsigned pin, bool input)
465 {
466 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
467 	void __iomem *padcfg0;
468 	unsigned long flags;
469 
470 	raw_spin_lock_irqsave(&pctrl->lock, flags);
471 
472 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
473 	__intel_gpio_set_direction(padcfg0, input);
474 
475 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
476 
477 	return 0;
478 }
479 
480 static const struct pinmux_ops intel_pinmux_ops = {
481 	.get_functions_count = intel_get_functions_count,
482 	.get_function_name = intel_get_function_name,
483 	.get_function_groups = intel_get_function_groups,
484 	.set_mux = intel_pinmux_set_mux,
485 	.gpio_request_enable = intel_gpio_request_enable,
486 	.gpio_set_direction = intel_gpio_set_direction,
487 };
488 
489 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
490 			    unsigned long *config)
491 {
492 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
493 	enum pin_config_param param = pinconf_to_config_param(*config);
494 	const struct intel_community *community;
495 	u32 value, term;
496 	u32 arg = 0;
497 
498 	if (!intel_pad_owned_by_host(pctrl, pin))
499 		return -ENOTSUPP;
500 
501 	community = intel_get_community(pctrl, pin);
502 	value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
503 	term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
504 
505 	switch (param) {
506 	case PIN_CONFIG_BIAS_DISABLE:
507 		if (term)
508 			return -EINVAL;
509 		break;
510 
511 	case PIN_CONFIG_BIAS_PULL_UP:
512 		if (!term || !(value & PADCFG1_TERM_UP))
513 			return -EINVAL;
514 
515 		switch (term) {
516 		case PADCFG1_TERM_1K:
517 			arg = 1000;
518 			break;
519 		case PADCFG1_TERM_2K:
520 			arg = 2000;
521 			break;
522 		case PADCFG1_TERM_5K:
523 			arg = 5000;
524 			break;
525 		case PADCFG1_TERM_20K:
526 			arg = 20000;
527 			break;
528 		}
529 
530 		break;
531 
532 	case PIN_CONFIG_BIAS_PULL_DOWN:
533 		if (!term || value & PADCFG1_TERM_UP)
534 			return -EINVAL;
535 
536 		switch (term) {
537 		case PADCFG1_TERM_1K:
538 			if (!(community->features & PINCTRL_FEATURE_1K_PD))
539 				return -EINVAL;
540 			arg = 1000;
541 			break;
542 		case PADCFG1_TERM_5K:
543 			arg = 5000;
544 			break;
545 		case PADCFG1_TERM_20K:
546 			arg = 20000;
547 			break;
548 		}
549 
550 		break;
551 
552 	case PIN_CONFIG_INPUT_DEBOUNCE: {
553 		void __iomem *padcfg2;
554 		u32 v;
555 
556 		padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
557 		if (!padcfg2)
558 			return -ENOTSUPP;
559 
560 		v = readl(padcfg2);
561 		if (!(v & PADCFG2_DEBEN))
562 			return -EINVAL;
563 
564 		v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
565 		arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
566 
567 		break;
568 	}
569 
570 	default:
571 		return -ENOTSUPP;
572 	}
573 
574 	*config = pinconf_to_config_packed(param, arg);
575 	return 0;
576 }
577 
578 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
579 				 unsigned long config)
580 {
581 	unsigned param = pinconf_to_config_param(config);
582 	unsigned arg = pinconf_to_config_argument(config);
583 	const struct intel_community *community;
584 	void __iomem *padcfg1;
585 	unsigned long flags;
586 	int ret = 0;
587 	u32 value;
588 
589 	raw_spin_lock_irqsave(&pctrl->lock, flags);
590 
591 	community = intel_get_community(pctrl, pin);
592 	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
593 	value = readl(padcfg1);
594 
595 	switch (param) {
596 	case PIN_CONFIG_BIAS_DISABLE:
597 		value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
598 		break;
599 
600 	case PIN_CONFIG_BIAS_PULL_UP:
601 		value &= ~PADCFG1_TERM_MASK;
602 
603 		value |= PADCFG1_TERM_UP;
604 
605 		switch (arg) {
606 		case 20000:
607 			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
608 			break;
609 		case 5000:
610 			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
611 			break;
612 		case 2000:
613 			value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
614 			break;
615 		case 1000:
616 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
617 			break;
618 		default:
619 			ret = -EINVAL;
620 		}
621 
622 		break;
623 
624 	case PIN_CONFIG_BIAS_PULL_DOWN:
625 		value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
626 
627 		switch (arg) {
628 		case 20000:
629 			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
630 			break;
631 		case 5000:
632 			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
633 			break;
634 		case 1000:
635 			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
636 				ret = -EINVAL;
637 				break;
638 			}
639 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
640 			break;
641 		default:
642 			ret = -EINVAL;
643 		}
644 
645 		break;
646 	}
647 
648 	if (!ret)
649 		writel(value, padcfg1);
650 
651 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
652 
653 	return ret;
654 }
655 
656 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
657 				     unsigned debounce)
658 {
659 	void __iomem *padcfg0, *padcfg2;
660 	unsigned long flags;
661 	u32 value0, value2;
662 	int ret = 0;
663 
664 	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
665 	if (!padcfg2)
666 		return -ENOTSUPP;
667 
668 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
669 
670 	raw_spin_lock_irqsave(&pctrl->lock, flags);
671 
672 	value0 = readl(padcfg0);
673 	value2 = readl(padcfg2);
674 
675 	/* Disable glitch filter and debouncer */
676 	value0 &= ~PADCFG0_PREGFRXSEL;
677 	value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
678 
679 	if (debounce) {
680 		unsigned long v;
681 
682 		v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
683 		if (v < 3 || v > 15) {
684 			ret = -EINVAL;
685 			goto exit_unlock;
686 		} else {
687 			/* Enable glitch filter and debouncer */
688 			value0 |= PADCFG0_PREGFRXSEL;
689 			value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
690 			value2 |= PADCFG2_DEBEN;
691 		}
692 	}
693 
694 	writel(value0, padcfg0);
695 	writel(value2, padcfg2);
696 
697 exit_unlock:
698 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
699 
700 	return ret;
701 }
702 
703 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
704 			  unsigned long *configs, unsigned nconfigs)
705 {
706 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
707 	int i, ret;
708 
709 	if (!intel_pad_usable(pctrl, pin))
710 		return -ENOTSUPP;
711 
712 	for (i = 0; i < nconfigs; i++) {
713 		switch (pinconf_to_config_param(configs[i])) {
714 		case PIN_CONFIG_BIAS_DISABLE:
715 		case PIN_CONFIG_BIAS_PULL_UP:
716 		case PIN_CONFIG_BIAS_PULL_DOWN:
717 			ret = intel_config_set_pull(pctrl, pin, configs[i]);
718 			if (ret)
719 				return ret;
720 			break;
721 
722 		case PIN_CONFIG_INPUT_DEBOUNCE:
723 			ret = intel_config_set_debounce(pctrl, pin,
724 				pinconf_to_config_argument(configs[i]));
725 			if (ret)
726 				return ret;
727 			break;
728 
729 		default:
730 			return -ENOTSUPP;
731 		}
732 	}
733 
734 	return 0;
735 }
736 
737 static const struct pinconf_ops intel_pinconf_ops = {
738 	.is_generic = true,
739 	.pin_config_get = intel_config_get,
740 	.pin_config_set = intel_config_set,
741 };
742 
743 static const struct pinctrl_desc intel_pinctrl_desc = {
744 	.pctlops = &intel_pinctrl_ops,
745 	.pmxops = &intel_pinmux_ops,
746 	.confops = &intel_pinconf_ops,
747 	.owner = THIS_MODULE,
748 };
749 
750 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
751 {
752 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
753 	void __iomem *reg;
754 
755 	reg = intel_get_padcfg(pctrl, offset, PADCFG0);
756 	if (!reg)
757 		return -EINVAL;
758 
759 	return !!(readl(reg) & PADCFG0_GPIORXSTATE);
760 }
761 
762 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
763 {
764 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
765 	void __iomem *reg;
766 
767 	reg = intel_get_padcfg(pctrl, offset, PADCFG0);
768 	if (reg) {
769 		unsigned long flags;
770 		u32 padcfg0;
771 
772 		raw_spin_lock_irqsave(&pctrl->lock, flags);
773 		padcfg0 = readl(reg);
774 		if (value)
775 			padcfg0 |= PADCFG0_GPIOTXSTATE;
776 		else
777 			padcfg0 &= ~PADCFG0_GPIOTXSTATE;
778 		writel(padcfg0, reg);
779 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
780 	}
781 }
782 
783 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
784 {
785 	return pinctrl_gpio_direction_input(chip->base + offset);
786 }
787 
788 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
789 				       int value)
790 {
791 	intel_gpio_set(chip, offset, value);
792 	return pinctrl_gpio_direction_output(chip->base + offset);
793 }
794 
795 static const struct gpio_chip intel_gpio_chip = {
796 	.owner = THIS_MODULE,
797 	.request = gpiochip_generic_request,
798 	.free = gpiochip_generic_free,
799 	.direction_input = intel_gpio_direction_input,
800 	.direction_output = intel_gpio_direction_output,
801 	.get = intel_gpio_get,
802 	.set = intel_gpio_set,
803 	.set_config = gpiochip_generic_config,
804 };
805 
806 static void intel_gpio_irq_ack(struct irq_data *d)
807 {
808 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
809 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
810 	const struct intel_community *community;
811 	unsigned pin = irqd_to_hwirq(d);
812 
813 	community = intel_get_community(pctrl, pin);
814 	if (community) {
815 		const struct intel_padgroup *padgrp;
816 		unsigned gpp, gpp_offset;
817 
818 		padgrp = intel_community_get_padgroup(community, pin);
819 		if (!padgrp)
820 			return;
821 
822 		gpp = padgrp->reg_num;
823 		gpp_offset = padgroup_offset(padgrp, pin);
824 
825 		raw_spin_lock(&pctrl->lock);
826 		writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
827 		raw_spin_unlock(&pctrl->lock);
828 	}
829 }
830 
831 static void intel_gpio_irq_enable(struct irq_data *d)
832 {
833 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
834 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
835 	const struct intel_community *community;
836 	unsigned pin = irqd_to_hwirq(d);
837 
838 	community = intel_get_community(pctrl, pin);
839 	if (community) {
840 		const struct intel_padgroup *padgrp;
841 		unsigned gpp, gpp_offset;
842 		unsigned long flags;
843 		u32 value;
844 
845 		padgrp = intel_community_get_padgroup(community, pin);
846 		if (!padgrp)
847 			return;
848 
849 		gpp = padgrp->reg_num;
850 		gpp_offset = padgroup_offset(padgrp, pin);
851 
852 		raw_spin_lock_irqsave(&pctrl->lock, flags);
853 		/* Clear interrupt status first to avoid unexpected interrupt */
854 		writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
855 
856 		value = readl(community->regs + community->ie_offset + gpp * 4);
857 		value |= BIT(gpp_offset);
858 		writel(value, community->regs + community->ie_offset + gpp * 4);
859 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
860 	}
861 }
862 
863 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
864 {
865 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
866 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
867 	const struct intel_community *community;
868 	unsigned pin = irqd_to_hwirq(d);
869 
870 	community = intel_get_community(pctrl, pin);
871 	if (community) {
872 		const struct intel_padgroup *padgrp;
873 		unsigned gpp, gpp_offset;
874 		unsigned long flags;
875 		void __iomem *reg;
876 		u32 value;
877 
878 		padgrp = intel_community_get_padgroup(community, pin);
879 		if (!padgrp)
880 			return;
881 
882 		gpp = padgrp->reg_num;
883 		gpp_offset = padgroup_offset(padgrp, pin);
884 
885 		reg = community->regs + community->ie_offset + gpp * 4;
886 
887 		raw_spin_lock_irqsave(&pctrl->lock, flags);
888 		value = readl(reg);
889 		if (mask)
890 			value &= ~BIT(gpp_offset);
891 		else
892 			value |= BIT(gpp_offset);
893 		writel(value, reg);
894 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
895 	}
896 }
897 
898 static void intel_gpio_irq_mask(struct irq_data *d)
899 {
900 	intel_gpio_irq_mask_unmask(d, true);
901 }
902 
903 static void intel_gpio_irq_unmask(struct irq_data *d)
904 {
905 	intel_gpio_irq_mask_unmask(d, false);
906 }
907 
908 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
909 {
910 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
911 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
912 	unsigned pin = irqd_to_hwirq(d);
913 	unsigned long flags;
914 	void __iomem *reg;
915 	u32 value;
916 
917 	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
918 	if (!reg)
919 		return -EINVAL;
920 
921 	/*
922 	 * If the pin is in ACPI mode it is still usable as a GPIO but it
923 	 * cannot be used as IRQ because GPI_IS status bit will not be
924 	 * updated by the host controller hardware.
925 	 */
926 	if (intel_pad_acpi_mode(pctrl, pin)) {
927 		dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
928 		return -EPERM;
929 	}
930 
931 	raw_spin_lock_irqsave(&pctrl->lock, flags);
932 
933 	value = readl(reg);
934 
935 	value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
936 
937 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
938 		value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
939 	} else if (type & IRQ_TYPE_EDGE_FALLING) {
940 		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
941 		value |= PADCFG0_RXINV;
942 	} else if (type & IRQ_TYPE_EDGE_RISING) {
943 		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
944 	} else if (type & IRQ_TYPE_LEVEL_MASK) {
945 		if (type & IRQ_TYPE_LEVEL_LOW)
946 			value |= PADCFG0_RXINV;
947 	} else {
948 		value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
949 	}
950 
951 	writel(value, reg);
952 
953 	if (type & IRQ_TYPE_EDGE_BOTH)
954 		irq_set_handler_locked(d, handle_edge_irq);
955 	else if (type & IRQ_TYPE_LEVEL_MASK)
956 		irq_set_handler_locked(d, handle_level_irq);
957 
958 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
959 
960 	return 0;
961 }
962 
963 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
964 {
965 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
966 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
967 	unsigned pin = irqd_to_hwirq(d);
968 
969 	if (on)
970 		enable_irq_wake(pctrl->irq);
971 	else
972 		disable_irq_wake(pctrl->irq);
973 
974 	dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
975 	return 0;
976 }
977 
978 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
979 	const struct intel_community *community)
980 {
981 	struct gpio_chip *gc = &pctrl->chip;
982 	irqreturn_t ret = IRQ_NONE;
983 	int gpp;
984 
985 	for (gpp = 0; gpp < community->ngpps; gpp++) {
986 		const struct intel_padgroup *padgrp = &community->gpps[gpp];
987 		unsigned long pending, enabled, gpp_offset;
988 
989 		pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);
990 		enabled = readl(community->regs + community->ie_offset +
991 				padgrp->reg_num * 4);
992 
993 		/* Only interrupts that are enabled */
994 		pending &= enabled;
995 
996 		for_each_set_bit(gpp_offset, &pending, padgrp->size) {
997 			unsigned padno, irq;
998 
999 			padno = padgrp->base - community->pin_base + gpp_offset;
1000 			if (padno >= community->npins)
1001 				break;
1002 
1003 			irq = irq_find_mapping(gc->irqdomain,
1004 					       community->pin_base + padno);
1005 			generic_handle_irq(irq);
1006 
1007 			ret |= IRQ_HANDLED;
1008 		}
1009 	}
1010 
1011 	return ret;
1012 }
1013 
1014 static irqreturn_t intel_gpio_irq(int irq, void *data)
1015 {
1016 	const struct intel_community *community;
1017 	struct intel_pinctrl *pctrl = data;
1018 	irqreturn_t ret = IRQ_NONE;
1019 	int i;
1020 
1021 	/* Need to check all communities for pending interrupts */
1022 	for (i = 0; i < pctrl->ncommunities; i++) {
1023 		community = &pctrl->communities[i];
1024 		ret |= intel_gpio_community_irq_handler(pctrl, community);
1025 	}
1026 
1027 	return ret;
1028 }
1029 
1030 static struct irq_chip intel_gpio_irqchip = {
1031 	.name = "intel-gpio",
1032 	.irq_enable = intel_gpio_irq_enable,
1033 	.irq_ack = intel_gpio_irq_ack,
1034 	.irq_mask = intel_gpio_irq_mask,
1035 	.irq_unmask = intel_gpio_irq_unmask,
1036 	.irq_set_type = intel_gpio_irq_type,
1037 	.irq_set_wake = intel_gpio_irq_wake,
1038 };
1039 
1040 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1041 {
1042 	int ret;
1043 
1044 	pctrl->chip = intel_gpio_chip;
1045 
1046 	pctrl->chip.ngpio = pctrl->soc->npins;
1047 	pctrl->chip.label = dev_name(pctrl->dev);
1048 	pctrl->chip.parent = pctrl->dev;
1049 	pctrl->chip.base = -1;
1050 	pctrl->irq = irq;
1051 
1052 	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1053 	if (ret) {
1054 		dev_err(pctrl->dev, "failed to register gpiochip\n");
1055 		return ret;
1056 	}
1057 
1058 	ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1059 				     0, 0, pctrl->soc->npins);
1060 	if (ret) {
1061 		dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1062 		return ret;
1063 	}
1064 
1065 	/*
1066 	 * We need to request the interrupt here (instead of providing chip
1067 	 * to the irq directly) because on some platforms several GPIO
1068 	 * controllers share the same interrupt line.
1069 	 */
1070 	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1071 			       IRQF_SHARED | IRQF_NO_THREAD,
1072 			       dev_name(pctrl->dev), pctrl);
1073 	if (ret) {
1074 		dev_err(pctrl->dev, "failed to request interrupt\n");
1075 		return ret;
1076 	}
1077 
1078 	ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1079 				   handle_bad_irq, IRQ_TYPE_NONE);
1080 	if (ret) {
1081 		dev_err(pctrl->dev, "failed to add irqchip\n");
1082 		return ret;
1083 	}
1084 
1085 	gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1086 				     NULL);
1087 	return 0;
1088 }
1089 
1090 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1091 				       struct intel_community *community)
1092 {
1093 	struct intel_padgroup *gpps;
1094 	unsigned npins = community->npins;
1095 	unsigned padown_num = 0;
1096 	size_t ngpps, i;
1097 
1098 	if (community->gpps)
1099 		ngpps = community->ngpps;
1100 	else
1101 		ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1102 
1103 	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1104 	if (!gpps)
1105 		return -ENOMEM;
1106 
1107 	for (i = 0; i < ngpps; i++) {
1108 		if (community->gpps) {
1109 			gpps[i] = community->gpps[i];
1110 		} else {
1111 			unsigned gpp_size = community->gpp_size;
1112 
1113 			gpps[i].reg_num = i;
1114 			gpps[i].base = community->pin_base + i * gpp_size;
1115 			gpps[i].size = min(gpp_size, npins);
1116 			npins -= gpps[i].size;
1117 		}
1118 
1119 		if (gpps[i].size > 32)
1120 			return -EINVAL;
1121 
1122 		gpps[i].padown_num = padown_num;
1123 
1124 		/*
1125 		 * In older hardware the number of padown registers per
1126 		 * group is fixed regardless of the group size.
1127 		 */
1128 		if (community->gpp_num_padown_regs)
1129 			padown_num += community->gpp_num_padown_regs;
1130 		else
1131 			padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1132 	}
1133 
1134 	community->ngpps = ngpps;
1135 	community->gpps = gpps;
1136 
1137 	return 0;
1138 }
1139 
1140 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1141 {
1142 #ifdef CONFIG_PM_SLEEP
1143 	const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1144 	struct intel_community_context *communities;
1145 	struct intel_pad_context *pads;
1146 	int i;
1147 
1148 	pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1149 	if (!pads)
1150 		return -ENOMEM;
1151 
1152 	communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1153 				   sizeof(*communities), GFP_KERNEL);
1154 	if (!communities)
1155 		return -ENOMEM;
1156 
1157 
1158 	for (i = 0; i < pctrl->ncommunities; i++) {
1159 		struct intel_community *community = &pctrl->communities[i];
1160 		u32 *intmask;
1161 
1162 		intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1163 				       sizeof(*intmask), GFP_KERNEL);
1164 		if (!intmask)
1165 			return -ENOMEM;
1166 
1167 		communities[i].intmask = intmask;
1168 	}
1169 
1170 	pctrl->context.pads = pads;
1171 	pctrl->context.communities = communities;
1172 #endif
1173 
1174 	return 0;
1175 }
1176 
1177 int intel_pinctrl_probe(struct platform_device *pdev,
1178 			const struct intel_pinctrl_soc_data *soc_data)
1179 {
1180 	struct intel_pinctrl *pctrl;
1181 	int i, ret, irq;
1182 
1183 	if (!soc_data)
1184 		return -EINVAL;
1185 
1186 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1187 	if (!pctrl)
1188 		return -ENOMEM;
1189 
1190 	pctrl->dev = &pdev->dev;
1191 	pctrl->soc = soc_data;
1192 	raw_spin_lock_init(&pctrl->lock);
1193 
1194 	/*
1195 	 * Make a copy of the communities which we can use to hold pointers
1196 	 * to the registers.
1197 	 */
1198 	pctrl->ncommunities = pctrl->soc->ncommunities;
1199 	pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1200 				  sizeof(*pctrl->communities), GFP_KERNEL);
1201 	if (!pctrl->communities)
1202 		return -ENOMEM;
1203 
1204 	for (i = 0; i < pctrl->ncommunities; i++) {
1205 		struct intel_community *community = &pctrl->communities[i];
1206 		struct resource *res;
1207 		void __iomem *regs;
1208 		u32 padbar;
1209 
1210 		*community = pctrl->soc->communities[i];
1211 
1212 		res = platform_get_resource(pdev, IORESOURCE_MEM,
1213 					    community->barno);
1214 		regs = devm_ioremap_resource(&pdev->dev, res);
1215 		if (IS_ERR(regs))
1216 			return PTR_ERR(regs);
1217 
1218 		/*
1219 		 * Determine community features based on the revision if
1220 		 * not specified already.
1221 		 */
1222 		if (!community->features) {
1223 			u32 rev;
1224 
1225 			rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1226 			if (rev >= 0x94) {
1227 				community->features |= PINCTRL_FEATURE_DEBOUNCE;
1228 				community->features |= PINCTRL_FEATURE_1K_PD;
1229 			}
1230 		}
1231 
1232 		/* Read offset of the pad configuration registers */
1233 		padbar = readl(regs + PADBAR);
1234 
1235 		community->regs = regs;
1236 		community->pad_regs = regs + padbar;
1237 
1238 		ret = intel_pinctrl_add_padgroups(pctrl, community);
1239 		if (ret)
1240 			return ret;
1241 	}
1242 
1243 	irq = platform_get_irq(pdev, 0);
1244 	if (irq < 0) {
1245 		dev_err(&pdev->dev, "failed to get interrupt number\n");
1246 		return irq;
1247 	}
1248 
1249 	ret = intel_pinctrl_pm_init(pctrl);
1250 	if (ret)
1251 		return ret;
1252 
1253 	pctrl->pctldesc = intel_pinctrl_desc;
1254 	pctrl->pctldesc.name = dev_name(&pdev->dev);
1255 	pctrl->pctldesc.pins = pctrl->soc->pins;
1256 	pctrl->pctldesc.npins = pctrl->soc->npins;
1257 
1258 	pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1259 					       pctrl);
1260 	if (IS_ERR(pctrl->pctldev)) {
1261 		dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1262 		return PTR_ERR(pctrl->pctldev);
1263 	}
1264 
1265 	ret = intel_gpio_probe(pctrl, irq);
1266 	if (ret)
1267 		return ret;
1268 
1269 	platform_set_drvdata(pdev, pctrl);
1270 
1271 	return 0;
1272 }
1273 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1274 
1275 #ifdef CONFIG_PM_SLEEP
1276 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1277 {
1278 	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1279 
1280 	if (!pd || !intel_pad_usable(pctrl, pin))
1281 		return false;
1282 
1283 	/*
1284 	 * Only restore the pin if it is actually in use by the kernel (or
1285 	 * by userspace). It is possible that some pins are used by the
1286 	 * BIOS during resume and those are not always locked down so leave
1287 	 * them alone.
1288 	 */
1289 	if (pd->mux_owner || pd->gpio_owner ||
1290 	    gpiochip_line_is_irq(&pctrl->chip, pin))
1291 		return true;
1292 
1293 	return false;
1294 }
1295 
1296 int intel_pinctrl_suspend(struct device *dev)
1297 {
1298 	struct platform_device *pdev = to_platform_device(dev);
1299 	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1300 	struct intel_community_context *communities;
1301 	struct intel_pad_context *pads;
1302 	int i;
1303 
1304 	pads = pctrl->context.pads;
1305 	for (i = 0; i < pctrl->soc->npins; i++) {
1306 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1307 		void __iomem *padcfg;
1308 		u32 val;
1309 
1310 		if (!intel_pinctrl_should_save(pctrl, desc->number))
1311 			continue;
1312 
1313 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1314 		pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1315 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1316 		pads[i].padcfg1 = val;
1317 
1318 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1319 		if (padcfg)
1320 			pads[i].padcfg2 = readl(padcfg);
1321 	}
1322 
1323 	communities = pctrl->context.communities;
1324 	for (i = 0; i < pctrl->ncommunities; i++) {
1325 		struct intel_community *community = &pctrl->communities[i];
1326 		void __iomem *base;
1327 		unsigned gpp;
1328 
1329 		base = community->regs + community->ie_offset;
1330 		for (gpp = 0; gpp < community->ngpps; gpp++)
1331 			communities[i].intmask[gpp] = readl(base + gpp * 4);
1332 	}
1333 
1334 	return 0;
1335 }
1336 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1337 
1338 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1339 {
1340 	size_t i;
1341 
1342 	for (i = 0; i < pctrl->ncommunities; i++) {
1343 		const struct intel_community *community;
1344 		void __iomem *base;
1345 		unsigned gpp;
1346 
1347 		community = &pctrl->communities[i];
1348 		base = community->regs;
1349 
1350 		for (gpp = 0; gpp < community->ngpps; gpp++) {
1351 			/* Mask and clear all interrupts */
1352 			writel(0, base + community->ie_offset + gpp * 4);
1353 			writel(0xffff, base + GPI_IS + gpp * 4);
1354 		}
1355 	}
1356 }
1357 
1358 int intel_pinctrl_resume(struct device *dev)
1359 {
1360 	struct platform_device *pdev = to_platform_device(dev);
1361 	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1362 	const struct intel_community_context *communities;
1363 	const struct intel_pad_context *pads;
1364 	int i;
1365 
1366 	/* Mask all interrupts */
1367 	intel_gpio_irq_init(pctrl);
1368 
1369 	pads = pctrl->context.pads;
1370 	for (i = 0; i < pctrl->soc->npins; i++) {
1371 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1372 		void __iomem *padcfg;
1373 		u32 val;
1374 
1375 		if (!intel_pinctrl_should_save(pctrl, desc->number))
1376 			continue;
1377 
1378 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1379 		val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1380 		if (val != pads[i].padcfg0) {
1381 			writel(pads[i].padcfg0, padcfg);
1382 			dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1383 				desc->number, readl(padcfg));
1384 		}
1385 
1386 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1387 		val = readl(padcfg);
1388 		if (val != pads[i].padcfg1) {
1389 			writel(pads[i].padcfg1, padcfg);
1390 			dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1391 				desc->number, readl(padcfg));
1392 		}
1393 
1394 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1395 		if (padcfg) {
1396 			val = readl(padcfg);
1397 			if (val != pads[i].padcfg2) {
1398 				writel(pads[i].padcfg2, padcfg);
1399 				dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1400 					desc->number, readl(padcfg));
1401 			}
1402 		}
1403 	}
1404 
1405 	communities = pctrl->context.communities;
1406 	for (i = 0; i < pctrl->ncommunities; i++) {
1407 		struct intel_community *community = &pctrl->communities[i];
1408 		void __iomem *base;
1409 		unsigned gpp;
1410 
1411 		base = community->regs + community->ie_offset;
1412 		for (gpp = 0; gpp < community->ngpps; gpp++) {
1413 			writel(communities[i].intmask[gpp], base + gpp * 4);
1414 			dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1415 				readl(base + gpp * 4));
1416 		}
1417 	}
1418 
1419 	return 0;
1420 }
1421 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1422 #endif
1423 
1424 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1425 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1426 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1427 MODULE_LICENSE("GPL v2");
1428