1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel pinctrl/GPIO core driver.
4  *
5  * Copyright (C) 2015, Intel Corporation
6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/time.h>
18 
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 
24 #include "../core.h"
25 #include "pinctrl-intel.h"
26 
27 /* Offset from regs */
28 #define REVID				0x000
29 #define REVID_SHIFT			16
30 #define REVID_MASK			GENMASK(31, 16)
31 
32 #define CAPLIST				0x004
33 #define CAPLIST_ID_SHIFT		16
34 #define CAPLIST_ID_MASK			GENMASK(23, 16)
35 #define CAPLIST_ID_GPIO_HW_INFO		1
36 #define CAPLIST_ID_PWM			2
37 #define CAPLIST_ID_BLINK		3
38 #define CAPLIST_ID_EXP			4
39 #define CAPLIST_NEXT_SHIFT		0
40 #define CAPLIST_NEXT_MASK		GENMASK(15, 0)
41 
42 #define PADBAR				0x00c
43 
44 #define PADOWN_BITS			4
45 #define PADOWN_SHIFT(p)			((p) % 8 * PADOWN_BITS)
46 #define PADOWN_MASK(p)			(GENMASK(3, 0) << PADOWN_SHIFT(p))
47 #define PADOWN_GPP(p)			((p) / 8)
48 
49 /* Offset from pad_regs */
50 #define PADCFG0				0x000
51 #define PADCFG0_RXEVCFG_SHIFT		25
52 #define PADCFG0_RXEVCFG_MASK		GENMASK(26, 25)
53 #define PADCFG0_RXEVCFG_LEVEL		0
54 #define PADCFG0_RXEVCFG_EDGE		1
55 #define PADCFG0_RXEVCFG_DISABLED	2
56 #define PADCFG0_RXEVCFG_EDGE_BOTH	3
57 #define PADCFG0_PREGFRXSEL		BIT(24)
58 #define PADCFG0_RXINV			BIT(23)
59 #define PADCFG0_GPIROUTIOXAPIC		BIT(20)
60 #define PADCFG0_GPIROUTSCI		BIT(19)
61 #define PADCFG0_GPIROUTSMI		BIT(18)
62 #define PADCFG0_GPIROUTNMI		BIT(17)
63 #define PADCFG0_PMODE_SHIFT		10
64 #define PADCFG0_PMODE_MASK		GENMASK(13, 10)
65 #define PADCFG0_PMODE_GPIO		0
66 #define PADCFG0_GPIORXDIS		BIT(9)
67 #define PADCFG0_GPIOTXDIS		BIT(8)
68 #define PADCFG0_GPIORXSTATE		BIT(1)
69 #define PADCFG0_GPIOTXSTATE		BIT(0)
70 
71 #define PADCFG1				0x004
72 #define PADCFG1_TERM_UP			BIT(13)
73 #define PADCFG1_TERM_SHIFT		10
74 #define PADCFG1_TERM_MASK		GENMASK(12, 10)
75 #define PADCFG1_TERM_20K		BIT(2)
76 #define PADCFG1_TERM_5K			BIT(1)
77 #define PADCFG1_TERM_1K			BIT(0)
78 #define PADCFG1_TERM_833		(BIT(1) | BIT(0))
79 
80 #define PADCFG2				0x008
81 #define PADCFG2_DEBEN			BIT(0)
82 #define PADCFG2_DEBOUNCE_SHIFT		1
83 #define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)
84 
85 #define DEBOUNCE_PERIOD_NSEC		31250
86 
87 struct intel_pad_context {
88 	u32 padcfg0;
89 	u32 padcfg1;
90 	u32 padcfg2;
91 };
92 
93 struct intel_community_context {
94 	u32 *intmask;
95 	u32 *hostown;
96 };
97 
98 #define pin_to_padno(c, p)	((p) - (c)->pin_base)
99 #define padgroup_offset(g, p)	((p) - (g)->base)
100 
101 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
102 						   unsigned int pin)
103 {
104 	struct intel_community *community;
105 	int i;
106 
107 	for (i = 0; i < pctrl->ncommunities; i++) {
108 		community = &pctrl->communities[i];
109 		if (pin >= community->pin_base &&
110 		    pin < community->pin_base + community->npins)
111 			return community;
112 	}
113 
114 	dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
115 	return NULL;
116 }
117 
118 static const struct intel_padgroup *
119 intel_community_get_padgroup(const struct intel_community *community,
120 			     unsigned int pin)
121 {
122 	int i;
123 
124 	for (i = 0; i < community->ngpps; i++) {
125 		const struct intel_padgroup *padgrp = &community->gpps[i];
126 
127 		if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
128 			return padgrp;
129 	}
130 
131 	return NULL;
132 }
133 
134 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
135 				      unsigned int pin, unsigned int reg)
136 {
137 	const struct intel_community *community;
138 	unsigned int padno;
139 	size_t nregs;
140 
141 	community = intel_get_community(pctrl, pin);
142 	if (!community)
143 		return NULL;
144 
145 	padno = pin_to_padno(community, pin);
146 	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
147 
148 	if (reg >= nregs * 4)
149 		return NULL;
150 
151 	return community->pad_regs + reg + padno * nregs * 4;
152 }
153 
154 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
155 {
156 	const struct intel_community *community;
157 	const struct intel_padgroup *padgrp;
158 	unsigned int gpp, offset, gpp_offset;
159 	void __iomem *padown;
160 
161 	community = intel_get_community(pctrl, pin);
162 	if (!community)
163 		return false;
164 	if (!community->padown_offset)
165 		return true;
166 
167 	padgrp = intel_community_get_padgroup(community, pin);
168 	if (!padgrp)
169 		return false;
170 
171 	gpp_offset = padgroup_offset(padgrp, pin);
172 	gpp = PADOWN_GPP(gpp_offset);
173 	offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
174 	padown = community->regs + offset;
175 
176 	return !(readl(padown) & PADOWN_MASK(gpp_offset));
177 }
178 
179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
180 {
181 	const struct intel_community *community;
182 	const struct intel_padgroup *padgrp;
183 	unsigned int offset, gpp_offset;
184 	void __iomem *hostown;
185 
186 	community = intel_get_community(pctrl, pin);
187 	if (!community)
188 		return true;
189 	if (!community->hostown_offset)
190 		return false;
191 
192 	padgrp = intel_community_get_padgroup(community, pin);
193 	if (!padgrp)
194 		return true;
195 
196 	gpp_offset = padgroup_offset(padgrp, pin);
197 	offset = community->hostown_offset + padgrp->reg_num * 4;
198 	hostown = community->regs + offset;
199 
200 	return !(readl(hostown) & BIT(gpp_offset));
201 }
202 
203 /**
204  * enum - Locking variants of the pad configuration
205  *
206  * @PAD_UNLOCKED:	pad is fully controlled by the configuration registers
207  * @PAD_LOCKED:		pad configuration registers, except TX state, are locked
208  * @PAD_LOCKED_TX:	pad configuration TX state is locked
209  * @PAD_LOCKED_FULL:	pad configuration registers are locked completely
210  *
211  * Locking is considered as read-only mode for corresponding registers and
212  * their respective fields. That said, TX state bit is locked separately from
213  * the main locking scheme.
214  */
215 enum {
216 	PAD_UNLOCKED	= 0,
217 	PAD_LOCKED	= 1,
218 	PAD_LOCKED_TX	= 2,
219 	PAD_LOCKED_FULL	= PAD_LOCKED | PAD_LOCKED_TX,
220 };
221 
222 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
223 {
224 	struct intel_community *community;
225 	const struct intel_padgroup *padgrp;
226 	unsigned int offset, gpp_offset;
227 	u32 value;
228 	int ret = PAD_UNLOCKED;
229 
230 	community = intel_get_community(pctrl, pin);
231 	if (!community)
232 		return PAD_LOCKED_FULL;
233 	if (!community->padcfglock_offset)
234 		return PAD_UNLOCKED;
235 
236 	padgrp = intel_community_get_padgroup(community, pin);
237 	if (!padgrp)
238 		return PAD_LOCKED_FULL;
239 
240 	gpp_offset = padgroup_offset(padgrp, pin);
241 
242 	/*
243 	 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
244 	 * the pad is considered unlocked. Any other case means that it is
245 	 * either fully or partially locked.
246 	 */
247 	offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
248 	value = readl(community->regs + offset);
249 	if (value & BIT(gpp_offset))
250 		ret |= PAD_LOCKED;
251 
252 	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
253 	value = readl(community->regs + offset);
254 	if (value & BIT(gpp_offset))
255 		ret |= PAD_LOCKED_TX;
256 
257 	return ret;
258 }
259 
260 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
261 {
262 	return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
263 }
264 
265 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
266 {
267 	return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
268 }
269 
270 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
271 {
272 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
273 
274 	return pctrl->soc->ngroups;
275 }
276 
277 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
278 				      unsigned int group)
279 {
280 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
281 
282 	return pctrl->soc->groups[group].name;
283 }
284 
285 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
286 			      const unsigned int **pins, unsigned int *npins)
287 {
288 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
289 
290 	*pins = pctrl->soc->groups[group].pins;
291 	*npins = pctrl->soc->groups[group].npins;
292 	return 0;
293 }
294 
295 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
296 			       unsigned int pin)
297 {
298 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
299 	void __iomem *padcfg;
300 	u32 cfg0, cfg1, mode;
301 	int locked;
302 	bool acpi;
303 
304 	if (!intel_pad_owned_by_host(pctrl, pin)) {
305 		seq_puts(s, "not available");
306 		return;
307 	}
308 
309 	cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
310 	cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
311 
312 	mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
313 	if (mode == PADCFG0_PMODE_GPIO)
314 		seq_puts(s, "GPIO ");
315 	else
316 		seq_printf(s, "mode %d ", mode);
317 
318 	seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
319 
320 	/* Dump the additional PADCFG registers if available */
321 	padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
322 	if (padcfg)
323 		seq_printf(s, " 0x%08x", readl(padcfg));
324 
325 	locked = intel_pad_locked(pctrl, pin);
326 	acpi = intel_pad_acpi_mode(pctrl, pin);
327 
328 	if (locked || acpi) {
329 		seq_puts(s, " [");
330 		if (locked)
331 			seq_puts(s, "LOCKED");
332 		if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
333 			seq_puts(s, " tx");
334 		else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
335 			seq_puts(s, " full");
336 
337 		if (locked && acpi)
338 			seq_puts(s, ", ");
339 
340 		if (acpi)
341 			seq_puts(s, "ACPI");
342 		seq_puts(s, "]");
343 	}
344 }
345 
346 static const struct pinctrl_ops intel_pinctrl_ops = {
347 	.get_groups_count = intel_get_groups_count,
348 	.get_group_name = intel_get_group_name,
349 	.get_group_pins = intel_get_group_pins,
350 	.pin_dbg_show = intel_pin_dbg_show,
351 };
352 
353 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
354 {
355 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
356 
357 	return pctrl->soc->nfunctions;
358 }
359 
360 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
361 					   unsigned int function)
362 {
363 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
364 
365 	return pctrl->soc->functions[function].name;
366 }
367 
368 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
369 				     unsigned int function,
370 				     const char * const **groups,
371 				     unsigned int * const ngroups)
372 {
373 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
374 
375 	*groups = pctrl->soc->functions[function].groups;
376 	*ngroups = pctrl->soc->functions[function].ngroups;
377 	return 0;
378 }
379 
380 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
381 				unsigned int function, unsigned int group)
382 {
383 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
384 	const struct intel_pingroup *grp = &pctrl->soc->groups[group];
385 	unsigned long flags;
386 	int i;
387 
388 	raw_spin_lock_irqsave(&pctrl->lock, flags);
389 
390 	/*
391 	 * All pins in the groups needs to be accessible and writable
392 	 * before we can enable the mux for this group.
393 	 */
394 	for (i = 0; i < grp->npins; i++) {
395 		if (!intel_pad_usable(pctrl, grp->pins[i])) {
396 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
397 			return -EBUSY;
398 		}
399 	}
400 
401 	/* Now enable the mux setting for each pin in the group */
402 	for (i = 0; i < grp->npins; i++) {
403 		void __iomem *padcfg0;
404 		u32 value;
405 
406 		padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
407 		value = readl(padcfg0);
408 
409 		value &= ~PADCFG0_PMODE_MASK;
410 
411 		if (grp->modes)
412 			value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
413 		else
414 			value |= grp->mode << PADCFG0_PMODE_SHIFT;
415 
416 		writel(value, padcfg0);
417 	}
418 
419 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
420 
421 	return 0;
422 }
423 
424 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
425 {
426 	u32 value;
427 
428 	value = readl(padcfg0);
429 	if (input) {
430 		value &= ~PADCFG0_GPIORXDIS;
431 		value |= PADCFG0_GPIOTXDIS;
432 	} else {
433 		value &= ~PADCFG0_GPIOTXDIS;
434 		value |= PADCFG0_GPIORXDIS;
435 	}
436 	writel(value, padcfg0);
437 }
438 
439 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
440 {
441 	return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
442 }
443 
444 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
445 {
446 	u32 value;
447 
448 	value = readl(padcfg0);
449 
450 	/* Put the pad into GPIO mode */
451 	value &= ~PADCFG0_PMODE_MASK;
452 	value |= PADCFG0_PMODE_GPIO;
453 
454 	/* Disable input and output buffers */
455 	value |= PADCFG0_GPIORXDIS;
456 	value |= PADCFG0_GPIOTXDIS;
457 
458 	/* Disable SCI/SMI/NMI generation */
459 	value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
460 	value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
461 
462 	writel(value, padcfg0);
463 }
464 
465 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
466 				     struct pinctrl_gpio_range *range,
467 				     unsigned int pin)
468 {
469 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
470 	void __iomem *padcfg0;
471 	unsigned long flags;
472 
473 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
474 
475 	raw_spin_lock_irqsave(&pctrl->lock, flags);
476 
477 	if (!intel_pad_owned_by_host(pctrl, pin)) {
478 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
479 		return -EBUSY;
480 	}
481 
482 	if (!intel_pad_is_unlocked(pctrl, pin)) {
483 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
484 		return 0;
485 	}
486 
487 	/*
488 	 * If pin is already configured in GPIO mode, we assume that
489 	 * firmware provides correct settings. In such case we avoid
490 	 * potential glitches on the pin. Otherwise, for the pin in
491 	 * alternative mode, consumer has to supply respective flags.
492 	 */
493 	if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
494 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
495 		return 0;
496 	}
497 
498 	intel_gpio_set_gpio_mode(padcfg0);
499 
500 	/* Disable TX buffer and enable RX (this will be input) */
501 	__intel_gpio_set_direction(padcfg0, true);
502 
503 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
504 
505 	return 0;
506 }
507 
508 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
509 				    struct pinctrl_gpio_range *range,
510 				    unsigned int pin, bool input)
511 {
512 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
513 	void __iomem *padcfg0;
514 	unsigned long flags;
515 
516 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
517 
518 	raw_spin_lock_irqsave(&pctrl->lock, flags);
519 	__intel_gpio_set_direction(padcfg0, input);
520 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
521 
522 	return 0;
523 }
524 
525 static const struct pinmux_ops intel_pinmux_ops = {
526 	.get_functions_count = intel_get_functions_count,
527 	.get_function_name = intel_get_function_name,
528 	.get_function_groups = intel_get_function_groups,
529 	.set_mux = intel_pinmux_set_mux,
530 	.gpio_request_enable = intel_gpio_request_enable,
531 	.gpio_set_direction = intel_gpio_set_direction,
532 };
533 
534 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
535 				 enum pin_config_param param, u32 *arg)
536 {
537 	const struct intel_community *community;
538 	void __iomem *padcfg1;
539 	unsigned long flags;
540 	u32 value, term;
541 
542 	community = intel_get_community(pctrl, pin);
543 	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
544 
545 	raw_spin_lock_irqsave(&pctrl->lock, flags);
546 	value = readl(padcfg1);
547 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
548 
549 	term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
550 
551 	switch (param) {
552 	case PIN_CONFIG_BIAS_DISABLE:
553 		if (term)
554 			return -EINVAL;
555 		break;
556 
557 	case PIN_CONFIG_BIAS_PULL_UP:
558 		if (!term || !(value & PADCFG1_TERM_UP))
559 			return -EINVAL;
560 
561 		switch (term) {
562 		case PADCFG1_TERM_833:
563 			*arg = 833;
564 			break;
565 		case PADCFG1_TERM_1K:
566 			*arg = 1000;
567 			break;
568 		case PADCFG1_TERM_5K:
569 			*arg = 5000;
570 			break;
571 		case PADCFG1_TERM_20K:
572 			*arg = 20000;
573 			break;
574 		}
575 
576 		break;
577 
578 	case PIN_CONFIG_BIAS_PULL_DOWN:
579 		if (!term || value & PADCFG1_TERM_UP)
580 			return -EINVAL;
581 
582 		switch (term) {
583 		case PADCFG1_TERM_833:
584 			if (!(community->features & PINCTRL_FEATURE_1K_PD))
585 				return -EINVAL;
586 			*arg = 833;
587 			break;
588 		case PADCFG1_TERM_1K:
589 			if (!(community->features & PINCTRL_FEATURE_1K_PD))
590 				return -EINVAL;
591 			*arg = 1000;
592 			break;
593 		case PADCFG1_TERM_5K:
594 			*arg = 5000;
595 			break;
596 		case PADCFG1_TERM_20K:
597 			*arg = 20000;
598 			break;
599 		}
600 
601 		break;
602 
603 	default:
604 		return -EINVAL;
605 	}
606 
607 	return 0;
608 }
609 
610 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
611 				     enum pin_config_param param, u32 *arg)
612 {
613 	void __iomem *padcfg2;
614 	unsigned long flags;
615 	unsigned long v;
616 	u32 value2;
617 
618 	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
619 	if (!padcfg2)
620 		return -ENOTSUPP;
621 
622 	raw_spin_lock_irqsave(&pctrl->lock, flags);
623 	value2 = readl(padcfg2);
624 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
625 	if (!(value2 & PADCFG2_DEBEN))
626 		return -EINVAL;
627 
628 	v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
629 	*arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
630 
631 	return 0;
632 }
633 
634 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
635 			    unsigned long *config)
636 {
637 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
638 	enum pin_config_param param = pinconf_to_config_param(*config);
639 	u32 arg = 0;
640 	int ret;
641 
642 	if (!intel_pad_owned_by_host(pctrl, pin))
643 		return -ENOTSUPP;
644 
645 	switch (param) {
646 	case PIN_CONFIG_BIAS_DISABLE:
647 	case PIN_CONFIG_BIAS_PULL_UP:
648 	case PIN_CONFIG_BIAS_PULL_DOWN:
649 		ret = intel_config_get_pull(pctrl, pin, param, &arg);
650 		if (ret)
651 			return ret;
652 		break;
653 
654 	case PIN_CONFIG_INPUT_DEBOUNCE:
655 		ret = intel_config_get_debounce(pctrl, pin, param, &arg);
656 		if (ret)
657 			return ret;
658 		break;
659 
660 	default:
661 		return -ENOTSUPP;
662 	}
663 
664 	*config = pinconf_to_config_packed(param, arg);
665 	return 0;
666 }
667 
668 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
669 				 unsigned long config)
670 {
671 	unsigned int param = pinconf_to_config_param(config);
672 	unsigned int arg = pinconf_to_config_argument(config);
673 	const struct intel_community *community;
674 	void __iomem *padcfg1;
675 	unsigned long flags;
676 	int ret = 0;
677 	u32 value;
678 
679 	community = intel_get_community(pctrl, pin);
680 	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
681 
682 	raw_spin_lock_irqsave(&pctrl->lock, flags);
683 
684 	value = readl(padcfg1);
685 
686 	switch (param) {
687 	case PIN_CONFIG_BIAS_DISABLE:
688 		value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
689 		break;
690 
691 	case PIN_CONFIG_BIAS_PULL_UP:
692 		value &= ~PADCFG1_TERM_MASK;
693 
694 		value |= PADCFG1_TERM_UP;
695 
696 		/* Set default strength value in case none is given */
697 		if (arg == 1)
698 			arg = 5000;
699 
700 		switch (arg) {
701 		case 20000:
702 			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
703 			break;
704 		case 5000:
705 			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
706 			break;
707 		case 1000:
708 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
709 			break;
710 		case 833:
711 			value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
712 			break;
713 		default:
714 			ret = -EINVAL;
715 		}
716 
717 		break;
718 
719 	case PIN_CONFIG_BIAS_PULL_DOWN:
720 		value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
721 
722 		/* Set default strength value in case none is given */
723 		if (arg == 1)
724 			arg = 5000;
725 
726 		switch (arg) {
727 		case 20000:
728 			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
729 			break;
730 		case 5000:
731 			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
732 			break;
733 		case 1000:
734 			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
735 				ret = -EINVAL;
736 				break;
737 			}
738 			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
739 			break;
740 		case 833:
741 			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
742 				ret = -EINVAL;
743 				break;
744 			}
745 			value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
746 			break;
747 		default:
748 			ret = -EINVAL;
749 		}
750 
751 		break;
752 	}
753 
754 	if (!ret)
755 		writel(value, padcfg1);
756 
757 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
758 
759 	return ret;
760 }
761 
762 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
763 				     unsigned int pin, unsigned int debounce)
764 {
765 	void __iomem *padcfg0, *padcfg2;
766 	unsigned long flags;
767 	u32 value0, value2;
768 
769 	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
770 	if (!padcfg2)
771 		return -ENOTSUPP;
772 
773 	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
774 
775 	raw_spin_lock_irqsave(&pctrl->lock, flags);
776 
777 	value0 = readl(padcfg0);
778 	value2 = readl(padcfg2);
779 
780 	/* Disable glitch filter and debouncer */
781 	value0 &= ~PADCFG0_PREGFRXSEL;
782 	value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
783 
784 	if (debounce) {
785 		unsigned long v;
786 
787 		v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
788 		if (v < 3 || v > 15) {
789 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
790 			return -EINVAL;
791 		}
792 
793 		/* Enable glitch filter and debouncer */
794 		value0 |= PADCFG0_PREGFRXSEL;
795 		value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
796 		value2 |= PADCFG2_DEBEN;
797 	}
798 
799 	writel(value0, padcfg0);
800 	writel(value2, padcfg2);
801 
802 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
803 
804 	return 0;
805 }
806 
807 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
808 			  unsigned long *configs, unsigned int nconfigs)
809 {
810 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
811 	int i, ret;
812 
813 	if (!intel_pad_usable(pctrl, pin))
814 		return -ENOTSUPP;
815 
816 	for (i = 0; i < nconfigs; i++) {
817 		switch (pinconf_to_config_param(configs[i])) {
818 		case PIN_CONFIG_BIAS_DISABLE:
819 		case PIN_CONFIG_BIAS_PULL_UP:
820 		case PIN_CONFIG_BIAS_PULL_DOWN:
821 			ret = intel_config_set_pull(pctrl, pin, configs[i]);
822 			if (ret)
823 				return ret;
824 			break;
825 
826 		case PIN_CONFIG_INPUT_DEBOUNCE:
827 			ret = intel_config_set_debounce(pctrl, pin,
828 				pinconf_to_config_argument(configs[i]));
829 			if (ret)
830 				return ret;
831 			break;
832 
833 		default:
834 			return -ENOTSUPP;
835 		}
836 	}
837 
838 	return 0;
839 }
840 
841 static const struct pinconf_ops intel_pinconf_ops = {
842 	.is_generic = true,
843 	.pin_config_get = intel_config_get,
844 	.pin_config_set = intel_config_set,
845 };
846 
847 static const struct pinctrl_desc intel_pinctrl_desc = {
848 	.pctlops = &intel_pinctrl_ops,
849 	.pmxops = &intel_pinmux_ops,
850 	.confops = &intel_pinconf_ops,
851 	.owner = THIS_MODULE,
852 };
853 
854 /**
855  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
856  * @pctrl: Pinctrl structure
857  * @offset: GPIO offset from gpiolib
858  * @community: Community is filled here if not %NULL
859  * @padgrp: Pad group is filled here if not %NULL
860  *
861  * When coming through gpiolib irqchip, the GPIO offset is not
862  * automatically translated to pinctrl pin number. This function can be
863  * used to find out the corresponding pinctrl pin.
864  */
865 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
866 			     const struct intel_community **community,
867 			     const struct intel_padgroup **padgrp)
868 {
869 	int i;
870 
871 	for (i = 0; i < pctrl->ncommunities; i++) {
872 		const struct intel_community *comm = &pctrl->communities[i];
873 		int j;
874 
875 		for (j = 0; j < comm->ngpps; j++) {
876 			const struct intel_padgroup *pgrp = &comm->gpps[j];
877 
878 			if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
879 				continue;
880 
881 			if (offset >= pgrp->gpio_base &&
882 			    offset < pgrp->gpio_base + pgrp->size) {
883 				int pin;
884 
885 				pin = pgrp->base + offset - pgrp->gpio_base;
886 				if (community)
887 					*community = comm;
888 				if (padgrp)
889 					*padgrp = pgrp;
890 
891 				return pin;
892 			}
893 		}
894 	}
895 
896 	return -EINVAL;
897 }
898 
899 /**
900  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
901  * @pctrl: Pinctrl structure
902  * @pin: pin number
903  *
904  * Translate the pin number of pinctrl to GPIO offset
905  */
906 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
907 {
908 	const struct intel_community *community;
909 	const struct intel_padgroup *padgrp;
910 
911 	community = intel_get_community(pctrl, pin);
912 	if (!community)
913 		return -EINVAL;
914 
915 	padgrp = intel_community_get_padgroup(community, pin);
916 	if (!padgrp)
917 		return -EINVAL;
918 
919 	return pin - padgrp->base + padgrp->gpio_base;
920 }
921 
922 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
923 {
924 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
925 	void __iomem *reg;
926 	u32 padcfg0;
927 	int pin;
928 
929 	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
930 	if (pin < 0)
931 		return -EINVAL;
932 
933 	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
934 	if (!reg)
935 		return -EINVAL;
936 
937 	padcfg0 = readl(reg);
938 	if (!(padcfg0 & PADCFG0_GPIOTXDIS))
939 		return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
940 
941 	return !!(padcfg0 & PADCFG0_GPIORXSTATE);
942 }
943 
944 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
945 			   int value)
946 {
947 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
948 	unsigned long flags;
949 	void __iomem *reg;
950 	u32 padcfg0;
951 	int pin;
952 
953 	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
954 	if (pin < 0)
955 		return;
956 
957 	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
958 	if (!reg)
959 		return;
960 
961 	raw_spin_lock_irqsave(&pctrl->lock, flags);
962 	padcfg0 = readl(reg);
963 	if (value)
964 		padcfg0 |= PADCFG0_GPIOTXSTATE;
965 	else
966 		padcfg0 &= ~PADCFG0_GPIOTXSTATE;
967 	writel(padcfg0, reg);
968 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
969 }
970 
971 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
972 {
973 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
974 	unsigned long flags;
975 	void __iomem *reg;
976 	u32 padcfg0;
977 	int pin;
978 
979 	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
980 	if (pin < 0)
981 		return -EINVAL;
982 
983 	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
984 	if (!reg)
985 		return -EINVAL;
986 
987 	raw_spin_lock_irqsave(&pctrl->lock, flags);
988 	padcfg0 = readl(reg);
989 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
990 	if (padcfg0 & PADCFG0_PMODE_MASK)
991 		return -EINVAL;
992 
993 	if (padcfg0 & PADCFG0_GPIOTXDIS)
994 		return GPIO_LINE_DIRECTION_IN;
995 
996 	return GPIO_LINE_DIRECTION_OUT;
997 }
998 
999 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1000 {
1001 	return pinctrl_gpio_direction_input(chip->base + offset);
1002 }
1003 
1004 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1005 				       int value)
1006 {
1007 	intel_gpio_set(chip, offset, value);
1008 	return pinctrl_gpio_direction_output(chip->base + offset);
1009 }
1010 
1011 static const struct gpio_chip intel_gpio_chip = {
1012 	.owner = THIS_MODULE,
1013 	.request = gpiochip_generic_request,
1014 	.free = gpiochip_generic_free,
1015 	.get_direction = intel_gpio_get_direction,
1016 	.direction_input = intel_gpio_direction_input,
1017 	.direction_output = intel_gpio_direction_output,
1018 	.get = intel_gpio_get,
1019 	.set = intel_gpio_set,
1020 	.set_config = gpiochip_generic_config,
1021 };
1022 
1023 static void intel_gpio_irq_ack(struct irq_data *d)
1024 {
1025 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1026 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1027 	const struct intel_community *community;
1028 	const struct intel_padgroup *padgrp;
1029 	int pin;
1030 
1031 	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1032 	if (pin >= 0) {
1033 		unsigned int gpp, gpp_offset, is_offset;
1034 
1035 		gpp = padgrp->reg_num;
1036 		gpp_offset = padgroup_offset(padgrp, pin);
1037 		is_offset = community->is_offset + gpp * 4;
1038 
1039 		raw_spin_lock(&pctrl->lock);
1040 		writel(BIT(gpp_offset), community->regs + is_offset);
1041 		raw_spin_unlock(&pctrl->lock);
1042 	}
1043 }
1044 
1045 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1046 {
1047 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1048 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1049 	const struct intel_community *community;
1050 	const struct intel_padgroup *padgrp;
1051 	int pin;
1052 
1053 	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1054 	if (pin >= 0) {
1055 		unsigned int gpp, gpp_offset;
1056 		unsigned long flags;
1057 		void __iomem *reg, *is;
1058 		u32 value;
1059 
1060 		gpp = padgrp->reg_num;
1061 		gpp_offset = padgroup_offset(padgrp, pin);
1062 
1063 		reg = community->regs + community->ie_offset + gpp * 4;
1064 		is = community->regs + community->is_offset + gpp * 4;
1065 
1066 		raw_spin_lock_irqsave(&pctrl->lock, flags);
1067 
1068 		/* Clear interrupt status first to avoid unexpected interrupt */
1069 		writel(BIT(gpp_offset), is);
1070 
1071 		value = readl(reg);
1072 		if (mask)
1073 			value &= ~BIT(gpp_offset);
1074 		else
1075 			value |= BIT(gpp_offset);
1076 		writel(value, reg);
1077 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1078 	}
1079 }
1080 
1081 static void intel_gpio_irq_mask(struct irq_data *d)
1082 {
1083 	intel_gpio_irq_mask_unmask(d, true);
1084 }
1085 
1086 static void intel_gpio_irq_unmask(struct irq_data *d)
1087 {
1088 	intel_gpio_irq_mask_unmask(d, false);
1089 }
1090 
1091 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1092 {
1093 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1095 	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1096 	unsigned long flags;
1097 	void __iomem *reg;
1098 	u32 value;
1099 
1100 	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1101 	if (!reg)
1102 		return -EINVAL;
1103 
1104 	/*
1105 	 * If the pin is in ACPI mode it is still usable as a GPIO but it
1106 	 * cannot be used as IRQ because GPI_IS status bit will not be
1107 	 * updated by the host controller hardware.
1108 	 */
1109 	if (intel_pad_acpi_mode(pctrl, pin)) {
1110 		dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1111 		return -EPERM;
1112 	}
1113 
1114 	raw_spin_lock_irqsave(&pctrl->lock, flags);
1115 
1116 	intel_gpio_set_gpio_mode(reg);
1117 
1118 	/* Disable TX buffer and enable RX (this will be input) */
1119 	__intel_gpio_set_direction(reg, true);
1120 
1121 	value = readl(reg);
1122 
1123 	value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1124 
1125 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1126 		value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1127 	} else if (type & IRQ_TYPE_EDGE_FALLING) {
1128 		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1129 		value |= PADCFG0_RXINV;
1130 	} else if (type & IRQ_TYPE_EDGE_RISING) {
1131 		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1132 	} else if (type & IRQ_TYPE_LEVEL_MASK) {
1133 		if (type & IRQ_TYPE_LEVEL_LOW)
1134 			value |= PADCFG0_RXINV;
1135 	} else {
1136 		value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1137 	}
1138 
1139 	writel(value, reg);
1140 
1141 	if (type & IRQ_TYPE_EDGE_BOTH)
1142 		irq_set_handler_locked(d, handle_edge_irq);
1143 	else if (type & IRQ_TYPE_LEVEL_MASK)
1144 		irq_set_handler_locked(d, handle_level_irq);
1145 
1146 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1147 
1148 	return 0;
1149 }
1150 
1151 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1152 {
1153 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1154 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1155 	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1156 
1157 	if (on)
1158 		enable_irq_wake(pctrl->irq);
1159 	else
1160 		disable_irq_wake(pctrl->irq);
1161 
1162 	dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1163 	return 0;
1164 }
1165 
1166 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1167 					    const struct intel_community *community)
1168 {
1169 	struct gpio_chip *gc = &pctrl->chip;
1170 	unsigned int gpp;
1171 	int ret = 0;
1172 
1173 	for (gpp = 0; gpp < community->ngpps; gpp++) {
1174 		const struct intel_padgroup *padgrp = &community->gpps[gpp];
1175 		unsigned long pending, enabled, gpp_offset;
1176 
1177 		raw_spin_lock(&pctrl->lock);
1178 
1179 		pending = readl(community->regs + community->is_offset +
1180 				padgrp->reg_num * 4);
1181 		enabled = readl(community->regs + community->ie_offset +
1182 				padgrp->reg_num * 4);
1183 
1184 		raw_spin_unlock(&pctrl->lock);
1185 
1186 		/* Only interrupts that are enabled */
1187 		pending &= enabled;
1188 
1189 		for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1190 			unsigned int irq;
1191 
1192 			irq = irq_find_mapping(gc->irq.domain,
1193 					       padgrp->gpio_base + gpp_offset);
1194 			generic_handle_irq(irq);
1195 		}
1196 
1197 		ret += pending ? 1 : 0;
1198 	}
1199 
1200 	return ret;
1201 }
1202 
1203 static irqreturn_t intel_gpio_irq(int irq, void *data)
1204 {
1205 	const struct intel_community *community;
1206 	struct intel_pinctrl *pctrl = data;
1207 	unsigned int i;
1208 	int ret = 0;
1209 
1210 	/* Need to check all communities for pending interrupts */
1211 	for (i = 0; i < pctrl->ncommunities; i++) {
1212 		community = &pctrl->communities[i];
1213 		ret += intel_gpio_community_irq_handler(pctrl, community);
1214 	}
1215 
1216 	return IRQ_RETVAL(ret);
1217 }
1218 
1219 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1220 				const struct intel_community *community)
1221 {
1222 	int ret = 0, i;
1223 
1224 	for (i = 0; i < community->ngpps; i++) {
1225 		const struct intel_padgroup *gpp = &community->gpps[i];
1226 
1227 		if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1228 			continue;
1229 
1230 		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1231 					     gpp->gpio_base, gpp->base,
1232 					     gpp->size);
1233 		if (ret)
1234 			return ret;
1235 	}
1236 
1237 	return ret;
1238 }
1239 
1240 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1241 {
1242 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1243 	int ret, i;
1244 
1245 	for (i = 0; i < pctrl->ncommunities; i++) {
1246 		struct intel_community *community = &pctrl->communities[i];
1247 
1248 		ret = intel_gpio_add_community_ranges(pctrl, community);
1249 		if (ret) {
1250 			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1251 			return ret;
1252 		}
1253 	}
1254 
1255 	return 0;
1256 }
1257 
1258 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1259 {
1260 	const struct intel_community *community;
1261 	unsigned int ngpio = 0;
1262 	int i, j;
1263 
1264 	for (i = 0; i < pctrl->ncommunities; i++) {
1265 		community = &pctrl->communities[i];
1266 		for (j = 0; j < community->ngpps; j++) {
1267 			const struct intel_padgroup *gpp = &community->gpps[j];
1268 
1269 			if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1270 				continue;
1271 
1272 			if (gpp->gpio_base + gpp->size > ngpio)
1273 				ngpio = gpp->gpio_base + gpp->size;
1274 		}
1275 	}
1276 
1277 	return ngpio;
1278 }
1279 
1280 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1281 {
1282 	int ret;
1283 	struct gpio_irq_chip *girq;
1284 
1285 	pctrl->chip = intel_gpio_chip;
1286 
1287 	/* Setup GPIO chip */
1288 	pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1289 	pctrl->chip.label = dev_name(pctrl->dev);
1290 	pctrl->chip.parent = pctrl->dev;
1291 	pctrl->chip.base = -1;
1292 	pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1293 	pctrl->irq = irq;
1294 
1295 	/* Setup IRQ chip */
1296 	pctrl->irqchip.name = dev_name(pctrl->dev);
1297 	pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1298 	pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1299 	pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1300 	pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1301 	pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1302 	pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1303 
1304 	/*
1305 	 * On some platforms several GPIO controllers share the same interrupt
1306 	 * line.
1307 	 */
1308 	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1309 			       IRQF_SHARED | IRQF_NO_THREAD,
1310 			       dev_name(pctrl->dev), pctrl);
1311 	if (ret) {
1312 		dev_err(pctrl->dev, "failed to request interrupt\n");
1313 		return ret;
1314 	}
1315 
1316 	girq = &pctrl->chip.irq;
1317 	girq->chip = &pctrl->irqchip;
1318 	/* This will let us handle the IRQ in the driver */
1319 	girq->parent_handler = NULL;
1320 	girq->num_parents = 0;
1321 	girq->default_type = IRQ_TYPE_NONE;
1322 	girq->handler = handle_bad_irq;
1323 
1324 	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1325 	if (ret) {
1326 		dev_err(pctrl->dev, "failed to register gpiochip\n");
1327 		return ret;
1328 	}
1329 
1330 	return 0;
1331 }
1332 
1333 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1334 					       struct intel_community *community)
1335 {
1336 	struct intel_padgroup *gpps;
1337 	unsigned int padown_num = 0;
1338 	size_t i, ngpps = community->ngpps;
1339 
1340 	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1341 	if (!gpps)
1342 		return -ENOMEM;
1343 
1344 	for (i = 0; i < ngpps; i++) {
1345 		gpps[i] = community->gpps[i];
1346 
1347 		if (gpps[i].size > 32)
1348 			return -EINVAL;
1349 
1350 		/* Special treatment for GPIO base */
1351 		switch (gpps[i].gpio_base) {
1352 			case INTEL_GPIO_BASE_MATCH:
1353 				gpps[i].gpio_base = gpps[i].base;
1354 				break;
1355 			case INTEL_GPIO_BASE_ZERO:
1356 				gpps[i].gpio_base = 0;
1357 				break;
1358 			case INTEL_GPIO_BASE_NOMAP:
1359 				break;
1360 			default:
1361 				break;
1362 		}
1363 
1364 		gpps[i].padown_num = padown_num;
1365 		padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1366 	}
1367 
1368 	community->gpps = gpps;
1369 
1370 	return 0;
1371 }
1372 
1373 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1374 					       struct intel_community *community)
1375 {
1376 	struct intel_padgroup *gpps;
1377 	unsigned int npins = community->npins;
1378 	unsigned int padown_num = 0;
1379 	size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1380 
1381 	if (community->gpp_size > 32)
1382 		return -EINVAL;
1383 
1384 	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1385 	if (!gpps)
1386 		return -ENOMEM;
1387 
1388 	for (i = 0; i < ngpps; i++) {
1389 		unsigned int gpp_size = community->gpp_size;
1390 
1391 		gpps[i].reg_num = i;
1392 		gpps[i].base = community->pin_base + i * gpp_size;
1393 		gpps[i].size = min(gpp_size, npins);
1394 		npins -= gpps[i].size;
1395 
1396 		gpps[i].gpio_base = gpps[i].base;
1397 		gpps[i].padown_num = padown_num;
1398 
1399 		/*
1400 		 * In older hardware the number of padown registers per
1401 		 * group is fixed regardless of the group size.
1402 		 */
1403 		if (community->gpp_num_padown_regs)
1404 			padown_num += community->gpp_num_padown_regs;
1405 		else
1406 			padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1407 	}
1408 
1409 	community->ngpps = ngpps;
1410 	community->gpps = gpps;
1411 
1412 	return 0;
1413 }
1414 
1415 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1416 {
1417 #ifdef CONFIG_PM_SLEEP
1418 	const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1419 	struct intel_community_context *communities;
1420 	struct intel_pad_context *pads;
1421 	int i;
1422 
1423 	pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1424 	if (!pads)
1425 		return -ENOMEM;
1426 
1427 	communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1428 				   sizeof(*communities), GFP_KERNEL);
1429 	if (!communities)
1430 		return -ENOMEM;
1431 
1432 
1433 	for (i = 0; i < pctrl->ncommunities; i++) {
1434 		struct intel_community *community = &pctrl->communities[i];
1435 		u32 *intmask, *hostown;
1436 
1437 		intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1438 				       sizeof(*intmask), GFP_KERNEL);
1439 		if (!intmask)
1440 			return -ENOMEM;
1441 
1442 		communities[i].intmask = intmask;
1443 
1444 		hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1445 				       sizeof(*hostown), GFP_KERNEL);
1446 		if (!hostown)
1447 			return -ENOMEM;
1448 
1449 		communities[i].hostown = hostown;
1450 	}
1451 
1452 	pctrl->context.pads = pads;
1453 	pctrl->context.communities = communities;
1454 #endif
1455 
1456 	return 0;
1457 }
1458 
1459 static int intel_pinctrl_probe(struct platform_device *pdev,
1460 			       const struct intel_pinctrl_soc_data *soc_data)
1461 {
1462 	struct intel_pinctrl *pctrl;
1463 	int i, ret, irq;
1464 
1465 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1466 	if (!pctrl)
1467 		return -ENOMEM;
1468 
1469 	pctrl->dev = &pdev->dev;
1470 	pctrl->soc = soc_data;
1471 	raw_spin_lock_init(&pctrl->lock);
1472 
1473 	/*
1474 	 * Make a copy of the communities which we can use to hold pointers
1475 	 * to the registers.
1476 	 */
1477 	pctrl->ncommunities = pctrl->soc->ncommunities;
1478 	pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1479 				  sizeof(*pctrl->communities), GFP_KERNEL);
1480 	if (!pctrl->communities)
1481 		return -ENOMEM;
1482 
1483 	for (i = 0; i < pctrl->ncommunities; i++) {
1484 		struct intel_community *community = &pctrl->communities[i];
1485 		void __iomem *regs;
1486 		u32 offset;
1487 		u32 value;
1488 
1489 		*community = pctrl->soc->communities[i];
1490 
1491 		regs = devm_platform_ioremap_resource(pdev, community->barno);
1492 		if (IS_ERR(regs))
1493 			return PTR_ERR(regs);
1494 
1495 		/*
1496 		 * Determine community features based on the revision.
1497 		 * A value of all ones means the device is not present.
1498 		 */
1499 		value = readl(regs + REVID);
1500 		if (value == ~0u)
1501 			return -ENODEV;
1502 		if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1503 			community->features |= PINCTRL_FEATURE_DEBOUNCE;
1504 			community->features |= PINCTRL_FEATURE_1K_PD;
1505 		}
1506 
1507 		/* Determine community features based on the capabilities */
1508 		offset = CAPLIST;
1509 		do {
1510 			value = readl(regs + offset);
1511 			switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1512 			case CAPLIST_ID_GPIO_HW_INFO:
1513 				community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1514 				break;
1515 			case CAPLIST_ID_PWM:
1516 				community->features |= PINCTRL_FEATURE_PWM;
1517 				break;
1518 			case CAPLIST_ID_BLINK:
1519 				community->features |= PINCTRL_FEATURE_BLINK;
1520 				break;
1521 			case CAPLIST_ID_EXP:
1522 				community->features |= PINCTRL_FEATURE_EXP;
1523 				break;
1524 			default:
1525 				break;
1526 			}
1527 			offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1528 		} while (offset);
1529 
1530 		dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1531 
1532 		/* Read offset of the pad configuration registers */
1533 		offset = readl(regs + PADBAR);
1534 
1535 		community->regs = regs;
1536 		community->pad_regs = regs + offset;
1537 
1538 		if (community->gpps)
1539 			ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1540 		else
1541 			ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1542 		if (ret)
1543 			return ret;
1544 	}
1545 
1546 	irq = platform_get_irq(pdev, 0);
1547 	if (irq < 0)
1548 		return irq;
1549 
1550 	ret = intel_pinctrl_pm_init(pctrl);
1551 	if (ret)
1552 		return ret;
1553 
1554 	pctrl->pctldesc = intel_pinctrl_desc;
1555 	pctrl->pctldesc.name = dev_name(&pdev->dev);
1556 	pctrl->pctldesc.pins = pctrl->soc->pins;
1557 	pctrl->pctldesc.npins = pctrl->soc->npins;
1558 
1559 	pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1560 					       pctrl);
1561 	if (IS_ERR(pctrl->pctldev)) {
1562 		dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1563 		return PTR_ERR(pctrl->pctldev);
1564 	}
1565 
1566 	ret = intel_gpio_probe(pctrl, irq);
1567 	if (ret)
1568 		return ret;
1569 
1570 	platform_set_drvdata(pdev, pctrl);
1571 
1572 	return 0;
1573 }
1574 
1575 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1576 {
1577 	const struct intel_pinctrl_soc_data *data;
1578 
1579 	data = device_get_match_data(&pdev->dev);
1580 	if (!data)
1581 		return -ENODATA;
1582 
1583 	return intel_pinctrl_probe(pdev, data);
1584 }
1585 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1586 
1587 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1588 {
1589 	const struct intel_pinctrl_soc_data *data;
1590 
1591 	data = intel_pinctrl_get_soc_data(pdev);
1592 	if (IS_ERR(data))
1593 		return PTR_ERR(data);
1594 
1595 	return intel_pinctrl_probe(pdev, data);
1596 }
1597 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1598 
1599 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1600 {
1601 	const struct intel_pinctrl_soc_data *data = NULL;
1602 	const struct intel_pinctrl_soc_data **table;
1603 	struct acpi_device *adev;
1604 	unsigned int i;
1605 
1606 	adev = ACPI_COMPANION(&pdev->dev);
1607 	if (adev) {
1608 		const void *match = device_get_match_data(&pdev->dev);
1609 
1610 		table = (const struct intel_pinctrl_soc_data **)match;
1611 		for (i = 0; table[i]; i++) {
1612 			if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1613 				data = table[i];
1614 				break;
1615 			}
1616 		}
1617 	} else {
1618 		const struct platform_device_id *id;
1619 
1620 		id = platform_get_device_id(pdev);
1621 		if (!id)
1622 			return ERR_PTR(-ENODEV);
1623 
1624 		table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1625 		data = table[pdev->id];
1626 	}
1627 
1628 	return data ?: ERR_PTR(-ENODATA);
1629 }
1630 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1631 
1632 #ifdef CONFIG_PM_SLEEP
1633 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1634 {
1635 	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1636 
1637 	if (!pd || !intel_pad_usable(pctrl, pin))
1638 		return false;
1639 
1640 	/*
1641 	 * Only restore the pin if it is actually in use by the kernel (or
1642 	 * by userspace). It is possible that some pins are used by the
1643 	 * BIOS during resume and those are not always locked down so leave
1644 	 * them alone.
1645 	 */
1646 	if (pd->mux_owner || pd->gpio_owner ||
1647 	    gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1648 		return true;
1649 
1650 	return false;
1651 }
1652 
1653 int intel_pinctrl_suspend_noirq(struct device *dev)
1654 {
1655 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1656 	struct intel_community_context *communities;
1657 	struct intel_pad_context *pads;
1658 	int i;
1659 
1660 	pads = pctrl->context.pads;
1661 	for (i = 0; i < pctrl->soc->npins; i++) {
1662 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1663 		void __iomem *padcfg;
1664 		u32 val;
1665 
1666 		if (!intel_pinctrl_should_save(pctrl, desc->number))
1667 			continue;
1668 
1669 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1670 		pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1671 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1672 		pads[i].padcfg1 = val;
1673 
1674 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1675 		if (padcfg)
1676 			pads[i].padcfg2 = readl(padcfg);
1677 	}
1678 
1679 	communities = pctrl->context.communities;
1680 	for (i = 0; i < pctrl->ncommunities; i++) {
1681 		struct intel_community *community = &pctrl->communities[i];
1682 		void __iomem *base;
1683 		unsigned int gpp;
1684 
1685 		base = community->regs + community->ie_offset;
1686 		for (gpp = 0; gpp < community->ngpps; gpp++)
1687 			communities[i].intmask[gpp] = readl(base + gpp * 4);
1688 
1689 		base = community->regs + community->hostown_offset;
1690 		for (gpp = 0; gpp < community->ngpps; gpp++)
1691 			communities[i].hostown[gpp] = readl(base + gpp * 4);
1692 	}
1693 
1694 	return 0;
1695 }
1696 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1697 
1698 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1699 {
1700 	size_t i;
1701 
1702 	for (i = 0; i < pctrl->ncommunities; i++) {
1703 		const struct intel_community *community;
1704 		void __iomem *base;
1705 		unsigned int gpp;
1706 
1707 		community = &pctrl->communities[i];
1708 		base = community->regs;
1709 
1710 		for (gpp = 0; gpp < community->ngpps; gpp++) {
1711 			/* Mask and clear all interrupts */
1712 			writel(0, base + community->ie_offset + gpp * 4);
1713 			writel(0xffff, base + community->is_offset + gpp * 4);
1714 		}
1715 	}
1716 }
1717 
1718 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1719 {
1720 	u32 curr, updated;
1721 
1722 	curr = readl(reg);
1723 
1724 	updated = (curr & ~mask) | (value & mask);
1725 	if (curr == updated)
1726 		return false;
1727 
1728 	writel(updated, reg);
1729 	return true;
1730 }
1731 
1732 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1733 				  void __iomem *base, unsigned int gpp, u32 saved)
1734 {
1735 	const struct intel_community *community = &pctrl->communities[c];
1736 	const struct intel_padgroup *padgrp = &community->gpps[gpp];
1737 	struct device *dev = pctrl->dev;
1738 	const char *dummy;
1739 	u32 requested = 0;
1740 	unsigned int i;
1741 
1742 	if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1743 		return;
1744 
1745 	for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1746 		requested |= BIT(i);
1747 
1748 	if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1749 		return;
1750 
1751 	dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1752 }
1753 
1754 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1755 				  void __iomem *base, unsigned int gpp, u32 saved)
1756 {
1757 	struct device *dev = pctrl->dev;
1758 
1759 	if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1760 		return;
1761 
1762 	dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1763 }
1764 
1765 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1766 				 unsigned int reg, u32 saved)
1767 {
1768 	u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1769 	unsigned int n = reg / sizeof(u32);
1770 	struct device *dev = pctrl->dev;
1771 	void __iomem *padcfg;
1772 
1773 	padcfg = intel_get_padcfg(pctrl, pin, reg);
1774 	if (!padcfg)
1775 		return;
1776 
1777 	if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1778 		return;
1779 
1780 	dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1781 }
1782 
1783 int intel_pinctrl_resume_noirq(struct device *dev)
1784 {
1785 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1786 	const struct intel_community_context *communities;
1787 	const struct intel_pad_context *pads;
1788 	int i;
1789 
1790 	/* Mask all interrupts */
1791 	intel_gpio_irq_init(pctrl);
1792 
1793 	pads = pctrl->context.pads;
1794 	for (i = 0; i < pctrl->soc->npins; i++) {
1795 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1796 
1797 		if (!intel_pinctrl_should_save(pctrl, desc->number))
1798 			continue;
1799 
1800 		intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1801 		intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1802 		intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1803 	}
1804 
1805 	communities = pctrl->context.communities;
1806 	for (i = 0; i < pctrl->ncommunities; i++) {
1807 		struct intel_community *community = &pctrl->communities[i];
1808 		void __iomem *base;
1809 		unsigned int gpp;
1810 
1811 		base = community->regs + community->ie_offset;
1812 		for (gpp = 0; gpp < community->ngpps; gpp++)
1813 			intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1814 
1815 		base = community->regs + community->hostown_offset;
1816 		for (gpp = 0; gpp < community->ngpps; gpp++)
1817 			intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1818 	}
1819 
1820 	return 0;
1821 }
1822 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1823 #endif
1824 
1825 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1826 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1827 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1828 MODULE_LICENSE("GPL v2");
1829