1 /* 2 * Intel pinctrl/GPIO core driver. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 6 * Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/platform_device.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 22 #include "pinctrl-intel.h" 23 24 /* Offset from regs */ 25 #define PADBAR 0x00c 26 #define GPI_IS 0x100 27 #define GPI_GPE_STS 0x140 28 #define GPI_GPE_EN 0x160 29 30 #define PADOWN_BITS 4 31 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 32 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 33 #define PADOWN_GPP(p) ((p) / 8) 34 35 /* Offset from pad_regs */ 36 #define PADCFG0 0x000 37 #define PADCFG0_RXEVCFG_SHIFT 25 38 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 39 #define PADCFG0_RXEVCFG_LEVEL 0 40 #define PADCFG0_RXEVCFG_EDGE 1 41 #define PADCFG0_RXEVCFG_DISABLED 2 42 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 43 #define PADCFG0_RXINV BIT(23) 44 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 45 #define PADCFG0_GPIROUTSCI BIT(19) 46 #define PADCFG0_GPIROUTSMI BIT(18) 47 #define PADCFG0_GPIROUTNMI BIT(17) 48 #define PADCFG0_PMODE_SHIFT 10 49 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 50 #define PADCFG0_GPIORXDIS BIT(9) 51 #define PADCFG0_GPIOTXDIS BIT(8) 52 #define PADCFG0_GPIORXSTATE BIT(1) 53 #define PADCFG0_GPIOTXSTATE BIT(0) 54 55 #define PADCFG1 0x004 56 #define PADCFG1_TERM_UP BIT(13) 57 #define PADCFG1_TERM_SHIFT 10 58 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 59 #define PADCFG1_TERM_20K 4 60 #define PADCFG1_TERM_2K 3 61 #define PADCFG1_TERM_5K 2 62 #define PADCFG1_TERM_1K 1 63 64 struct intel_pad_context { 65 u32 padcfg0; 66 u32 padcfg1; 67 }; 68 69 struct intel_community_context { 70 u32 *intmask; 71 }; 72 73 struct intel_pinctrl_context { 74 struct intel_pad_context *pads; 75 struct intel_community_context *communities; 76 }; 77 78 /** 79 * struct intel_pinctrl - Intel pinctrl private structure 80 * @dev: Pointer to the device structure 81 * @lock: Lock to serialize register access 82 * @pctldesc: Pin controller description 83 * @pctldev: Pointer to the pin controller device 84 * @chip: GPIO chip in this pin controller 85 * @soc: SoC/PCH specific pin configuration data 86 * @communities: All communities in this pin controller 87 * @ncommunities: Number of communities in this pin controller 88 * @context: Configuration saved over system sleep 89 */ 90 struct intel_pinctrl { 91 struct device *dev; 92 spinlock_t lock; 93 struct pinctrl_desc pctldesc; 94 struct pinctrl_dev *pctldev; 95 struct gpio_chip chip; 96 const struct intel_pinctrl_soc_data *soc; 97 struct intel_community *communities; 98 size_t ncommunities; 99 struct intel_pinctrl_context context; 100 }; 101 102 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 103 104 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 105 unsigned pin) 106 { 107 struct intel_community *community; 108 int i; 109 110 for (i = 0; i < pctrl->ncommunities; i++) { 111 community = &pctrl->communities[i]; 112 if (pin >= community->pin_base && 113 pin < community->pin_base + community->npins) 114 return community; 115 } 116 117 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 118 return NULL; 119 } 120 121 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, 122 unsigned reg) 123 { 124 const struct intel_community *community; 125 unsigned padno; 126 127 community = intel_get_community(pctrl, pin); 128 if (!community) 129 return NULL; 130 131 padno = pin_to_padno(community, pin); 132 return community->pad_regs + reg + padno * 8; 133 } 134 135 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) 136 { 137 const struct intel_community *community; 138 unsigned padno, gpp, offset, group; 139 void __iomem *padown; 140 141 community = intel_get_community(pctrl, pin); 142 if (!community) 143 return false; 144 if (!community->padown_offset) 145 return true; 146 147 padno = pin_to_padno(community, pin); 148 group = padno / community->gpp_size; 149 gpp = PADOWN_GPP(padno % community->gpp_size); 150 offset = community->padown_offset + 0x10 * group + gpp * 4; 151 padown = community->regs + offset; 152 153 return !(readl(padown) & PADOWN_MASK(padno)); 154 } 155 156 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) 157 { 158 const struct intel_community *community; 159 unsigned padno, gpp, offset; 160 void __iomem *hostown; 161 162 community = intel_get_community(pctrl, pin); 163 if (!community) 164 return true; 165 if (!community->hostown_offset) 166 return false; 167 168 padno = pin_to_padno(community, pin); 169 gpp = padno / community->gpp_size; 170 offset = community->hostown_offset + gpp * 4; 171 hostown = community->regs + offset; 172 173 return !(readl(hostown) & BIT(padno % community->gpp_size)); 174 } 175 176 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) 177 { 178 struct intel_community *community; 179 unsigned padno, gpp, offset; 180 u32 value; 181 182 community = intel_get_community(pctrl, pin); 183 if (!community) 184 return true; 185 if (!community->padcfglock_offset) 186 return false; 187 188 padno = pin_to_padno(community, pin); 189 gpp = padno / community->gpp_size; 190 191 /* 192 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 193 * the pad is considered unlocked. Any other case means that it is 194 * either fully or partially locked and we don't touch it. 195 */ 196 offset = community->padcfglock_offset + gpp * 8; 197 value = readl(community->regs + offset); 198 if (value & BIT(pin % community->gpp_size)) 199 return true; 200 201 offset = community->padcfglock_offset + 4 + gpp * 8; 202 value = readl(community->regs + offset); 203 if (value & BIT(pin % community->gpp_size)) 204 return true; 205 206 return false; 207 } 208 209 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 210 { 211 return intel_pad_owned_by_host(pctrl, pin) && 212 !intel_pad_locked(pctrl, pin); 213 } 214 215 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 216 { 217 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 218 219 return pctrl->soc->ngroups; 220 } 221 222 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 223 unsigned group) 224 { 225 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 226 227 return pctrl->soc->groups[group].name; 228 } 229 230 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 231 const unsigned **pins, unsigned *npins) 232 { 233 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 234 235 *pins = pctrl->soc->groups[group].pins; 236 *npins = pctrl->soc->groups[group].npins; 237 return 0; 238 } 239 240 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 241 unsigned pin) 242 { 243 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 244 u32 cfg0, cfg1, mode; 245 bool locked, acpi; 246 247 if (!intel_pad_owned_by_host(pctrl, pin)) { 248 seq_puts(s, "not available"); 249 return; 250 } 251 252 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 253 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 254 255 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 256 if (!mode) 257 seq_puts(s, "GPIO "); 258 else 259 seq_printf(s, "mode %d ", mode); 260 261 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 262 263 locked = intel_pad_locked(pctrl, pin); 264 acpi = intel_pad_acpi_mode(pctrl, pin); 265 266 if (locked || acpi) { 267 seq_puts(s, " ["); 268 if (locked) { 269 seq_puts(s, "LOCKED"); 270 if (acpi) 271 seq_puts(s, ", "); 272 } 273 if (acpi) 274 seq_puts(s, "ACPI"); 275 seq_puts(s, "]"); 276 } 277 } 278 279 static const struct pinctrl_ops intel_pinctrl_ops = { 280 .get_groups_count = intel_get_groups_count, 281 .get_group_name = intel_get_group_name, 282 .get_group_pins = intel_get_group_pins, 283 .pin_dbg_show = intel_pin_dbg_show, 284 }; 285 286 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 287 { 288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 289 290 return pctrl->soc->nfunctions; 291 } 292 293 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 294 unsigned function) 295 { 296 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 297 298 return pctrl->soc->functions[function].name; 299 } 300 301 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 302 unsigned function, 303 const char * const **groups, 304 unsigned * const ngroups) 305 { 306 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 307 308 *groups = pctrl->soc->functions[function].groups; 309 *ngroups = pctrl->soc->functions[function].ngroups; 310 return 0; 311 } 312 313 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 314 unsigned group) 315 { 316 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 317 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 318 unsigned long flags; 319 int i; 320 321 spin_lock_irqsave(&pctrl->lock, flags); 322 323 /* 324 * All pins in the groups needs to be accessible and writable 325 * before we can enable the mux for this group. 326 */ 327 for (i = 0; i < grp->npins; i++) { 328 if (!intel_pad_usable(pctrl, grp->pins[i])) { 329 spin_unlock_irqrestore(&pctrl->lock, flags); 330 return -EBUSY; 331 } 332 } 333 334 /* Now enable the mux setting for each pin in the group */ 335 for (i = 0; i < grp->npins; i++) { 336 void __iomem *padcfg0; 337 u32 value; 338 339 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 340 value = readl(padcfg0); 341 342 value &= ~PADCFG0_PMODE_MASK; 343 value |= grp->mode << PADCFG0_PMODE_SHIFT; 344 345 writel(value, padcfg0); 346 } 347 348 spin_unlock_irqrestore(&pctrl->lock, flags); 349 350 return 0; 351 } 352 353 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 354 struct pinctrl_gpio_range *range, 355 unsigned pin) 356 { 357 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 358 void __iomem *padcfg0; 359 unsigned long flags; 360 u32 value; 361 362 spin_lock_irqsave(&pctrl->lock, flags); 363 364 if (!intel_pad_usable(pctrl, pin)) { 365 spin_unlock_irqrestore(&pctrl->lock, flags); 366 return -EBUSY; 367 } 368 369 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 370 /* Put the pad into GPIO mode */ 371 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 372 /* Disable SCI/SMI/NMI generation */ 373 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 374 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 375 /* Disable TX buffer and enable RX (this will be input) */ 376 value &= ~PADCFG0_GPIORXDIS; 377 value |= PADCFG0_GPIOTXDIS; 378 writel(value, padcfg0); 379 380 spin_unlock_irqrestore(&pctrl->lock, flags); 381 382 return 0; 383 } 384 385 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 386 struct pinctrl_gpio_range *range, 387 unsigned pin, bool input) 388 { 389 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 390 void __iomem *padcfg0; 391 unsigned long flags; 392 u32 value; 393 394 spin_lock_irqsave(&pctrl->lock, flags); 395 396 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 397 398 value = readl(padcfg0); 399 if (input) 400 value |= PADCFG0_GPIOTXDIS; 401 else 402 value &= ~PADCFG0_GPIOTXDIS; 403 writel(value, padcfg0); 404 405 spin_unlock_irqrestore(&pctrl->lock, flags); 406 407 return 0; 408 } 409 410 static const struct pinmux_ops intel_pinmux_ops = { 411 .get_functions_count = intel_get_functions_count, 412 .get_function_name = intel_get_function_name, 413 .get_function_groups = intel_get_function_groups, 414 .set_mux = intel_pinmux_set_mux, 415 .gpio_request_enable = intel_gpio_request_enable, 416 .gpio_set_direction = intel_gpio_set_direction, 417 }; 418 419 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, 420 unsigned long *config) 421 { 422 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 423 enum pin_config_param param = pinconf_to_config_param(*config); 424 u32 value, term; 425 u16 arg = 0; 426 427 if (!intel_pad_owned_by_host(pctrl, pin)) 428 return -ENOTSUPP; 429 430 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 431 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 432 433 switch (param) { 434 case PIN_CONFIG_BIAS_DISABLE: 435 if (term) 436 return -EINVAL; 437 break; 438 439 case PIN_CONFIG_BIAS_PULL_UP: 440 if (!term || !(value & PADCFG1_TERM_UP)) 441 return -EINVAL; 442 443 switch (term) { 444 case PADCFG1_TERM_1K: 445 arg = 1000; 446 break; 447 case PADCFG1_TERM_2K: 448 arg = 2000; 449 break; 450 case PADCFG1_TERM_5K: 451 arg = 5000; 452 break; 453 case PADCFG1_TERM_20K: 454 arg = 20000; 455 break; 456 } 457 458 break; 459 460 case PIN_CONFIG_BIAS_PULL_DOWN: 461 if (!term || value & PADCFG1_TERM_UP) 462 return -EINVAL; 463 464 switch (term) { 465 case PADCFG1_TERM_5K: 466 arg = 5000; 467 break; 468 case PADCFG1_TERM_20K: 469 arg = 20000; 470 break; 471 } 472 473 break; 474 475 default: 476 return -ENOTSUPP; 477 } 478 479 *config = pinconf_to_config_packed(param, arg); 480 return 0; 481 } 482 483 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, 484 unsigned long config) 485 { 486 unsigned param = pinconf_to_config_param(config); 487 unsigned arg = pinconf_to_config_argument(config); 488 void __iomem *padcfg1; 489 unsigned long flags; 490 int ret = 0; 491 u32 value; 492 493 spin_lock_irqsave(&pctrl->lock, flags); 494 495 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 496 value = readl(padcfg1); 497 498 switch (param) { 499 case PIN_CONFIG_BIAS_DISABLE: 500 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 501 break; 502 503 case PIN_CONFIG_BIAS_PULL_UP: 504 value &= ~PADCFG1_TERM_MASK; 505 506 value |= PADCFG1_TERM_UP; 507 508 switch (arg) { 509 case 20000: 510 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 511 break; 512 case 5000: 513 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 514 break; 515 case 2000: 516 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 517 break; 518 case 1000: 519 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 520 break; 521 default: 522 ret = -EINVAL; 523 } 524 525 break; 526 527 case PIN_CONFIG_BIAS_PULL_DOWN: 528 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 529 530 switch (arg) { 531 case 20000: 532 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 533 break; 534 case 5000: 535 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 536 break; 537 default: 538 ret = -EINVAL; 539 } 540 541 break; 542 } 543 544 if (!ret) 545 writel(value, padcfg1); 546 547 spin_unlock_irqrestore(&pctrl->lock, flags); 548 549 return ret; 550 } 551 552 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, 553 unsigned long *configs, unsigned nconfigs) 554 { 555 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 556 int i, ret; 557 558 if (!intel_pad_usable(pctrl, pin)) 559 return -ENOTSUPP; 560 561 for (i = 0; i < nconfigs; i++) { 562 switch (pinconf_to_config_param(configs[i])) { 563 case PIN_CONFIG_BIAS_DISABLE: 564 case PIN_CONFIG_BIAS_PULL_UP: 565 case PIN_CONFIG_BIAS_PULL_DOWN: 566 ret = intel_config_set_pull(pctrl, pin, configs[i]); 567 if (ret) 568 return ret; 569 break; 570 571 default: 572 return -ENOTSUPP; 573 } 574 } 575 576 return 0; 577 } 578 579 static const struct pinconf_ops intel_pinconf_ops = { 580 .is_generic = true, 581 .pin_config_get = intel_config_get, 582 .pin_config_set = intel_config_set, 583 }; 584 585 static const struct pinctrl_desc intel_pinctrl_desc = { 586 .pctlops = &intel_pinctrl_ops, 587 .pmxops = &intel_pinmux_ops, 588 .confops = &intel_pinconf_ops, 589 .owner = THIS_MODULE, 590 }; 591 592 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) 593 { 594 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 595 void __iomem *reg; 596 597 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 598 if (!reg) 599 return -EINVAL; 600 601 return !!(readl(reg) & PADCFG0_GPIORXSTATE); 602 } 603 604 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 605 { 606 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 607 void __iomem *reg; 608 609 reg = intel_get_padcfg(pctrl, offset, PADCFG0); 610 if (reg) { 611 unsigned long flags; 612 u32 padcfg0; 613 614 spin_lock_irqsave(&pctrl->lock, flags); 615 padcfg0 = readl(reg); 616 if (value) 617 padcfg0 |= PADCFG0_GPIOTXSTATE; 618 else 619 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 620 writel(padcfg0, reg); 621 spin_unlock_irqrestore(&pctrl->lock, flags); 622 } 623 } 624 625 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 626 { 627 return pinctrl_gpio_direction_input(chip->base + offset); 628 } 629 630 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 631 int value) 632 { 633 intel_gpio_set(chip, offset, value); 634 return pinctrl_gpio_direction_output(chip->base + offset); 635 } 636 637 static const struct gpio_chip intel_gpio_chip = { 638 .owner = THIS_MODULE, 639 .request = gpiochip_generic_request, 640 .free = gpiochip_generic_free, 641 .direction_input = intel_gpio_direction_input, 642 .direction_output = intel_gpio_direction_output, 643 .get = intel_gpio_get, 644 .set = intel_gpio_set, 645 }; 646 647 static void intel_gpio_irq_ack(struct irq_data *d) 648 { 649 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 650 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 651 const struct intel_community *community; 652 unsigned pin = irqd_to_hwirq(d); 653 654 spin_lock(&pctrl->lock); 655 656 community = intel_get_community(pctrl, pin); 657 if (community) { 658 unsigned padno = pin_to_padno(community, pin); 659 unsigned gpp_offset = padno % community->gpp_size; 660 unsigned gpp = padno / community->gpp_size; 661 662 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 663 } 664 665 spin_unlock(&pctrl->lock); 666 } 667 668 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 669 { 670 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 671 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 672 const struct intel_community *community; 673 unsigned pin = irqd_to_hwirq(d); 674 unsigned long flags; 675 676 spin_lock_irqsave(&pctrl->lock, flags); 677 678 community = intel_get_community(pctrl, pin); 679 if (community) { 680 unsigned padno = pin_to_padno(community, pin); 681 unsigned gpp_offset = padno % community->gpp_size; 682 unsigned gpp = padno / community->gpp_size; 683 void __iomem *reg; 684 u32 value; 685 686 reg = community->regs + community->ie_offset + gpp * 4; 687 value = readl(reg); 688 if (mask) 689 value &= ~BIT(gpp_offset); 690 else 691 value |= BIT(gpp_offset); 692 writel(value, reg); 693 } 694 695 spin_unlock_irqrestore(&pctrl->lock, flags); 696 } 697 698 static void intel_gpio_irq_mask(struct irq_data *d) 699 { 700 intel_gpio_irq_mask_unmask(d, true); 701 } 702 703 static void intel_gpio_irq_unmask(struct irq_data *d) 704 { 705 intel_gpio_irq_mask_unmask(d, false); 706 } 707 708 static int intel_gpio_irq_type(struct irq_data *d, unsigned type) 709 { 710 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 711 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 712 unsigned pin = irqd_to_hwirq(d); 713 unsigned long flags; 714 void __iomem *reg; 715 u32 value; 716 717 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 718 if (!reg) 719 return -EINVAL; 720 721 /* 722 * If the pin is in ACPI mode it is still usable as a GPIO but it 723 * cannot be used as IRQ because GPI_IS status bit will not be 724 * updated by the host controller hardware. 725 */ 726 if (intel_pad_acpi_mode(pctrl, pin)) { 727 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 728 return -EPERM; 729 } 730 731 spin_lock_irqsave(&pctrl->lock, flags); 732 733 value = readl(reg); 734 735 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 736 737 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 738 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 739 } else if (type & IRQ_TYPE_EDGE_FALLING) { 740 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 741 value |= PADCFG0_RXINV; 742 } else if (type & IRQ_TYPE_EDGE_RISING) { 743 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 744 } else if (type & IRQ_TYPE_LEVEL_LOW) { 745 value |= PADCFG0_RXINV; 746 } else { 747 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 748 } 749 750 writel(value, reg); 751 752 if (type & IRQ_TYPE_EDGE_BOTH) 753 irq_set_handler_locked(d, handle_edge_irq); 754 else if (type & IRQ_TYPE_LEVEL_MASK) 755 irq_set_handler_locked(d, handle_level_irq); 756 757 spin_unlock_irqrestore(&pctrl->lock, flags); 758 759 return 0; 760 } 761 762 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 763 { 764 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 765 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 766 const struct intel_community *community; 767 unsigned pin = irqd_to_hwirq(d); 768 unsigned padno, gpp, gpp_offset; 769 u32 gpe_en; 770 771 community = intel_get_community(pctrl, pin); 772 if (!community) 773 return -EINVAL; 774 775 padno = pin_to_padno(community, pin); 776 gpp = padno / community->gpp_size; 777 gpp_offset = padno % community->gpp_size; 778 779 /* Clear the existing wake status */ 780 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4); 781 782 /* 783 * The controller will generate wake when GPE of the corresponding 784 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not 785 * set). 786 */ 787 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4); 788 if (on) 789 gpe_en |= BIT(gpp_offset); 790 else 791 gpe_en &= ~BIT(gpp_offset); 792 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4); 793 794 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 795 return 0; 796 } 797 798 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 799 const struct intel_community *community) 800 { 801 struct gpio_chip *gc = &pctrl->chip; 802 irqreturn_t ret = IRQ_NONE; 803 int gpp; 804 805 for (gpp = 0; gpp < community->ngpps; gpp++) { 806 unsigned long pending, enabled, gpp_offset; 807 808 pending = readl(community->regs + GPI_IS + gpp * 4); 809 enabled = readl(community->regs + community->ie_offset + 810 gpp * 4); 811 812 /* Only interrupts that are enabled */ 813 pending &= enabled; 814 815 for_each_set_bit(gpp_offset, &pending, community->gpp_size) { 816 unsigned padno, irq; 817 818 /* 819 * The last group in community can have less pins 820 * than NPADS_IN_GPP. 821 */ 822 padno = gpp_offset + gpp * community->gpp_size; 823 if (padno >= community->npins) 824 break; 825 826 irq = irq_find_mapping(gc->irqdomain, 827 community->pin_base + padno); 828 generic_handle_irq(irq); 829 830 ret |= IRQ_HANDLED; 831 } 832 } 833 834 return ret; 835 } 836 837 static irqreturn_t intel_gpio_irq(int irq, void *data) 838 { 839 const struct intel_community *community; 840 struct intel_pinctrl *pctrl = data; 841 irqreturn_t ret = IRQ_NONE; 842 int i; 843 844 /* Need to check all communities for pending interrupts */ 845 for (i = 0; i < pctrl->ncommunities; i++) { 846 community = &pctrl->communities[i]; 847 ret |= intel_gpio_community_irq_handler(pctrl, community); 848 } 849 850 return ret; 851 } 852 853 static struct irq_chip intel_gpio_irqchip = { 854 .name = "intel-gpio", 855 .irq_ack = intel_gpio_irq_ack, 856 .irq_mask = intel_gpio_irq_mask, 857 .irq_unmask = intel_gpio_irq_unmask, 858 .irq_set_type = intel_gpio_irq_type, 859 .irq_set_wake = intel_gpio_irq_wake, 860 }; 861 862 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 863 { 864 int ret; 865 866 pctrl->chip = intel_gpio_chip; 867 868 pctrl->chip.ngpio = pctrl->soc->npins; 869 pctrl->chip.label = dev_name(pctrl->dev); 870 pctrl->chip.parent = pctrl->dev; 871 pctrl->chip.base = -1; 872 873 ret = gpiochip_add_data(&pctrl->chip, pctrl); 874 if (ret) { 875 dev_err(pctrl->dev, "failed to register gpiochip\n"); 876 return ret; 877 } 878 879 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 880 0, 0, pctrl->soc->npins); 881 if (ret) { 882 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 883 goto fail; 884 } 885 886 /* 887 * We need to request the interrupt here (instead of providing chip 888 * to the irq directly) because on some platforms several GPIO 889 * controllers share the same interrupt line. 890 */ 891 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED, 892 dev_name(pctrl->dev), pctrl); 893 if (ret) { 894 dev_err(pctrl->dev, "failed to request interrupt\n"); 895 goto fail; 896 } 897 898 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 899 handle_simple_irq, IRQ_TYPE_NONE); 900 if (ret) { 901 dev_err(pctrl->dev, "failed to add irqchip\n"); 902 goto fail; 903 } 904 905 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 906 NULL); 907 return 0; 908 909 fail: 910 gpiochip_remove(&pctrl->chip); 911 912 return ret; 913 } 914 915 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 916 { 917 #ifdef CONFIG_PM_SLEEP 918 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 919 struct intel_community_context *communities; 920 struct intel_pad_context *pads; 921 int i; 922 923 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 924 if (!pads) 925 return -ENOMEM; 926 927 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 928 sizeof(*communities), GFP_KERNEL); 929 if (!communities) 930 return -ENOMEM; 931 932 933 for (i = 0; i < pctrl->ncommunities; i++) { 934 struct intel_community *community = &pctrl->communities[i]; 935 u32 *intmask; 936 937 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 938 sizeof(*intmask), GFP_KERNEL); 939 if (!intmask) 940 return -ENOMEM; 941 942 communities[i].intmask = intmask; 943 } 944 945 pctrl->context.pads = pads; 946 pctrl->context.communities = communities; 947 #endif 948 949 return 0; 950 } 951 952 int intel_pinctrl_probe(struct platform_device *pdev, 953 const struct intel_pinctrl_soc_data *soc_data) 954 { 955 struct intel_pinctrl *pctrl; 956 int i, ret, irq; 957 958 if (!soc_data) 959 return -EINVAL; 960 961 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 962 if (!pctrl) 963 return -ENOMEM; 964 965 pctrl->dev = &pdev->dev; 966 pctrl->soc = soc_data; 967 spin_lock_init(&pctrl->lock); 968 969 /* 970 * Make a copy of the communities which we can use to hold pointers 971 * to the registers. 972 */ 973 pctrl->ncommunities = pctrl->soc->ncommunities; 974 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 975 sizeof(*pctrl->communities), GFP_KERNEL); 976 if (!pctrl->communities) 977 return -ENOMEM; 978 979 for (i = 0; i < pctrl->ncommunities; i++) { 980 struct intel_community *community = &pctrl->communities[i]; 981 struct resource *res; 982 void __iomem *regs; 983 u32 padbar; 984 985 *community = pctrl->soc->communities[i]; 986 987 res = platform_get_resource(pdev, IORESOURCE_MEM, 988 community->barno); 989 regs = devm_ioremap_resource(&pdev->dev, res); 990 if (IS_ERR(regs)) 991 return PTR_ERR(regs); 992 993 /* Read offset of the pad configuration registers */ 994 padbar = readl(regs + PADBAR); 995 996 community->regs = regs; 997 community->pad_regs = regs + padbar; 998 community->ngpps = DIV_ROUND_UP(community->npins, 999 community->gpp_size); 1000 } 1001 1002 irq = platform_get_irq(pdev, 0); 1003 if (irq < 0) { 1004 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1005 return irq; 1006 } 1007 1008 ret = intel_pinctrl_pm_init(pctrl); 1009 if (ret) 1010 return ret; 1011 1012 pctrl->pctldesc = intel_pinctrl_desc; 1013 pctrl->pctldesc.name = dev_name(&pdev->dev); 1014 pctrl->pctldesc.pins = pctrl->soc->pins; 1015 pctrl->pctldesc.npins = pctrl->soc->npins; 1016 1017 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); 1018 if (IS_ERR(pctrl->pctldev)) { 1019 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1020 return PTR_ERR(pctrl->pctldev); 1021 } 1022 1023 ret = intel_gpio_probe(pctrl, irq); 1024 if (ret) { 1025 pinctrl_unregister(pctrl->pctldev); 1026 return ret; 1027 } 1028 1029 platform_set_drvdata(pdev, pctrl); 1030 1031 return 0; 1032 } 1033 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1034 1035 int intel_pinctrl_remove(struct platform_device *pdev) 1036 { 1037 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1038 1039 gpiochip_remove(&pctrl->chip); 1040 pinctrl_unregister(pctrl->pctldev); 1041 1042 return 0; 1043 } 1044 EXPORT_SYMBOL_GPL(intel_pinctrl_remove); 1045 1046 #ifdef CONFIG_PM_SLEEP 1047 int intel_pinctrl_suspend(struct device *dev) 1048 { 1049 struct platform_device *pdev = to_platform_device(dev); 1050 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1051 struct intel_community_context *communities; 1052 struct intel_pad_context *pads; 1053 int i; 1054 1055 pads = pctrl->context.pads; 1056 for (i = 0; i < pctrl->soc->npins; i++) { 1057 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1058 u32 val; 1059 1060 if (!intel_pad_usable(pctrl, desc->number)) 1061 continue; 1062 1063 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1064 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1065 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1066 pads[i].padcfg1 = val; 1067 } 1068 1069 communities = pctrl->context.communities; 1070 for (i = 0; i < pctrl->ncommunities; i++) { 1071 struct intel_community *community = &pctrl->communities[i]; 1072 void __iomem *base; 1073 unsigned gpp; 1074 1075 base = community->regs + community->ie_offset; 1076 for (gpp = 0; gpp < community->ngpps; gpp++) 1077 communities[i].intmask[gpp] = readl(base + gpp * 4); 1078 } 1079 1080 return 0; 1081 } 1082 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1083 1084 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1085 { 1086 size_t i; 1087 1088 for (i = 0; i < pctrl->ncommunities; i++) { 1089 const struct intel_community *community; 1090 void __iomem *base; 1091 unsigned gpp; 1092 1093 community = &pctrl->communities[i]; 1094 base = community->regs; 1095 1096 for (gpp = 0; gpp < community->ngpps; gpp++) { 1097 /* Mask and clear all interrupts */ 1098 writel(0, base + community->ie_offset + gpp * 4); 1099 writel(0xffff, base + GPI_IS + gpp * 4); 1100 } 1101 } 1102 } 1103 1104 int intel_pinctrl_resume(struct device *dev) 1105 { 1106 struct platform_device *pdev = to_platform_device(dev); 1107 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1108 const struct intel_community_context *communities; 1109 const struct intel_pad_context *pads; 1110 int i; 1111 1112 /* Mask all interrupts */ 1113 intel_gpio_irq_init(pctrl); 1114 1115 pads = pctrl->context.pads; 1116 for (i = 0; i < pctrl->soc->npins; i++) { 1117 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1118 void __iomem *padcfg; 1119 u32 val; 1120 1121 if (!intel_pad_usable(pctrl, desc->number)) 1122 continue; 1123 1124 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1125 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1126 if (val != pads[i].padcfg0) { 1127 writel(pads[i].padcfg0, padcfg); 1128 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1129 desc->number, readl(padcfg)); 1130 } 1131 1132 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1133 val = readl(padcfg); 1134 if (val != pads[i].padcfg1) { 1135 writel(pads[i].padcfg1, padcfg); 1136 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1137 desc->number, readl(padcfg)); 1138 } 1139 } 1140 1141 communities = pctrl->context.communities; 1142 for (i = 0; i < pctrl->ncommunities; i++) { 1143 struct intel_community *community = &pctrl->communities[i]; 1144 void __iomem *base; 1145 unsigned gpp; 1146 1147 base = community->regs + community->ie_offset; 1148 for (gpp = 0; gpp < community->ngpps; gpp++) { 1149 writel(communities[i].intmask[gpp], base + gpp * 4); 1150 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1151 readl(base + gpp * 4)); 1152 } 1153 } 1154 1155 return 0; 1156 } 1157 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1158 #endif 1159 1160 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1161 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1162 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1163 MODULE_LICENSE("GPL v2"); 1164