1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/log2.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 23 #include "../core.h" 24 #include "pinctrl-intel.h" 25 26 /* Offset from regs */ 27 #define REVID 0x000 28 #define REVID_SHIFT 16 29 #define REVID_MASK GENMASK(31, 16) 30 31 #define PADBAR 0x00c 32 #define GPI_IS 0x100 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_PREGFRXSEL BIT(24) 48 #define PADCFG0_RXINV BIT(23) 49 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 50 #define PADCFG0_GPIROUTSCI BIT(19) 51 #define PADCFG0_GPIROUTSMI BIT(18) 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 #define PADCFG0_PMODE_SHIFT 10 54 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) 55 #define PADCFG0_GPIORXDIS BIT(9) 56 #define PADCFG0_GPIOTXDIS BIT(8) 57 #define PADCFG0_GPIORXSTATE BIT(1) 58 #define PADCFG0_GPIOTXSTATE BIT(0) 59 60 #define PADCFG1 0x004 61 #define PADCFG1_TERM_UP BIT(13) 62 #define PADCFG1_TERM_SHIFT 10 63 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) 64 #define PADCFG1_TERM_20K 4 65 #define PADCFG1_TERM_2K 3 66 #define PADCFG1_TERM_5K 2 67 #define PADCFG1_TERM_1K 1 68 69 #define PADCFG2 0x008 70 #define PADCFG2_DEBEN BIT(0) 71 #define PADCFG2_DEBOUNCE_SHIFT 1 72 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 73 74 #define DEBOUNCE_PERIOD 31250 /* ns */ 75 76 struct intel_pad_context { 77 u32 padcfg0; 78 u32 padcfg1; 79 u32 padcfg2; 80 }; 81 82 struct intel_community_context { 83 u32 *intmask; 84 }; 85 86 struct intel_pinctrl_context { 87 struct intel_pad_context *pads; 88 struct intel_community_context *communities; 89 }; 90 91 /** 92 * struct intel_pinctrl - Intel pinctrl private structure 93 * @dev: Pointer to the device structure 94 * @lock: Lock to serialize register access 95 * @pctldesc: Pin controller description 96 * @pctldev: Pointer to the pin controller device 97 * @chip: GPIO chip in this pin controller 98 * @soc: SoC/PCH specific pin configuration data 99 * @communities: All communities in this pin controller 100 * @ncommunities: Number of communities in this pin controller 101 * @context: Configuration saved over system sleep 102 * @irq: pinctrl/GPIO chip irq number 103 */ 104 struct intel_pinctrl { 105 struct device *dev; 106 raw_spinlock_t lock; 107 struct pinctrl_desc pctldesc; 108 struct pinctrl_dev *pctldev; 109 struct gpio_chip chip; 110 const struct intel_pinctrl_soc_data *soc; 111 struct intel_community *communities; 112 size_t ncommunities; 113 struct intel_pinctrl_context context; 114 int irq; 115 }; 116 117 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 118 #define padgroup_offset(g, p) ((p) - (g)->base) 119 120 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 121 unsigned int pin) 122 { 123 struct intel_community *community; 124 int i; 125 126 for (i = 0; i < pctrl->ncommunities; i++) { 127 community = &pctrl->communities[i]; 128 if (pin >= community->pin_base && 129 pin < community->pin_base + community->npins) 130 return community; 131 } 132 133 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 134 return NULL; 135 } 136 137 static const struct intel_padgroup * 138 intel_community_get_padgroup(const struct intel_community *community, 139 unsigned int pin) 140 { 141 int i; 142 143 for (i = 0; i < community->ngpps; i++) { 144 const struct intel_padgroup *padgrp = &community->gpps[i]; 145 146 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 147 return padgrp; 148 } 149 150 return NULL; 151 } 152 153 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 154 unsigned int pin, unsigned int reg) 155 { 156 const struct intel_community *community; 157 unsigned int padno; 158 size_t nregs; 159 160 community = intel_get_community(pctrl, pin); 161 if (!community) 162 return NULL; 163 164 padno = pin_to_padno(community, pin); 165 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 166 167 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) 168 return NULL; 169 170 return community->pad_regs + reg + padno * nregs * 4; 171 } 172 173 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 174 { 175 const struct intel_community *community; 176 const struct intel_padgroup *padgrp; 177 unsigned int gpp, offset, gpp_offset; 178 void __iomem *padown; 179 180 community = intel_get_community(pctrl, pin); 181 if (!community) 182 return false; 183 if (!community->padown_offset) 184 return true; 185 186 padgrp = intel_community_get_padgroup(community, pin); 187 if (!padgrp) 188 return false; 189 190 gpp_offset = padgroup_offset(padgrp, pin); 191 gpp = PADOWN_GPP(gpp_offset); 192 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 193 padown = community->regs + offset; 194 195 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 196 } 197 198 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 199 { 200 const struct intel_community *community; 201 const struct intel_padgroup *padgrp; 202 unsigned int offset, gpp_offset; 203 void __iomem *hostown; 204 205 community = intel_get_community(pctrl, pin); 206 if (!community) 207 return true; 208 if (!community->hostown_offset) 209 return false; 210 211 padgrp = intel_community_get_padgroup(community, pin); 212 if (!padgrp) 213 return true; 214 215 gpp_offset = padgroup_offset(padgrp, pin); 216 offset = community->hostown_offset + padgrp->reg_num * 4; 217 hostown = community->regs + offset; 218 219 return !(readl(hostown) & BIT(gpp_offset)); 220 } 221 222 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 223 { 224 struct intel_community *community; 225 const struct intel_padgroup *padgrp; 226 unsigned int offset, gpp_offset; 227 u32 value; 228 229 community = intel_get_community(pctrl, pin); 230 if (!community) 231 return true; 232 if (!community->padcfglock_offset) 233 return false; 234 235 padgrp = intel_community_get_padgroup(community, pin); 236 if (!padgrp) 237 return true; 238 239 gpp_offset = padgroup_offset(padgrp, pin); 240 241 /* 242 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 243 * the pad is considered unlocked. Any other case means that it is 244 * either fully or partially locked and we don't touch it. 245 */ 246 offset = community->padcfglock_offset + padgrp->reg_num * 8; 247 value = readl(community->regs + offset); 248 if (value & BIT(gpp_offset)) 249 return true; 250 251 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 252 value = readl(community->regs + offset); 253 if (value & BIT(gpp_offset)) 254 return true; 255 256 return false; 257 } 258 259 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 260 { 261 return intel_pad_owned_by_host(pctrl, pin) && 262 !intel_pad_locked(pctrl, pin); 263 } 264 265 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 266 { 267 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 268 269 return pctrl->soc->ngroups; 270 } 271 272 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 273 unsigned int group) 274 { 275 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 276 277 return pctrl->soc->groups[group].name; 278 } 279 280 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 281 const unsigned int **pins, unsigned int *npins) 282 { 283 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 284 285 *pins = pctrl->soc->groups[group].pins; 286 *npins = pctrl->soc->groups[group].npins; 287 return 0; 288 } 289 290 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 291 unsigned int pin) 292 { 293 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 294 void __iomem *padcfg; 295 u32 cfg0, cfg1, mode; 296 bool locked, acpi; 297 298 if (!intel_pad_owned_by_host(pctrl, pin)) { 299 seq_puts(s, "not available"); 300 return; 301 } 302 303 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 304 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 305 306 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 307 if (!mode) 308 seq_puts(s, "GPIO "); 309 else 310 seq_printf(s, "mode %d ", mode); 311 312 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 313 314 /* Dump the additional PADCFG registers if available */ 315 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 316 if (padcfg) 317 seq_printf(s, " 0x%08x", readl(padcfg)); 318 319 locked = intel_pad_locked(pctrl, pin); 320 acpi = intel_pad_acpi_mode(pctrl, pin); 321 322 if (locked || acpi) { 323 seq_puts(s, " ["); 324 if (locked) { 325 seq_puts(s, "LOCKED"); 326 if (acpi) 327 seq_puts(s, ", "); 328 } 329 if (acpi) 330 seq_puts(s, "ACPI"); 331 seq_puts(s, "]"); 332 } 333 } 334 335 static const struct pinctrl_ops intel_pinctrl_ops = { 336 .get_groups_count = intel_get_groups_count, 337 .get_group_name = intel_get_group_name, 338 .get_group_pins = intel_get_group_pins, 339 .pin_dbg_show = intel_pin_dbg_show, 340 }; 341 342 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 343 { 344 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 345 346 return pctrl->soc->nfunctions; 347 } 348 349 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 350 unsigned int function) 351 { 352 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctrl->soc->functions[function].name; 355 } 356 357 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 358 unsigned int function, 359 const char * const **groups, 360 unsigned int * const ngroups) 361 { 362 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 363 364 *groups = pctrl->soc->functions[function].groups; 365 *ngroups = pctrl->soc->functions[function].ngroups; 366 return 0; 367 } 368 369 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 370 unsigned int function, unsigned int group) 371 { 372 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 373 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 374 unsigned long flags; 375 int i; 376 377 raw_spin_lock_irqsave(&pctrl->lock, flags); 378 379 /* 380 * All pins in the groups needs to be accessible and writable 381 * before we can enable the mux for this group. 382 */ 383 for (i = 0; i < grp->npins; i++) { 384 if (!intel_pad_usable(pctrl, grp->pins[i])) { 385 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 386 return -EBUSY; 387 } 388 } 389 390 /* Now enable the mux setting for each pin in the group */ 391 for (i = 0; i < grp->npins; i++) { 392 void __iomem *padcfg0; 393 u32 value; 394 395 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 396 value = readl(padcfg0); 397 398 value &= ~PADCFG0_PMODE_MASK; 399 400 if (grp->modes) 401 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 402 else 403 value |= grp->mode << PADCFG0_PMODE_SHIFT; 404 405 writel(value, padcfg0); 406 } 407 408 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 409 410 return 0; 411 } 412 413 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 414 { 415 u32 value; 416 417 value = readl(padcfg0); 418 if (input) { 419 value &= ~PADCFG0_GPIORXDIS; 420 value |= PADCFG0_GPIOTXDIS; 421 } else { 422 value &= ~PADCFG0_GPIOTXDIS; 423 value |= PADCFG0_GPIORXDIS; 424 } 425 writel(value, padcfg0); 426 } 427 428 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 429 { 430 u32 value; 431 432 /* Put the pad into GPIO mode */ 433 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; 434 /* Disable SCI/SMI/NMI generation */ 435 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 436 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 437 writel(value, padcfg0); 438 } 439 440 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 441 struct pinctrl_gpio_range *range, 442 unsigned int pin) 443 { 444 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 445 void __iomem *padcfg0; 446 unsigned long flags; 447 448 raw_spin_lock_irqsave(&pctrl->lock, flags); 449 450 if (!intel_pad_usable(pctrl, pin)) { 451 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 452 return -EBUSY; 453 } 454 455 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 456 intel_gpio_set_gpio_mode(padcfg0); 457 /* Disable TX buffer and enable RX (this will be input) */ 458 __intel_gpio_set_direction(padcfg0, true); 459 460 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 461 462 return 0; 463 } 464 465 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 466 struct pinctrl_gpio_range *range, 467 unsigned int pin, bool input) 468 { 469 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 470 void __iomem *padcfg0; 471 unsigned long flags; 472 473 raw_spin_lock_irqsave(&pctrl->lock, flags); 474 475 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 476 __intel_gpio_set_direction(padcfg0, input); 477 478 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 479 480 return 0; 481 } 482 483 static const struct pinmux_ops intel_pinmux_ops = { 484 .get_functions_count = intel_get_functions_count, 485 .get_function_name = intel_get_function_name, 486 .get_function_groups = intel_get_function_groups, 487 .set_mux = intel_pinmux_set_mux, 488 .gpio_request_enable = intel_gpio_request_enable, 489 .gpio_set_direction = intel_gpio_set_direction, 490 }; 491 492 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 493 unsigned long *config) 494 { 495 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 496 enum pin_config_param param = pinconf_to_config_param(*config); 497 const struct intel_community *community; 498 u32 value, term; 499 u32 arg = 0; 500 501 if (!intel_pad_owned_by_host(pctrl, pin)) 502 return -ENOTSUPP; 503 504 community = intel_get_community(pctrl, pin); 505 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 506 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 507 508 switch (param) { 509 case PIN_CONFIG_BIAS_DISABLE: 510 if (term) 511 return -EINVAL; 512 break; 513 514 case PIN_CONFIG_BIAS_PULL_UP: 515 if (!term || !(value & PADCFG1_TERM_UP)) 516 return -EINVAL; 517 518 switch (term) { 519 case PADCFG1_TERM_1K: 520 arg = 1000; 521 break; 522 case PADCFG1_TERM_2K: 523 arg = 2000; 524 break; 525 case PADCFG1_TERM_5K: 526 arg = 5000; 527 break; 528 case PADCFG1_TERM_20K: 529 arg = 20000; 530 break; 531 } 532 533 break; 534 535 case PIN_CONFIG_BIAS_PULL_DOWN: 536 if (!term || value & PADCFG1_TERM_UP) 537 return -EINVAL; 538 539 switch (term) { 540 case PADCFG1_TERM_1K: 541 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 542 return -EINVAL; 543 arg = 1000; 544 break; 545 case PADCFG1_TERM_5K: 546 arg = 5000; 547 break; 548 case PADCFG1_TERM_20K: 549 arg = 20000; 550 break; 551 } 552 553 break; 554 555 case PIN_CONFIG_INPUT_DEBOUNCE: { 556 void __iomem *padcfg2; 557 u32 v; 558 559 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 560 if (!padcfg2) 561 return -ENOTSUPP; 562 563 v = readl(padcfg2); 564 if (!(v & PADCFG2_DEBEN)) 565 return -EINVAL; 566 567 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 568 arg = BIT(v) * DEBOUNCE_PERIOD / 1000; 569 570 break; 571 } 572 573 default: 574 return -ENOTSUPP; 575 } 576 577 *config = pinconf_to_config_packed(param, arg); 578 return 0; 579 } 580 581 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 582 unsigned long config) 583 { 584 unsigned int param = pinconf_to_config_param(config); 585 unsigned int arg = pinconf_to_config_argument(config); 586 const struct intel_community *community; 587 void __iomem *padcfg1; 588 unsigned long flags; 589 int ret = 0; 590 u32 value; 591 592 raw_spin_lock_irqsave(&pctrl->lock, flags); 593 594 community = intel_get_community(pctrl, pin); 595 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 596 value = readl(padcfg1); 597 598 switch (param) { 599 case PIN_CONFIG_BIAS_DISABLE: 600 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 601 break; 602 603 case PIN_CONFIG_BIAS_PULL_UP: 604 value &= ~PADCFG1_TERM_MASK; 605 606 value |= PADCFG1_TERM_UP; 607 608 switch (arg) { 609 case 20000: 610 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 611 break; 612 case 5000: 613 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 614 break; 615 case 2000: 616 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 617 break; 618 case 1000: 619 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 620 break; 621 default: 622 ret = -EINVAL; 623 } 624 625 break; 626 627 case PIN_CONFIG_BIAS_PULL_DOWN: 628 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 629 630 switch (arg) { 631 case 20000: 632 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 633 break; 634 case 5000: 635 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 636 break; 637 case 1000: 638 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 639 ret = -EINVAL; 640 break; 641 } 642 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 643 break; 644 default: 645 ret = -EINVAL; 646 } 647 648 break; 649 } 650 651 if (!ret) 652 writel(value, padcfg1); 653 654 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 655 656 return ret; 657 } 658 659 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 660 unsigned int pin, unsigned int debounce) 661 { 662 void __iomem *padcfg0, *padcfg2; 663 unsigned long flags; 664 u32 value0, value2; 665 int ret = 0; 666 667 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 668 if (!padcfg2) 669 return -ENOTSUPP; 670 671 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 672 673 raw_spin_lock_irqsave(&pctrl->lock, flags); 674 675 value0 = readl(padcfg0); 676 value2 = readl(padcfg2); 677 678 /* Disable glitch filter and debouncer */ 679 value0 &= ~PADCFG0_PREGFRXSEL; 680 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 681 682 if (debounce) { 683 unsigned long v; 684 685 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); 686 if (v < 3 || v > 15) { 687 ret = -EINVAL; 688 goto exit_unlock; 689 } else { 690 /* Enable glitch filter and debouncer */ 691 value0 |= PADCFG0_PREGFRXSEL; 692 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 693 value2 |= PADCFG2_DEBEN; 694 } 695 } 696 697 writel(value0, padcfg0); 698 writel(value2, padcfg2); 699 700 exit_unlock: 701 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 702 703 return ret; 704 } 705 706 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 707 unsigned long *configs, unsigned int nconfigs) 708 { 709 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 710 int i, ret; 711 712 if (!intel_pad_usable(pctrl, pin)) 713 return -ENOTSUPP; 714 715 for (i = 0; i < nconfigs; i++) { 716 switch (pinconf_to_config_param(configs[i])) { 717 case PIN_CONFIG_BIAS_DISABLE: 718 case PIN_CONFIG_BIAS_PULL_UP: 719 case PIN_CONFIG_BIAS_PULL_DOWN: 720 ret = intel_config_set_pull(pctrl, pin, configs[i]); 721 if (ret) 722 return ret; 723 break; 724 725 case PIN_CONFIG_INPUT_DEBOUNCE: 726 ret = intel_config_set_debounce(pctrl, pin, 727 pinconf_to_config_argument(configs[i])); 728 if (ret) 729 return ret; 730 break; 731 732 default: 733 return -ENOTSUPP; 734 } 735 } 736 737 return 0; 738 } 739 740 static const struct pinconf_ops intel_pinconf_ops = { 741 .is_generic = true, 742 .pin_config_get = intel_config_get, 743 .pin_config_set = intel_config_set, 744 }; 745 746 static const struct pinctrl_desc intel_pinctrl_desc = { 747 .pctlops = &intel_pinctrl_ops, 748 .pmxops = &intel_pinmux_ops, 749 .confops = &intel_pinconf_ops, 750 .owner = THIS_MODULE, 751 }; 752 753 /** 754 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 755 * @pctrl: Pinctrl structure 756 * @offset: GPIO offset from gpiolib 757 * @community: Community is filled here if not %NULL 758 * @padgrp: Pad group is filled here if not %NULL 759 * 760 * When coming through gpiolib irqchip, the GPIO offset is not 761 * automatically translated to pinctrl pin number. This function can be 762 * used to find out the corresponding pinctrl pin. 763 */ 764 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 765 const struct intel_community **community, 766 const struct intel_padgroup **padgrp) 767 { 768 int i; 769 770 for (i = 0; i < pctrl->ncommunities; i++) { 771 const struct intel_community *comm = &pctrl->communities[i]; 772 int j; 773 774 for (j = 0; j < comm->ngpps; j++) { 775 const struct intel_padgroup *pgrp = &comm->gpps[j]; 776 777 if (pgrp->gpio_base < 0) 778 continue; 779 780 if (offset >= pgrp->gpio_base && 781 offset < pgrp->gpio_base + pgrp->size) { 782 int pin; 783 784 pin = pgrp->base + offset - pgrp->gpio_base; 785 if (community) 786 *community = comm; 787 if (padgrp) 788 *padgrp = pgrp; 789 790 return pin; 791 } 792 } 793 } 794 795 return -EINVAL; 796 } 797 798 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 799 { 800 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 801 void __iomem *reg; 802 u32 padcfg0; 803 int pin; 804 805 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 806 if (pin < 0) 807 return -EINVAL; 808 809 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 810 if (!reg) 811 return -EINVAL; 812 813 padcfg0 = readl(reg); 814 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 815 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 816 817 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 818 } 819 820 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 821 int value) 822 { 823 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 824 unsigned long flags; 825 void __iomem *reg; 826 u32 padcfg0; 827 int pin; 828 829 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 830 if (pin < 0) 831 return; 832 833 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 834 if (!reg) 835 return; 836 837 raw_spin_lock_irqsave(&pctrl->lock, flags); 838 padcfg0 = readl(reg); 839 if (value) 840 padcfg0 |= PADCFG0_GPIOTXSTATE; 841 else 842 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 843 writel(padcfg0, reg); 844 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 845 } 846 847 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 848 { 849 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 850 void __iomem *reg; 851 u32 padcfg0; 852 int pin; 853 854 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 855 if (pin < 0) 856 return -EINVAL; 857 858 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 859 if (!reg) 860 return -EINVAL; 861 862 padcfg0 = readl(reg); 863 864 if (padcfg0 & PADCFG0_PMODE_MASK) 865 return -EINVAL; 866 867 return !!(padcfg0 & PADCFG0_GPIOTXDIS); 868 } 869 870 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 871 { 872 return pinctrl_gpio_direction_input(chip->base + offset); 873 } 874 875 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 876 int value) 877 { 878 intel_gpio_set(chip, offset, value); 879 return pinctrl_gpio_direction_output(chip->base + offset); 880 } 881 882 static const struct gpio_chip intel_gpio_chip = { 883 .owner = THIS_MODULE, 884 .request = gpiochip_generic_request, 885 .free = gpiochip_generic_free, 886 .get_direction = intel_gpio_get_direction, 887 .direction_input = intel_gpio_direction_input, 888 .direction_output = intel_gpio_direction_output, 889 .get = intel_gpio_get, 890 .set = intel_gpio_set, 891 .set_config = gpiochip_generic_config, 892 }; 893 894 static void intel_gpio_irq_ack(struct irq_data *d) 895 { 896 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 897 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 898 const struct intel_community *community; 899 const struct intel_padgroup *padgrp; 900 int pin; 901 902 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 903 if (pin >= 0) { 904 unsigned int gpp, gpp_offset, is_offset; 905 906 gpp = padgrp->reg_num; 907 gpp_offset = padgroup_offset(padgrp, pin); 908 is_offset = community->is_offset + gpp * 4; 909 910 raw_spin_lock(&pctrl->lock); 911 writel(BIT(gpp_offset), community->regs + is_offset); 912 raw_spin_unlock(&pctrl->lock); 913 } 914 } 915 916 static void intel_gpio_irq_enable(struct irq_data *d) 917 { 918 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 919 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 920 const struct intel_community *community; 921 const struct intel_padgroup *padgrp; 922 int pin; 923 924 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 925 if (pin >= 0) { 926 unsigned int gpp, gpp_offset, is_offset; 927 unsigned long flags; 928 u32 value; 929 930 gpp = padgrp->reg_num; 931 gpp_offset = padgroup_offset(padgrp, pin); 932 is_offset = community->is_offset + gpp * 4; 933 934 raw_spin_lock_irqsave(&pctrl->lock, flags); 935 /* Clear interrupt status first to avoid unexpected interrupt */ 936 writel(BIT(gpp_offset), community->regs + is_offset); 937 938 value = readl(community->regs + community->ie_offset + gpp * 4); 939 value |= BIT(gpp_offset); 940 writel(value, community->regs + community->ie_offset + gpp * 4); 941 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 942 } 943 } 944 945 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 946 { 947 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 948 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 949 const struct intel_community *community; 950 const struct intel_padgroup *padgrp; 951 int pin; 952 953 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 954 if (pin >= 0) { 955 unsigned int gpp, gpp_offset; 956 unsigned long flags; 957 void __iomem *reg; 958 u32 value; 959 960 gpp = padgrp->reg_num; 961 gpp_offset = padgroup_offset(padgrp, pin); 962 963 reg = community->regs + community->ie_offset + gpp * 4; 964 965 raw_spin_lock_irqsave(&pctrl->lock, flags); 966 value = readl(reg); 967 if (mask) 968 value &= ~BIT(gpp_offset); 969 else 970 value |= BIT(gpp_offset); 971 writel(value, reg); 972 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 973 } 974 } 975 976 static void intel_gpio_irq_mask(struct irq_data *d) 977 { 978 intel_gpio_irq_mask_unmask(d, true); 979 } 980 981 static void intel_gpio_irq_unmask(struct irq_data *d) 982 { 983 intel_gpio_irq_mask_unmask(d, false); 984 } 985 986 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 987 { 988 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 989 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 990 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 991 unsigned long flags; 992 void __iomem *reg; 993 u32 value; 994 995 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 996 if (!reg) 997 return -EINVAL; 998 999 /* 1000 * If the pin is in ACPI mode it is still usable as a GPIO but it 1001 * cannot be used as IRQ because GPI_IS status bit will not be 1002 * updated by the host controller hardware. 1003 */ 1004 if (intel_pad_acpi_mode(pctrl, pin)) { 1005 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1006 return -EPERM; 1007 } 1008 1009 raw_spin_lock_irqsave(&pctrl->lock, flags); 1010 1011 intel_gpio_set_gpio_mode(reg); 1012 1013 value = readl(reg); 1014 1015 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1016 1017 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1018 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1019 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1020 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1021 value |= PADCFG0_RXINV; 1022 } else if (type & IRQ_TYPE_EDGE_RISING) { 1023 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1024 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1025 if (type & IRQ_TYPE_LEVEL_LOW) 1026 value |= PADCFG0_RXINV; 1027 } else { 1028 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1029 } 1030 1031 writel(value, reg); 1032 1033 if (type & IRQ_TYPE_EDGE_BOTH) 1034 irq_set_handler_locked(d, handle_edge_irq); 1035 else if (type & IRQ_TYPE_LEVEL_MASK) 1036 irq_set_handler_locked(d, handle_level_irq); 1037 1038 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1039 1040 return 0; 1041 } 1042 1043 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1044 { 1045 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1046 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1047 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1048 1049 if (on) 1050 enable_irq_wake(pctrl->irq); 1051 else 1052 disable_irq_wake(pctrl->irq); 1053 1054 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1055 return 0; 1056 } 1057 1058 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1059 const struct intel_community *community) 1060 { 1061 struct gpio_chip *gc = &pctrl->chip; 1062 irqreturn_t ret = IRQ_NONE; 1063 int gpp; 1064 1065 for (gpp = 0; gpp < community->ngpps; gpp++) { 1066 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1067 unsigned long pending, enabled, gpp_offset; 1068 1069 pending = readl(community->regs + community->is_offset + 1070 padgrp->reg_num * 4); 1071 enabled = readl(community->regs + community->ie_offset + 1072 padgrp->reg_num * 4); 1073 1074 /* Only interrupts that are enabled */ 1075 pending &= enabled; 1076 1077 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1078 unsigned irq; 1079 1080 irq = irq_find_mapping(gc->irq.domain, 1081 padgrp->gpio_base + gpp_offset); 1082 generic_handle_irq(irq); 1083 1084 ret |= IRQ_HANDLED; 1085 } 1086 } 1087 1088 return ret; 1089 } 1090 1091 static irqreturn_t intel_gpio_irq(int irq, void *data) 1092 { 1093 const struct intel_community *community; 1094 struct intel_pinctrl *pctrl = data; 1095 irqreturn_t ret = IRQ_NONE; 1096 int i; 1097 1098 /* Need to check all communities for pending interrupts */ 1099 for (i = 0; i < pctrl->ncommunities; i++) { 1100 community = &pctrl->communities[i]; 1101 ret |= intel_gpio_community_irq_handler(pctrl, community); 1102 } 1103 1104 return ret; 1105 } 1106 1107 static struct irq_chip intel_gpio_irqchip = { 1108 .name = "intel-gpio", 1109 .irq_enable = intel_gpio_irq_enable, 1110 .irq_ack = intel_gpio_irq_ack, 1111 .irq_mask = intel_gpio_irq_mask, 1112 .irq_unmask = intel_gpio_irq_unmask, 1113 .irq_set_type = intel_gpio_irq_type, 1114 .irq_set_wake = intel_gpio_irq_wake, 1115 .flags = IRQCHIP_MASK_ON_SUSPEND, 1116 }; 1117 1118 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, 1119 const struct intel_community *community) 1120 { 1121 int ret = 0, i; 1122 1123 for (i = 0; i < community->ngpps; i++) { 1124 const struct intel_padgroup *gpp = &community->gpps[i]; 1125 1126 if (gpp->gpio_base < 0) 1127 continue; 1128 1129 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1130 gpp->gpio_base, gpp->base, 1131 gpp->size); 1132 if (ret) 1133 return ret; 1134 } 1135 1136 return ret; 1137 } 1138 1139 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1140 { 1141 const struct intel_community *community; 1142 unsigned int ngpio = 0; 1143 int i, j; 1144 1145 for (i = 0; i < pctrl->ncommunities; i++) { 1146 community = &pctrl->communities[i]; 1147 for (j = 0; j < community->ngpps; j++) { 1148 const struct intel_padgroup *gpp = &community->gpps[j]; 1149 1150 if (gpp->gpio_base < 0) 1151 continue; 1152 1153 if (gpp->gpio_base + gpp->size > ngpio) 1154 ngpio = gpp->gpio_base + gpp->size; 1155 } 1156 } 1157 1158 return ngpio; 1159 } 1160 1161 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1162 { 1163 int ret, i; 1164 1165 pctrl->chip = intel_gpio_chip; 1166 1167 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1168 pctrl->chip.label = dev_name(pctrl->dev); 1169 pctrl->chip.parent = pctrl->dev; 1170 pctrl->chip.base = -1; 1171 pctrl->irq = irq; 1172 1173 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1174 if (ret) { 1175 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1176 return ret; 1177 } 1178 1179 for (i = 0; i < pctrl->ncommunities; i++) { 1180 struct intel_community *community = &pctrl->communities[i]; 1181 1182 ret = intel_gpio_add_pin_ranges(pctrl, community); 1183 if (ret) { 1184 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1185 return ret; 1186 } 1187 } 1188 1189 /* 1190 * We need to request the interrupt here (instead of providing chip 1191 * to the irq directly) because on some platforms several GPIO 1192 * controllers share the same interrupt line. 1193 */ 1194 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1195 IRQF_SHARED | IRQF_NO_THREAD, 1196 dev_name(pctrl->dev), pctrl); 1197 if (ret) { 1198 dev_err(pctrl->dev, "failed to request interrupt\n"); 1199 return ret; 1200 } 1201 1202 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 1203 handle_bad_irq, IRQ_TYPE_NONE); 1204 if (ret) { 1205 dev_err(pctrl->dev, "failed to add irqchip\n"); 1206 return ret; 1207 } 1208 1209 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 1210 NULL); 1211 return 0; 1212 } 1213 1214 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1215 struct intel_community *community) 1216 { 1217 struct intel_padgroup *gpps; 1218 unsigned int npins = community->npins; 1219 unsigned int padown_num = 0; 1220 size_t ngpps, i; 1221 1222 if (community->gpps) 1223 ngpps = community->ngpps; 1224 else 1225 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1226 1227 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1228 if (!gpps) 1229 return -ENOMEM; 1230 1231 for (i = 0; i < ngpps; i++) { 1232 if (community->gpps) { 1233 gpps[i] = community->gpps[i]; 1234 } else { 1235 unsigned int gpp_size = community->gpp_size; 1236 1237 gpps[i].reg_num = i; 1238 gpps[i].base = community->pin_base + i * gpp_size; 1239 gpps[i].size = min(gpp_size, npins); 1240 npins -= gpps[i].size; 1241 } 1242 1243 if (gpps[i].size > 32) 1244 return -EINVAL; 1245 1246 if (!gpps[i].gpio_base) 1247 gpps[i].gpio_base = gpps[i].base; 1248 1249 gpps[i].padown_num = padown_num; 1250 1251 /* 1252 * In older hardware the number of padown registers per 1253 * group is fixed regardless of the group size. 1254 */ 1255 if (community->gpp_num_padown_regs) 1256 padown_num += community->gpp_num_padown_regs; 1257 else 1258 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1259 } 1260 1261 community->ngpps = ngpps; 1262 community->gpps = gpps; 1263 1264 return 0; 1265 } 1266 1267 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1268 { 1269 #ifdef CONFIG_PM_SLEEP 1270 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1271 struct intel_community_context *communities; 1272 struct intel_pad_context *pads; 1273 int i; 1274 1275 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1276 if (!pads) 1277 return -ENOMEM; 1278 1279 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1280 sizeof(*communities), GFP_KERNEL); 1281 if (!communities) 1282 return -ENOMEM; 1283 1284 1285 for (i = 0; i < pctrl->ncommunities; i++) { 1286 struct intel_community *community = &pctrl->communities[i]; 1287 u32 *intmask; 1288 1289 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1290 sizeof(*intmask), GFP_KERNEL); 1291 if (!intmask) 1292 return -ENOMEM; 1293 1294 communities[i].intmask = intmask; 1295 } 1296 1297 pctrl->context.pads = pads; 1298 pctrl->context.communities = communities; 1299 #endif 1300 1301 return 0; 1302 } 1303 1304 int intel_pinctrl_probe(struct platform_device *pdev, 1305 const struct intel_pinctrl_soc_data *soc_data) 1306 { 1307 struct intel_pinctrl *pctrl; 1308 int i, ret, irq; 1309 1310 if (!soc_data) 1311 return -EINVAL; 1312 1313 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1314 if (!pctrl) 1315 return -ENOMEM; 1316 1317 pctrl->dev = &pdev->dev; 1318 pctrl->soc = soc_data; 1319 raw_spin_lock_init(&pctrl->lock); 1320 1321 /* 1322 * Make a copy of the communities which we can use to hold pointers 1323 * to the registers. 1324 */ 1325 pctrl->ncommunities = pctrl->soc->ncommunities; 1326 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1327 sizeof(*pctrl->communities), GFP_KERNEL); 1328 if (!pctrl->communities) 1329 return -ENOMEM; 1330 1331 for (i = 0; i < pctrl->ncommunities; i++) { 1332 struct intel_community *community = &pctrl->communities[i]; 1333 struct resource *res; 1334 void __iomem *regs; 1335 u32 padbar; 1336 1337 *community = pctrl->soc->communities[i]; 1338 1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 1340 community->barno); 1341 regs = devm_ioremap_resource(&pdev->dev, res); 1342 if (IS_ERR(regs)) 1343 return PTR_ERR(regs); 1344 1345 /* 1346 * Determine community features based on the revision if 1347 * not specified already. 1348 */ 1349 if (!community->features) { 1350 u32 rev; 1351 1352 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1353 if (rev >= 0x94) { 1354 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1355 community->features |= PINCTRL_FEATURE_1K_PD; 1356 } 1357 } 1358 1359 /* Read offset of the pad configuration registers */ 1360 padbar = readl(regs + PADBAR); 1361 1362 community->regs = regs; 1363 community->pad_regs = regs + padbar; 1364 1365 if (!community->is_offset) 1366 community->is_offset = GPI_IS; 1367 1368 ret = intel_pinctrl_add_padgroups(pctrl, community); 1369 if (ret) 1370 return ret; 1371 } 1372 1373 irq = platform_get_irq(pdev, 0); 1374 if (irq < 0) { 1375 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1376 return irq; 1377 } 1378 1379 ret = intel_pinctrl_pm_init(pctrl); 1380 if (ret) 1381 return ret; 1382 1383 pctrl->pctldesc = intel_pinctrl_desc; 1384 pctrl->pctldesc.name = dev_name(&pdev->dev); 1385 pctrl->pctldesc.pins = pctrl->soc->pins; 1386 pctrl->pctldesc.npins = pctrl->soc->npins; 1387 1388 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1389 pctrl); 1390 if (IS_ERR(pctrl->pctldev)) { 1391 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1392 return PTR_ERR(pctrl->pctldev); 1393 } 1394 1395 ret = intel_gpio_probe(pctrl, irq); 1396 if (ret) 1397 return ret; 1398 1399 platform_set_drvdata(pdev, pctrl); 1400 1401 return 0; 1402 } 1403 EXPORT_SYMBOL_GPL(intel_pinctrl_probe); 1404 1405 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1406 { 1407 const struct intel_pinctrl_soc_data *data; 1408 1409 data = device_get_match_data(&pdev->dev); 1410 return intel_pinctrl_probe(pdev, data); 1411 } 1412 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1413 1414 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1415 { 1416 const struct intel_pinctrl_soc_data *data = NULL; 1417 const struct intel_pinctrl_soc_data **table; 1418 struct acpi_device *adev; 1419 unsigned int i; 1420 1421 adev = ACPI_COMPANION(&pdev->dev); 1422 if (adev) { 1423 const void *match = device_get_match_data(&pdev->dev); 1424 1425 table = (const struct intel_pinctrl_soc_data **)match; 1426 for (i = 0; table[i]; i++) { 1427 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1428 data = table[i]; 1429 break; 1430 } 1431 } 1432 } else { 1433 const struct platform_device_id *id; 1434 1435 id = platform_get_device_id(pdev); 1436 if (!id) 1437 return -ENODEV; 1438 1439 table = (const struct intel_pinctrl_soc_data **)id->driver_data; 1440 data = table[pdev->id]; 1441 } 1442 if (!data) 1443 return -ENODEV; 1444 1445 return intel_pinctrl_probe(pdev, data); 1446 } 1447 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1448 1449 #ifdef CONFIG_PM_SLEEP 1450 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1451 { 1452 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1453 1454 if (!pd || !intel_pad_usable(pctrl, pin)) 1455 return false; 1456 1457 /* 1458 * Only restore the pin if it is actually in use by the kernel (or 1459 * by userspace). It is possible that some pins are used by the 1460 * BIOS during resume and those are not always locked down so leave 1461 * them alone. 1462 */ 1463 if (pd->mux_owner || pd->gpio_owner || 1464 gpiochip_line_is_irq(&pctrl->chip, pin)) 1465 return true; 1466 1467 return false; 1468 } 1469 1470 int intel_pinctrl_suspend(struct device *dev) 1471 { 1472 struct platform_device *pdev = to_platform_device(dev); 1473 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1474 struct intel_community_context *communities; 1475 struct intel_pad_context *pads; 1476 int i; 1477 1478 pads = pctrl->context.pads; 1479 for (i = 0; i < pctrl->soc->npins; i++) { 1480 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1481 void __iomem *padcfg; 1482 u32 val; 1483 1484 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1485 continue; 1486 1487 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1488 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1489 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1490 pads[i].padcfg1 = val; 1491 1492 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1493 if (padcfg) 1494 pads[i].padcfg2 = readl(padcfg); 1495 } 1496 1497 communities = pctrl->context.communities; 1498 for (i = 0; i < pctrl->ncommunities; i++) { 1499 struct intel_community *community = &pctrl->communities[i]; 1500 void __iomem *base; 1501 unsigned int gpp; 1502 1503 base = community->regs + community->ie_offset; 1504 for (gpp = 0; gpp < community->ngpps; gpp++) 1505 communities[i].intmask[gpp] = readl(base + gpp * 4); 1506 } 1507 1508 return 0; 1509 } 1510 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1511 1512 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1513 { 1514 size_t i; 1515 1516 for (i = 0; i < pctrl->ncommunities; i++) { 1517 const struct intel_community *community; 1518 void __iomem *base; 1519 unsigned int gpp; 1520 1521 community = &pctrl->communities[i]; 1522 base = community->regs; 1523 1524 for (gpp = 0; gpp < community->ngpps; gpp++) { 1525 /* Mask and clear all interrupts */ 1526 writel(0, base + community->ie_offset + gpp * 4); 1527 writel(0xffff, base + community->is_offset + gpp * 4); 1528 } 1529 } 1530 } 1531 1532 int intel_pinctrl_resume(struct device *dev) 1533 { 1534 struct platform_device *pdev = to_platform_device(dev); 1535 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1536 const struct intel_community_context *communities; 1537 const struct intel_pad_context *pads; 1538 int i; 1539 1540 /* Mask all interrupts */ 1541 intel_gpio_irq_init(pctrl); 1542 1543 pads = pctrl->context.pads; 1544 for (i = 0; i < pctrl->soc->npins; i++) { 1545 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1546 void __iomem *padcfg; 1547 u32 val; 1548 1549 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1550 continue; 1551 1552 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1553 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; 1554 if (val != pads[i].padcfg0) { 1555 writel(pads[i].padcfg0, padcfg); 1556 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", 1557 desc->number, readl(padcfg)); 1558 } 1559 1560 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); 1561 val = readl(padcfg); 1562 if (val != pads[i].padcfg1) { 1563 writel(pads[i].padcfg1, padcfg); 1564 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", 1565 desc->number, readl(padcfg)); 1566 } 1567 1568 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1569 if (padcfg) { 1570 val = readl(padcfg); 1571 if (val != pads[i].padcfg2) { 1572 writel(pads[i].padcfg2, padcfg); 1573 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", 1574 desc->number, readl(padcfg)); 1575 } 1576 } 1577 } 1578 1579 communities = pctrl->context.communities; 1580 for (i = 0; i < pctrl->ncommunities; i++) { 1581 struct intel_community *community = &pctrl->communities[i]; 1582 void __iomem *base; 1583 unsigned int gpp; 1584 1585 base = community->regs + community->ie_offset; 1586 for (gpp = 0; gpp < community->ngpps; gpp++) { 1587 writel(communities[i].intmask[gpp], base + gpp * 4); 1588 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1589 readl(base + gpp * 4)); 1590 } 1591 } 1592 1593 return 0; 1594 } 1595 EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1596 #endif 1597 1598 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1599 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1600 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1601 MODULE_LICENSE("GPL v2"); 1602