1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel pinctrl/GPIO core driver. 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/time.h> 18 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 24 #include "../core.h" 25 #include "pinctrl-intel.h" 26 27 /* Offset from regs */ 28 #define REVID 0x000 29 #define REVID_SHIFT 16 30 #define REVID_MASK GENMASK(31, 16) 31 32 #define PADBAR 0x00c 33 34 #define PADOWN_BITS 4 35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 36 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) 37 #define PADOWN_GPP(p) ((p) / 8) 38 39 /* Offset from pad_regs */ 40 #define PADCFG0 0x000 41 #define PADCFG0_RXEVCFG_SHIFT 25 42 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) 43 #define PADCFG0_RXEVCFG_LEVEL 0 44 #define PADCFG0_RXEVCFG_EDGE 1 45 #define PADCFG0_RXEVCFG_DISABLED 2 46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 47 #define PADCFG0_PREGFRXSEL BIT(24) 48 #define PADCFG0_RXINV BIT(23) 49 #define PADCFG0_GPIROUTIOXAPIC BIT(20) 50 #define PADCFG0_GPIROUTSCI BIT(19) 51 #define PADCFG0_GPIROUTSMI BIT(18) 52 #define PADCFG0_GPIROUTNMI BIT(17) 53 #define PADCFG0_PMODE_SHIFT 10 54 #define PADCFG0_PMODE_MASK GENMASK(13, 10) 55 #define PADCFG0_PMODE_GPIO 0 56 #define PADCFG0_GPIORXDIS BIT(9) 57 #define PADCFG0_GPIOTXDIS BIT(8) 58 #define PADCFG0_GPIORXSTATE BIT(1) 59 #define PADCFG0_GPIOTXSTATE BIT(0) 60 61 #define PADCFG1 0x004 62 #define PADCFG1_TERM_UP BIT(13) 63 #define PADCFG1_TERM_SHIFT 10 64 #define PADCFG1_TERM_MASK GENMASK(12, 10) 65 #define PADCFG1_TERM_20K 4 66 #define PADCFG1_TERM_2K 3 67 #define PADCFG1_TERM_5K 2 68 #define PADCFG1_TERM_1K 1 69 70 #define PADCFG2 0x008 71 #define PADCFG2_DEBEN BIT(0) 72 #define PADCFG2_DEBOUNCE_SHIFT 1 73 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) 74 75 #define DEBOUNCE_PERIOD_NSEC 31250 76 77 struct intel_pad_context { 78 u32 padcfg0; 79 u32 padcfg1; 80 u32 padcfg2; 81 }; 82 83 struct intel_community_context { 84 u32 *intmask; 85 u32 *hostown; 86 }; 87 88 #define pin_to_padno(c, p) ((p) - (c)->pin_base) 89 #define padgroup_offset(g, p) ((p) - (g)->base) 90 91 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, 92 unsigned int pin) 93 { 94 struct intel_community *community; 95 int i; 96 97 for (i = 0; i < pctrl->ncommunities; i++) { 98 community = &pctrl->communities[i]; 99 if (pin >= community->pin_base && 100 pin < community->pin_base + community->npins) 101 return community; 102 } 103 104 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); 105 return NULL; 106 } 107 108 static const struct intel_padgroup * 109 intel_community_get_padgroup(const struct intel_community *community, 110 unsigned int pin) 111 { 112 int i; 113 114 for (i = 0; i < community->ngpps; i++) { 115 const struct intel_padgroup *padgrp = &community->gpps[i]; 116 117 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) 118 return padgrp; 119 } 120 121 return NULL; 122 } 123 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, 125 unsigned int pin, unsigned int reg) 126 { 127 const struct intel_community *community; 128 unsigned int padno; 129 size_t nregs; 130 131 community = intel_get_community(pctrl, pin); 132 if (!community) 133 return NULL; 134 135 padno = pin_to_padno(community, pin); 136 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; 137 138 if (reg >= nregs * 4) 139 return NULL; 140 141 return community->pad_regs + reg + padno * nregs * 4; 142 } 143 144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) 145 { 146 const struct intel_community *community; 147 const struct intel_padgroup *padgrp; 148 unsigned int gpp, offset, gpp_offset; 149 void __iomem *padown; 150 151 community = intel_get_community(pctrl, pin); 152 if (!community) 153 return false; 154 if (!community->padown_offset) 155 return true; 156 157 padgrp = intel_community_get_padgroup(community, pin); 158 if (!padgrp) 159 return false; 160 161 gpp_offset = padgroup_offset(padgrp, pin); 162 gpp = PADOWN_GPP(gpp_offset); 163 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; 164 padown = community->regs + offset; 165 166 return !(readl(padown) & PADOWN_MASK(gpp_offset)); 167 } 168 169 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) 170 { 171 const struct intel_community *community; 172 const struct intel_padgroup *padgrp; 173 unsigned int offset, gpp_offset; 174 void __iomem *hostown; 175 176 community = intel_get_community(pctrl, pin); 177 if (!community) 178 return true; 179 if (!community->hostown_offset) 180 return false; 181 182 padgrp = intel_community_get_padgroup(community, pin); 183 if (!padgrp) 184 return true; 185 186 gpp_offset = padgroup_offset(padgrp, pin); 187 offset = community->hostown_offset + padgrp->reg_num * 4; 188 hostown = community->regs + offset; 189 190 return !(readl(hostown) & BIT(gpp_offset)); 191 } 192 193 /** 194 * enum - Locking variants of the pad configuration 195 * 196 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers 197 * @PAD_LOCKED: pad configuration registers, except TX state, are locked 198 * @PAD_LOCKED_TX: pad configuration TX state is locked 199 * @PAD_LOCKED_FULL: pad configuration registers are locked completely 200 * 201 * Locking is considered as read-only mode for corresponding registers and 202 * their respective fields. That said, TX state bit is locked separately from 203 * the main locking scheme. 204 */ 205 enum { 206 PAD_UNLOCKED = 0, 207 PAD_LOCKED = 1, 208 PAD_LOCKED_TX = 2, 209 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, 210 }; 211 212 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) 213 { 214 struct intel_community *community; 215 const struct intel_padgroup *padgrp; 216 unsigned int offset, gpp_offset; 217 u32 value; 218 int ret = PAD_UNLOCKED; 219 220 community = intel_get_community(pctrl, pin); 221 if (!community) 222 return PAD_LOCKED_FULL; 223 if (!community->padcfglock_offset) 224 return PAD_UNLOCKED; 225 226 padgrp = intel_community_get_padgroup(community, pin); 227 if (!padgrp) 228 return PAD_LOCKED_FULL; 229 230 gpp_offset = padgroup_offset(padgrp, pin); 231 232 /* 233 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, 234 * the pad is considered unlocked. Any other case means that it is 235 * either fully or partially locked. 236 */ 237 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; 238 value = readl(community->regs + offset); 239 if (value & BIT(gpp_offset)) 240 ret |= PAD_LOCKED; 241 242 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; 243 value = readl(community->regs + offset); 244 if (value & BIT(gpp_offset)) 245 ret |= PAD_LOCKED_TX; 246 247 return ret; 248 } 249 250 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) 251 { 252 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; 253 } 254 255 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) 256 { 257 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); 258 } 259 260 static int intel_get_groups_count(struct pinctrl_dev *pctldev) 261 { 262 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 263 264 return pctrl->soc->ngroups; 265 } 266 267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev, 268 unsigned int group) 269 { 270 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 271 272 return pctrl->soc->groups[group].name; 273 } 274 275 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 276 const unsigned int **pins, unsigned int *npins) 277 { 278 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 279 280 *pins = pctrl->soc->groups[group].pins; 281 *npins = pctrl->soc->groups[group].npins; 282 return 0; 283 } 284 285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 286 unsigned int pin) 287 { 288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 289 void __iomem *padcfg; 290 u32 cfg0, cfg1, mode; 291 int locked; 292 bool acpi; 293 294 if (!intel_pad_owned_by_host(pctrl, pin)) { 295 seq_puts(s, "not available"); 296 return; 297 } 298 299 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 300 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); 301 302 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 303 if (mode == PADCFG0_PMODE_GPIO) 304 seq_puts(s, "GPIO "); 305 else 306 seq_printf(s, "mode %d ", mode); 307 308 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 309 310 /* Dump the additional PADCFG registers if available */ 311 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); 312 if (padcfg) 313 seq_printf(s, " 0x%08x", readl(padcfg)); 314 315 locked = intel_pad_locked(pctrl, pin); 316 acpi = intel_pad_acpi_mode(pctrl, pin); 317 318 if (locked || acpi) { 319 seq_puts(s, " ["); 320 if (locked) 321 seq_puts(s, "LOCKED"); 322 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) 323 seq_puts(s, " tx"); 324 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) 325 seq_puts(s, " full"); 326 327 if (locked && acpi) 328 seq_puts(s, ", "); 329 330 if (acpi) 331 seq_puts(s, "ACPI"); 332 seq_puts(s, "]"); 333 } 334 } 335 336 static const struct pinctrl_ops intel_pinctrl_ops = { 337 .get_groups_count = intel_get_groups_count, 338 .get_group_name = intel_get_group_name, 339 .get_group_pins = intel_get_group_pins, 340 .pin_dbg_show = intel_pin_dbg_show, 341 }; 342 343 static int intel_get_functions_count(struct pinctrl_dev *pctldev) 344 { 345 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 346 347 return pctrl->soc->nfunctions; 348 } 349 350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev, 351 unsigned int function) 352 { 353 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 354 355 return pctrl->soc->functions[function].name; 356 } 357 358 static int intel_get_function_groups(struct pinctrl_dev *pctldev, 359 unsigned int function, 360 const char * const **groups, 361 unsigned int * const ngroups) 362 { 363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 364 365 *groups = pctrl->soc->functions[function].groups; 366 *ngroups = pctrl->soc->functions[function].ngroups; 367 return 0; 368 } 369 370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, 371 unsigned int function, unsigned int group) 372 { 373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 374 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; 375 unsigned long flags; 376 int i; 377 378 raw_spin_lock_irqsave(&pctrl->lock, flags); 379 380 /* 381 * All pins in the groups needs to be accessible and writable 382 * before we can enable the mux for this group. 383 */ 384 for (i = 0; i < grp->npins; i++) { 385 if (!intel_pad_usable(pctrl, grp->pins[i])) { 386 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 387 return -EBUSY; 388 } 389 } 390 391 /* Now enable the mux setting for each pin in the group */ 392 for (i = 0; i < grp->npins; i++) { 393 void __iomem *padcfg0; 394 u32 value; 395 396 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); 397 value = readl(padcfg0); 398 399 value &= ~PADCFG0_PMODE_MASK; 400 401 if (grp->modes) 402 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; 403 else 404 value |= grp->mode << PADCFG0_PMODE_SHIFT; 405 406 writel(value, padcfg0); 407 } 408 409 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 410 411 return 0; 412 } 413 414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 415 { 416 u32 value; 417 418 value = readl(padcfg0); 419 if (input) { 420 value &= ~PADCFG0_GPIORXDIS; 421 value |= PADCFG0_GPIOTXDIS; 422 } else { 423 value &= ~PADCFG0_GPIOTXDIS; 424 value |= PADCFG0_GPIORXDIS; 425 } 426 writel(value, padcfg0); 427 } 428 429 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 430 { 431 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 432 } 433 434 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) 435 { 436 u32 value; 437 438 value = readl(padcfg0); 439 440 /* Put the pad into GPIO mode */ 441 value &= ~PADCFG0_PMODE_MASK; 442 value |= PADCFG0_PMODE_GPIO; 443 444 /* Disable input and output buffers */ 445 value &= ~PADCFG0_GPIORXDIS; 446 value &= ~PADCFG0_GPIOTXDIS; 447 448 /* Disable SCI/SMI/NMI generation */ 449 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); 450 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); 451 452 writel(value, padcfg0); 453 } 454 455 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 456 struct pinctrl_gpio_range *range, 457 unsigned int pin) 458 { 459 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 460 void __iomem *padcfg0; 461 unsigned long flags; 462 463 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 464 465 raw_spin_lock_irqsave(&pctrl->lock, flags); 466 467 if (!intel_pad_owned_by_host(pctrl, pin)) { 468 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 469 return -EBUSY; 470 } 471 472 if (!intel_pad_is_unlocked(pctrl, pin)) { 473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 474 return 0; 475 } 476 477 /* 478 * If pin is already configured in GPIO mode, we assume that 479 * firmware provides correct settings. In such case we avoid 480 * potential glitches on the pin. Otherwise, for the pin in 481 * alternative mode, consumer has to supply respective flags. 482 */ 483 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { 484 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 485 return 0; 486 } 487 488 intel_gpio_set_gpio_mode(padcfg0); 489 490 /* Disable TX buffer and enable RX (this will be input) */ 491 __intel_gpio_set_direction(padcfg0, true); 492 493 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 494 495 return 0; 496 } 497 498 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, 499 struct pinctrl_gpio_range *range, 500 unsigned int pin, bool input) 501 { 502 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 503 void __iomem *padcfg0; 504 unsigned long flags; 505 506 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 507 508 raw_spin_lock_irqsave(&pctrl->lock, flags); 509 __intel_gpio_set_direction(padcfg0, input); 510 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 511 512 return 0; 513 } 514 515 static const struct pinmux_ops intel_pinmux_ops = { 516 .get_functions_count = intel_get_functions_count, 517 .get_function_name = intel_get_function_name, 518 .get_function_groups = intel_get_function_groups, 519 .set_mux = intel_pinmux_set_mux, 520 .gpio_request_enable = intel_gpio_request_enable, 521 .gpio_set_direction = intel_gpio_set_direction, 522 }; 523 524 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, 525 enum pin_config_param param, u32 *arg) 526 { 527 const struct intel_community *community; 528 void __iomem *padcfg1; 529 unsigned long flags; 530 u32 value, term; 531 532 community = intel_get_community(pctrl, pin); 533 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 534 535 raw_spin_lock_irqsave(&pctrl->lock, flags); 536 value = readl(padcfg1); 537 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 538 539 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; 540 541 switch (param) { 542 case PIN_CONFIG_BIAS_DISABLE: 543 if (term) 544 return -EINVAL; 545 break; 546 547 case PIN_CONFIG_BIAS_PULL_UP: 548 if (!term || !(value & PADCFG1_TERM_UP)) 549 return -EINVAL; 550 551 switch (term) { 552 case PADCFG1_TERM_1K: 553 *arg = 1000; 554 break; 555 case PADCFG1_TERM_2K: 556 *arg = 2000; 557 break; 558 case PADCFG1_TERM_5K: 559 *arg = 5000; 560 break; 561 case PADCFG1_TERM_20K: 562 *arg = 20000; 563 break; 564 } 565 566 break; 567 568 case PIN_CONFIG_BIAS_PULL_DOWN: 569 if (!term || value & PADCFG1_TERM_UP) 570 return -EINVAL; 571 572 switch (term) { 573 case PADCFG1_TERM_1K: 574 if (!(community->features & PINCTRL_FEATURE_1K_PD)) 575 return -EINVAL; 576 *arg = 1000; 577 break; 578 case PADCFG1_TERM_5K: 579 *arg = 5000; 580 break; 581 case PADCFG1_TERM_20K: 582 *arg = 20000; 583 break; 584 } 585 586 break; 587 588 default: 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 595 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, 596 enum pin_config_param param, u32 *arg) 597 { 598 void __iomem *padcfg2; 599 unsigned long flags; 600 unsigned long v; 601 u32 value2; 602 603 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 604 if (!padcfg2) 605 return -ENOTSUPP; 606 607 raw_spin_lock_irqsave(&pctrl->lock, flags); 608 value2 = readl(padcfg2); 609 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 610 if (!(value2 & PADCFG2_DEBEN)) 611 return -EINVAL; 612 613 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; 614 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; 615 616 return 0; 617 } 618 619 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 620 unsigned long *config) 621 { 622 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 623 enum pin_config_param param = pinconf_to_config_param(*config); 624 u32 arg = 0; 625 int ret; 626 627 if (!intel_pad_owned_by_host(pctrl, pin)) 628 return -ENOTSUPP; 629 630 switch (param) { 631 case PIN_CONFIG_BIAS_DISABLE: 632 case PIN_CONFIG_BIAS_PULL_UP: 633 case PIN_CONFIG_BIAS_PULL_DOWN: 634 ret = intel_config_get_pull(pctrl, pin, param, &arg); 635 if (ret) 636 return ret; 637 break; 638 639 case PIN_CONFIG_INPUT_DEBOUNCE: 640 ret = intel_config_get_debounce(pctrl, pin, param, &arg); 641 if (ret) 642 return ret; 643 break; 644 645 default: 646 return -ENOTSUPP; 647 } 648 649 *config = pinconf_to_config_packed(param, arg); 650 return 0; 651 } 652 653 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 654 unsigned long config) 655 { 656 unsigned int param = pinconf_to_config_param(config); 657 unsigned int arg = pinconf_to_config_argument(config); 658 const struct intel_community *community; 659 void __iomem *padcfg1; 660 unsigned long flags; 661 int ret = 0; 662 u32 value; 663 664 community = intel_get_community(pctrl, pin); 665 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); 666 667 raw_spin_lock_irqsave(&pctrl->lock, flags); 668 669 value = readl(padcfg1); 670 671 switch (param) { 672 case PIN_CONFIG_BIAS_DISABLE: 673 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); 674 break; 675 676 case PIN_CONFIG_BIAS_PULL_UP: 677 value &= ~PADCFG1_TERM_MASK; 678 679 value |= PADCFG1_TERM_UP; 680 681 switch (arg) { 682 case 20000: 683 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 684 break; 685 case 5000: 686 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 687 break; 688 case 2000: 689 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; 690 break; 691 case 1000: 692 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 693 break; 694 default: 695 ret = -EINVAL; 696 } 697 698 break; 699 700 case PIN_CONFIG_BIAS_PULL_DOWN: 701 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); 702 703 switch (arg) { 704 case 20000: 705 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; 706 break; 707 case 5000: 708 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; 709 break; 710 case 1000: 711 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { 712 ret = -EINVAL; 713 break; 714 } 715 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; 716 break; 717 default: 718 ret = -EINVAL; 719 } 720 721 break; 722 } 723 724 if (!ret) 725 writel(value, padcfg1); 726 727 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 728 729 return ret; 730 } 731 732 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, 733 unsigned int pin, unsigned int debounce) 734 { 735 void __iomem *padcfg0, *padcfg2; 736 unsigned long flags; 737 u32 value0, value2; 738 739 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); 740 if (!padcfg2) 741 return -ENOTSUPP; 742 743 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); 744 745 raw_spin_lock_irqsave(&pctrl->lock, flags); 746 747 value0 = readl(padcfg0); 748 value2 = readl(padcfg2); 749 750 /* Disable glitch filter and debouncer */ 751 value0 &= ~PADCFG0_PREGFRXSEL; 752 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); 753 754 if (debounce) { 755 unsigned long v; 756 757 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); 758 if (v < 3 || v > 15) { 759 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 760 return -EINVAL; 761 } 762 763 /* Enable glitch filter and debouncer */ 764 value0 |= PADCFG0_PREGFRXSEL; 765 value2 |= v << PADCFG2_DEBOUNCE_SHIFT; 766 value2 |= PADCFG2_DEBEN; 767 } 768 769 writel(value0, padcfg0); 770 writel(value2, padcfg2); 771 772 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 773 774 return 0; 775 } 776 777 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 778 unsigned long *configs, unsigned int nconfigs) 779 { 780 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 781 int i, ret; 782 783 if (!intel_pad_usable(pctrl, pin)) 784 return -ENOTSUPP; 785 786 for (i = 0; i < nconfigs; i++) { 787 switch (pinconf_to_config_param(configs[i])) { 788 case PIN_CONFIG_BIAS_DISABLE: 789 case PIN_CONFIG_BIAS_PULL_UP: 790 case PIN_CONFIG_BIAS_PULL_DOWN: 791 ret = intel_config_set_pull(pctrl, pin, configs[i]); 792 if (ret) 793 return ret; 794 break; 795 796 case PIN_CONFIG_INPUT_DEBOUNCE: 797 ret = intel_config_set_debounce(pctrl, pin, 798 pinconf_to_config_argument(configs[i])); 799 if (ret) 800 return ret; 801 break; 802 803 default: 804 return -ENOTSUPP; 805 } 806 } 807 808 return 0; 809 } 810 811 static const struct pinconf_ops intel_pinconf_ops = { 812 .is_generic = true, 813 .pin_config_get = intel_config_get, 814 .pin_config_set = intel_config_set, 815 }; 816 817 static const struct pinctrl_desc intel_pinctrl_desc = { 818 .pctlops = &intel_pinctrl_ops, 819 .pmxops = &intel_pinmux_ops, 820 .confops = &intel_pinconf_ops, 821 .owner = THIS_MODULE, 822 }; 823 824 /** 825 * intel_gpio_to_pin() - Translate from GPIO offset to pin number 826 * @pctrl: Pinctrl structure 827 * @offset: GPIO offset from gpiolib 828 * @community: Community is filled here if not %NULL 829 * @padgrp: Pad group is filled here if not %NULL 830 * 831 * When coming through gpiolib irqchip, the GPIO offset is not 832 * automatically translated to pinctrl pin number. This function can be 833 * used to find out the corresponding pinctrl pin. 834 */ 835 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, 836 const struct intel_community **community, 837 const struct intel_padgroup **padgrp) 838 { 839 int i; 840 841 for (i = 0; i < pctrl->ncommunities; i++) { 842 const struct intel_community *comm = &pctrl->communities[i]; 843 int j; 844 845 for (j = 0; j < comm->ngpps; j++) { 846 const struct intel_padgroup *pgrp = &comm->gpps[j]; 847 848 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 849 continue; 850 851 if (offset >= pgrp->gpio_base && 852 offset < pgrp->gpio_base + pgrp->size) { 853 int pin; 854 855 pin = pgrp->base + offset - pgrp->gpio_base; 856 if (community) 857 *community = comm; 858 if (padgrp) 859 *padgrp = pgrp; 860 861 return pin; 862 } 863 } 864 } 865 866 return -EINVAL; 867 } 868 869 /** 870 * intel_pin_to_gpio() - Translate from pin number to GPIO offset 871 * @pctrl: Pinctrl structure 872 * @pin: pin number 873 * 874 * Translate the pin number of pinctrl to GPIO offset 875 */ 876 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) 877 { 878 const struct intel_community *community; 879 const struct intel_padgroup *padgrp; 880 881 community = intel_get_community(pctrl, pin); 882 if (!community) 883 return -EINVAL; 884 885 padgrp = intel_community_get_padgroup(community, pin); 886 if (!padgrp) 887 return -EINVAL; 888 889 return pin - padgrp->base + padgrp->gpio_base; 890 } 891 892 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) 893 { 894 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 895 void __iomem *reg; 896 u32 padcfg0; 897 int pin; 898 899 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 900 if (pin < 0) 901 return -EINVAL; 902 903 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 904 if (!reg) 905 return -EINVAL; 906 907 padcfg0 = readl(reg); 908 if (!(padcfg0 & PADCFG0_GPIOTXDIS)) 909 return !!(padcfg0 & PADCFG0_GPIOTXSTATE); 910 911 return !!(padcfg0 & PADCFG0_GPIORXSTATE); 912 } 913 914 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, 915 int value) 916 { 917 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 918 unsigned long flags; 919 void __iomem *reg; 920 u32 padcfg0; 921 int pin; 922 923 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 924 if (pin < 0) 925 return; 926 927 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 928 if (!reg) 929 return; 930 931 raw_spin_lock_irqsave(&pctrl->lock, flags); 932 padcfg0 = readl(reg); 933 if (value) 934 padcfg0 |= PADCFG0_GPIOTXSTATE; 935 else 936 padcfg0 &= ~PADCFG0_GPIOTXSTATE; 937 writel(padcfg0, reg); 938 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 939 } 940 941 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 942 { 943 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 944 unsigned long flags; 945 void __iomem *reg; 946 u32 padcfg0; 947 int pin; 948 949 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); 950 if (pin < 0) 951 return -EINVAL; 952 953 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 954 if (!reg) 955 return -EINVAL; 956 957 raw_spin_lock_irqsave(&pctrl->lock, flags); 958 padcfg0 = readl(reg); 959 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 960 if (padcfg0 & PADCFG0_PMODE_MASK) 961 return -EINVAL; 962 963 if (padcfg0 & PADCFG0_GPIOTXDIS) 964 return GPIO_LINE_DIRECTION_IN; 965 966 return GPIO_LINE_DIRECTION_OUT; 967 } 968 969 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 970 { 971 return pinctrl_gpio_direction_input(chip->base + offset); 972 } 973 974 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 975 int value) 976 { 977 intel_gpio_set(chip, offset, value); 978 return pinctrl_gpio_direction_output(chip->base + offset); 979 } 980 981 static const struct gpio_chip intel_gpio_chip = { 982 .owner = THIS_MODULE, 983 .request = gpiochip_generic_request, 984 .free = gpiochip_generic_free, 985 .get_direction = intel_gpio_get_direction, 986 .direction_input = intel_gpio_direction_input, 987 .direction_output = intel_gpio_direction_output, 988 .get = intel_gpio_get, 989 .set = intel_gpio_set, 990 .set_config = gpiochip_generic_config, 991 }; 992 993 static void intel_gpio_irq_ack(struct irq_data *d) 994 { 995 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 996 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 997 const struct intel_community *community; 998 const struct intel_padgroup *padgrp; 999 int pin; 1000 1001 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1002 if (pin >= 0) { 1003 unsigned int gpp, gpp_offset, is_offset; 1004 1005 gpp = padgrp->reg_num; 1006 gpp_offset = padgroup_offset(padgrp, pin); 1007 is_offset = community->is_offset + gpp * 4; 1008 1009 raw_spin_lock(&pctrl->lock); 1010 writel(BIT(gpp_offset), community->regs + is_offset); 1011 raw_spin_unlock(&pctrl->lock); 1012 } 1013 } 1014 1015 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1016 { 1017 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1018 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1019 const struct intel_community *community; 1020 const struct intel_padgroup *padgrp; 1021 int pin; 1022 1023 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); 1024 if (pin >= 0) { 1025 unsigned int gpp, gpp_offset; 1026 unsigned long flags; 1027 void __iomem *reg, *is; 1028 u32 value; 1029 1030 gpp = padgrp->reg_num; 1031 gpp_offset = padgroup_offset(padgrp, pin); 1032 1033 reg = community->regs + community->ie_offset + gpp * 4; 1034 is = community->regs + community->is_offset + gpp * 4; 1035 1036 raw_spin_lock_irqsave(&pctrl->lock, flags); 1037 1038 /* Clear interrupt status first to avoid unexpected interrupt */ 1039 writel(BIT(gpp_offset), is); 1040 1041 value = readl(reg); 1042 if (mask) 1043 value &= ~BIT(gpp_offset); 1044 else 1045 value |= BIT(gpp_offset); 1046 writel(value, reg); 1047 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1048 } 1049 } 1050 1051 static void intel_gpio_irq_mask(struct irq_data *d) 1052 { 1053 intel_gpio_irq_mask_unmask(d, true); 1054 } 1055 1056 static void intel_gpio_irq_unmask(struct irq_data *d) 1057 { 1058 intel_gpio_irq_mask_unmask(d, false); 1059 } 1060 1061 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) 1062 { 1063 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1064 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1065 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1066 unsigned long flags; 1067 void __iomem *reg; 1068 u32 value; 1069 1070 reg = intel_get_padcfg(pctrl, pin, PADCFG0); 1071 if (!reg) 1072 return -EINVAL; 1073 1074 /* 1075 * If the pin is in ACPI mode it is still usable as a GPIO but it 1076 * cannot be used as IRQ because GPI_IS status bit will not be 1077 * updated by the host controller hardware. 1078 */ 1079 if (intel_pad_acpi_mode(pctrl, pin)) { 1080 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); 1081 return -EPERM; 1082 } 1083 1084 raw_spin_lock_irqsave(&pctrl->lock, flags); 1085 1086 intel_gpio_set_gpio_mode(reg); 1087 1088 /* Disable TX buffer and enable RX (this will be input) */ 1089 __intel_gpio_set_direction(reg, true); 1090 1091 value = readl(reg); 1092 1093 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); 1094 1095 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 1096 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; 1097 } else if (type & IRQ_TYPE_EDGE_FALLING) { 1098 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1099 value |= PADCFG0_RXINV; 1100 } else if (type & IRQ_TYPE_EDGE_RISING) { 1101 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; 1102 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1103 if (type & IRQ_TYPE_LEVEL_LOW) 1104 value |= PADCFG0_RXINV; 1105 } else { 1106 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; 1107 } 1108 1109 writel(value, reg); 1110 1111 if (type & IRQ_TYPE_EDGE_BOTH) 1112 irq_set_handler_locked(d, handle_edge_irq); 1113 else if (type & IRQ_TYPE_LEVEL_MASK) 1114 irq_set_handler_locked(d, handle_level_irq); 1115 1116 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1117 1118 return 0; 1119 } 1120 1121 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) 1122 { 1123 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1124 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1125 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 1126 1127 if (on) 1128 enable_irq_wake(pctrl->irq); 1129 else 1130 disable_irq_wake(pctrl->irq); 1131 1132 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); 1133 return 0; 1134 } 1135 1136 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 1137 const struct intel_community *community) 1138 { 1139 struct gpio_chip *gc = &pctrl->chip; 1140 unsigned int gpp; 1141 int ret = 0; 1142 1143 for (gpp = 0; gpp < community->ngpps; gpp++) { 1144 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1145 unsigned long pending, enabled, gpp_offset; 1146 unsigned long flags; 1147 1148 raw_spin_lock_irqsave(&pctrl->lock, flags); 1149 1150 pending = readl(community->regs + community->is_offset + 1151 padgrp->reg_num * 4); 1152 enabled = readl(community->regs + community->ie_offset + 1153 padgrp->reg_num * 4); 1154 1155 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1156 1157 /* Only interrupts that are enabled */ 1158 pending &= enabled; 1159 1160 for_each_set_bit(gpp_offset, &pending, padgrp->size) { 1161 unsigned int irq; 1162 1163 irq = irq_find_mapping(gc->irq.domain, 1164 padgrp->gpio_base + gpp_offset); 1165 generic_handle_irq(irq); 1166 } 1167 1168 ret += pending ? 1 : 0; 1169 } 1170 1171 return ret; 1172 } 1173 1174 static irqreturn_t intel_gpio_irq(int irq, void *data) 1175 { 1176 const struct intel_community *community; 1177 struct intel_pinctrl *pctrl = data; 1178 unsigned int i; 1179 int ret = 0; 1180 1181 /* Need to check all communities for pending interrupts */ 1182 for (i = 0; i < pctrl->ncommunities; i++) { 1183 community = &pctrl->communities[i]; 1184 ret += intel_gpio_community_irq_handler(pctrl, community); 1185 } 1186 1187 return IRQ_RETVAL(ret); 1188 } 1189 1190 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, 1191 const struct intel_community *community) 1192 { 1193 int ret = 0, i; 1194 1195 for (i = 0; i < community->ngpps; i++) { 1196 const struct intel_padgroup *gpp = &community->gpps[i]; 1197 1198 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1199 continue; 1200 1201 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1202 gpp->gpio_base, gpp->base, 1203 gpp->size); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 return ret; 1209 } 1210 1211 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1212 { 1213 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1214 int ret, i; 1215 1216 for (i = 0; i < pctrl->ncommunities; i++) { 1217 struct intel_community *community = &pctrl->communities[i]; 1218 1219 ret = intel_gpio_add_community_ranges(pctrl, community); 1220 if (ret) { 1221 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1222 return ret; 1223 } 1224 } 1225 1226 return 0; 1227 } 1228 1229 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1230 { 1231 const struct intel_community *community; 1232 unsigned int ngpio = 0; 1233 int i, j; 1234 1235 for (i = 0; i < pctrl->ncommunities; i++) { 1236 community = &pctrl->communities[i]; 1237 for (j = 0; j < community->ngpps; j++) { 1238 const struct intel_padgroup *gpp = &community->gpps[j]; 1239 1240 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1241 continue; 1242 1243 if (gpp->gpio_base + gpp->size > ngpio) 1244 ngpio = gpp->gpio_base + gpp->size; 1245 } 1246 } 1247 1248 return ngpio; 1249 } 1250 1251 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1252 { 1253 int ret; 1254 struct gpio_irq_chip *girq; 1255 1256 pctrl->chip = intel_gpio_chip; 1257 1258 /* Setup GPIO chip */ 1259 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); 1260 pctrl->chip.label = dev_name(pctrl->dev); 1261 pctrl->chip.parent = pctrl->dev; 1262 pctrl->chip.base = -1; 1263 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; 1264 pctrl->irq = irq; 1265 1266 /* Setup IRQ chip */ 1267 pctrl->irqchip.name = dev_name(pctrl->dev); 1268 pctrl->irqchip.irq_ack = intel_gpio_irq_ack; 1269 pctrl->irqchip.irq_mask = intel_gpio_irq_mask; 1270 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask; 1271 pctrl->irqchip.irq_set_type = intel_gpio_irq_type; 1272 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake; 1273 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; 1274 1275 /* 1276 * On some platforms several GPIO controllers share the same interrupt 1277 * line. 1278 */ 1279 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1280 IRQF_SHARED | IRQF_NO_THREAD, 1281 dev_name(pctrl->dev), pctrl); 1282 if (ret) { 1283 dev_err(pctrl->dev, "failed to request interrupt\n"); 1284 return ret; 1285 } 1286 1287 girq = &pctrl->chip.irq; 1288 girq->chip = &pctrl->irqchip; 1289 /* This will let us handle the IRQ in the driver */ 1290 girq->parent_handler = NULL; 1291 girq->num_parents = 0; 1292 girq->default_type = IRQ_TYPE_NONE; 1293 girq->handler = handle_bad_irq; 1294 1295 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1296 if (ret) { 1297 dev_err(pctrl->dev, "failed to register gpiochip\n"); 1298 return ret; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, 1305 struct intel_community *community) 1306 { 1307 struct intel_padgroup *gpps; 1308 unsigned int npins = community->npins; 1309 unsigned int padown_num = 0; 1310 size_t ngpps, i; 1311 1312 if (community->gpps) 1313 ngpps = community->ngpps; 1314 else 1315 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); 1316 1317 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); 1318 if (!gpps) 1319 return -ENOMEM; 1320 1321 for (i = 0; i < ngpps; i++) { 1322 if (community->gpps) { 1323 gpps[i] = community->gpps[i]; 1324 } else { 1325 unsigned int gpp_size = community->gpp_size; 1326 1327 gpps[i].reg_num = i; 1328 gpps[i].base = community->pin_base + i * gpp_size; 1329 gpps[i].size = min(gpp_size, npins); 1330 npins -= gpps[i].size; 1331 } 1332 1333 if (gpps[i].size > 32) 1334 return -EINVAL; 1335 1336 /* Special treatment for GPIO base */ 1337 switch (gpps[i].gpio_base) { 1338 case INTEL_GPIO_BASE_MATCH: 1339 gpps[i].gpio_base = gpps[i].base; 1340 break; 1341 case INTEL_GPIO_BASE_ZERO: 1342 gpps[i].gpio_base = 0; 1343 break; 1344 case INTEL_GPIO_BASE_NOMAP: 1345 default: 1346 break; 1347 } 1348 1349 gpps[i].padown_num = padown_num; 1350 1351 /* 1352 * In older hardware the number of padown registers per 1353 * group is fixed regardless of the group size. 1354 */ 1355 if (community->gpp_num_padown_regs) 1356 padown_num += community->gpp_num_padown_regs; 1357 else 1358 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); 1359 } 1360 1361 community->ngpps = ngpps; 1362 community->gpps = gpps; 1363 1364 return 0; 1365 } 1366 1367 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 1368 { 1369 #ifdef CONFIG_PM_SLEEP 1370 const struct intel_pinctrl_soc_data *soc = pctrl->soc; 1371 struct intel_community_context *communities; 1372 struct intel_pad_context *pads; 1373 int i; 1374 1375 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); 1376 if (!pads) 1377 return -ENOMEM; 1378 1379 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, 1380 sizeof(*communities), GFP_KERNEL); 1381 if (!communities) 1382 return -ENOMEM; 1383 1384 1385 for (i = 0; i < pctrl->ncommunities; i++) { 1386 struct intel_community *community = &pctrl->communities[i]; 1387 u32 *intmask, *hostown; 1388 1389 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1390 sizeof(*intmask), GFP_KERNEL); 1391 if (!intmask) 1392 return -ENOMEM; 1393 1394 communities[i].intmask = intmask; 1395 1396 hostown = devm_kcalloc(pctrl->dev, community->ngpps, 1397 sizeof(*hostown), GFP_KERNEL); 1398 if (!hostown) 1399 return -ENOMEM; 1400 1401 communities[i].hostown = hostown; 1402 } 1403 1404 pctrl->context.pads = pads; 1405 pctrl->context.communities = communities; 1406 #endif 1407 1408 return 0; 1409 } 1410 1411 static int intel_pinctrl_probe(struct platform_device *pdev, 1412 const struct intel_pinctrl_soc_data *soc_data) 1413 { 1414 struct intel_pinctrl *pctrl; 1415 int i, ret, irq; 1416 1417 if (!soc_data) 1418 return -EINVAL; 1419 1420 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1421 if (!pctrl) 1422 return -ENOMEM; 1423 1424 pctrl->dev = &pdev->dev; 1425 pctrl->soc = soc_data; 1426 raw_spin_lock_init(&pctrl->lock); 1427 1428 /* 1429 * Make a copy of the communities which we can use to hold pointers 1430 * to the registers. 1431 */ 1432 pctrl->ncommunities = pctrl->soc->ncommunities; 1433 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, 1434 sizeof(*pctrl->communities), GFP_KERNEL); 1435 if (!pctrl->communities) 1436 return -ENOMEM; 1437 1438 for (i = 0; i < pctrl->ncommunities; i++) { 1439 struct intel_community *community = &pctrl->communities[i]; 1440 void __iomem *regs; 1441 u32 padbar; 1442 1443 *community = pctrl->soc->communities[i]; 1444 1445 regs = devm_platform_ioremap_resource(pdev, community->barno); 1446 if (IS_ERR(regs)) 1447 return PTR_ERR(regs); 1448 1449 /* 1450 * Determine community features based on the revision if 1451 * not specified already. 1452 */ 1453 if (!community->features) { 1454 u32 rev; 1455 1456 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; 1457 if (rev >= 0x94) { 1458 community->features |= PINCTRL_FEATURE_DEBOUNCE; 1459 community->features |= PINCTRL_FEATURE_1K_PD; 1460 } 1461 } 1462 1463 /* Read offset of the pad configuration registers */ 1464 padbar = readl(regs + PADBAR); 1465 1466 community->regs = regs; 1467 community->pad_regs = regs + padbar; 1468 1469 ret = intel_pinctrl_add_padgroups(pctrl, community); 1470 if (ret) 1471 return ret; 1472 } 1473 1474 irq = platform_get_irq(pdev, 0); 1475 if (irq < 0) 1476 return irq; 1477 1478 ret = intel_pinctrl_pm_init(pctrl); 1479 if (ret) 1480 return ret; 1481 1482 pctrl->pctldesc = intel_pinctrl_desc; 1483 pctrl->pctldesc.name = dev_name(&pdev->dev); 1484 pctrl->pctldesc.pins = pctrl->soc->pins; 1485 pctrl->pctldesc.npins = pctrl->soc->npins; 1486 1487 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1488 pctrl); 1489 if (IS_ERR(pctrl->pctldev)) { 1490 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1491 return PTR_ERR(pctrl->pctldev); 1492 } 1493 1494 ret = intel_gpio_probe(pctrl, irq); 1495 if (ret) 1496 return ret; 1497 1498 platform_set_drvdata(pdev, pctrl); 1499 1500 return 0; 1501 } 1502 1503 int intel_pinctrl_probe_by_hid(struct platform_device *pdev) 1504 { 1505 const struct intel_pinctrl_soc_data *data; 1506 1507 data = device_get_match_data(&pdev->dev); 1508 return intel_pinctrl_probe(pdev, data); 1509 } 1510 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); 1511 1512 int intel_pinctrl_probe_by_uid(struct platform_device *pdev) 1513 { 1514 const struct intel_pinctrl_soc_data *data = NULL; 1515 const struct intel_pinctrl_soc_data **table; 1516 struct acpi_device *adev; 1517 unsigned int i; 1518 1519 adev = ACPI_COMPANION(&pdev->dev); 1520 if (adev) { 1521 const void *match = device_get_match_data(&pdev->dev); 1522 1523 table = (const struct intel_pinctrl_soc_data **)match; 1524 for (i = 0; table[i]; i++) { 1525 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { 1526 data = table[i]; 1527 break; 1528 } 1529 } 1530 } else { 1531 const struct platform_device_id *id; 1532 1533 id = platform_get_device_id(pdev); 1534 if (!id) 1535 return -ENODEV; 1536 1537 table = (const struct intel_pinctrl_soc_data **)id->driver_data; 1538 data = table[pdev->id]; 1539 } 1540 1541 return intel_pinctrl_probe(pdev, data); 1542 } 1543 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); 1544 1545 #ifdef CONFIG_PM_SLEEP 1546 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1547 { 1548 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1549 1550 if (!pd || !intel_pad_usable(pctrl, pin)) 1551 return false; 1552 1553 /* 1554 * Only restore the pin if it is actually in use by the kernel (or 1555 * by userspace). It is possible that some pins are used by the 1556 * BIOS during resume and those are not always locked down so leave 1557 * them alone. 1558 */ 1559 if (pd->mux_owner || pd->gpio_owner || 1560 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1561 return true; 1562 1563 return false; 1564 } 1565 1566 int intel_pinctrl_suspend_noirq(struct device *dev) 1567 { 1568 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1569 struct intel_community_context *communities; 1570 struct intel_pad_context *pads; 1571 int i; 1572 1573 pads = pctrl->context.pads; 1574 for (i = 0; i < pctrl->soc->npins; i++) { 1575 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1576 void __iomem *padcfg; 1577 u32 val; 1578 1579 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1580 continue; 1581 1582 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1583 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; 1584 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); 1585 pads[i].padcfg1 = val; 1586 1587 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); 1588 if (padcfg) 1589 pads[i].padcfg2 = readl(padcfg); 1590 } 1591 1592 communities = pctrl->context.communities; 1593 for (i = 0; i < pctrl->ncommunities; i++) { 1594 struct intel_community *community = &pctrl->communities[i]; 1595 void __iomem *base; 1596 unsigned int gpp; 1597 1598 base = community->regs + community->ie_offset; 1599 for (gpp = 0; gpp < community->ngpps; gpp++) 1600 communities[i].intmask[gpp] = readl(base + gpp * 4); 1601 1602 base = community->regs + community->hostown_offset; 1603 for (gpp = 0; gpp < community->ngpps; gpp++) 1604 communities[i].hostown[gpp] = readl(base + gpp * 4); 1605 } 1606 1607 return 0; 1608 } 1609 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); 1610 1611 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1612 { 1613 size_t i; 1614 1615 for (i = 0; i < pctrl->ncommunities; i++) { 1616 const struct intel_community *community; 1617 void __iomem *base; 1618 unsigned int gpp; 1619 1620 community = &pctrl->communities[i]; 1621 base = community->regs; 1622 1623 for (gpp = 0; gpp < community->ngpps; gpp++) { 1624 /* Mask and clear all interrupts */ 1625 writel(0, base + community->ie_offset + gpp * 4); 1626 writel(0xffff, base + community->is_offset + gpp * 4); 1627 } 1628 } 1629 } 1630 1631 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) 1632 { 1633 u32 curr, updated; 1634 1635 curr = readl(reg); 1636 1637 updated = (curr & ~mask) | (value & mask); 1638 if (curr == updated) 1639 return false; 1640 1641 writel(updated, reg); 1642 return true; 1643 } 1644 1645 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, 1646 void __iomem *base, unsigned int gpp, u32 saved) 1647 { 1648 const struct intel_community *community = &pctrl->communities[c]; 1649 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 1650 struct device *dev = pctrl->dev; 1651 const char *dummy; 1652 u32 requested = 0; 1653 unsigned int i; 1654 1655 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) 1656 return; 1657 1658 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) 1659 requested |= BIT(i); 1660 1661 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) 1662 return; 1663 1664 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1665 } 1666 1667 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, 1668 void __iomem *base, unsigned int gpp, u32 saved) 1669 { 1670 struct device *dev = pctrl->dev; 1671 1672 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) 1673 return; 1674 1675 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); 1676 } 1677 1678 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, 1679 unsigned int reg, u32 saved) 1680 { 1681 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; 1682 unsigned int n = reg / sizeof(u32); 1683 struct device *dev = pctrl->dev; 1684 void __iomem *padcfg; 1685 1686 padcfg = intel_get_padcfg(pctrl, pin, reg); 1687 if (!padcfg) 1688 return; 1689 1690 if (!intel_gpio_update_reg(padcfg, ~mask, saved)) 1691 return; 1692 1693 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); 1694 } 1695 1696 int intel_pinctrl_resume_noirq(struct device *dev) 1697 { 1698 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1699 const struct intel_community_context *communities; 1700 const struct intel_pad_context *pads; 1701 int i; 1702 1703 /* Mask all interrupts */ 1704 intel_gpio_irq_init(pctrl); 1705 1706 pads = pctrl->context.pads; 1707 for (i = 0; i < pctrl->soc->npins; i++) { 1708 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1709 1710 if (!intel_pinctrl_should_save(pctrl, desc->number)) 1711 continue; 1712 1713 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); 1714 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); 1715 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); 1716 } 1717 1718 communities = pctrl->context.communities; 1719 for (i = 0; i < pctrl->ncommunities; i++) { 1720 struct intel_community *community = &pctrl->communities[i]; 1721 void __iomem *base; 1722 unsigned int gpp; 1723 1724 base = community->regs + community->ie_offset; 1725 for (gpp = 0; gpp < community->ngpps; gpp++) 1726 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); 1727 1728 base = community->regs + community->hostown_offset; 1729 for (gpp = 0; gpp < community->ngpps; gpp++) 1730 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); 1731 } 1732 1733 return 0; 1734 } 1735 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); 1736 #endif 1737 1738 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1739 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1740 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); 1741 MODULE_LICENSE("GPL v2"); 1742