1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Ice Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2018, Intel Corporation 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-intel.h" 17 18 #define ICL_PAD_OWN 0x020 19 #define ICL_PADCFGLOCK 0x080 20 #define ICL_HOSTSW_OWN 0x0b0 21 #define ICL_GPI_IS 0x100 22 #define ICL_GPI_IE 0x110 23 24 #define ICL_GPP(r, s, e, g) \ 25 { \ 26 .reg_num = (r), \ 27 .base = (s), \ 28 .size = ((e) - (s) + 1), \ 29 .gpio_base = (g), \ 30 } 31 32 #define ICL_NO_GPIO -1 33 34 #define ICL_COMMUNITY(b, s, e, g) \ 35 { \ 36 .barno = (b), \ 37 .padown_offset = ICL_PAD_OWN, \ 38 .padcfglock_offset = ICL_PADCFGLOCK, \ 39 .hostown_offset = ICL_HOSTSW_OWN, \ 40 .is_offset = ICL_GPI_IS, \ 41 .ie_offset = ICL_GPI_IE, \ 42 .pin_base = (s), \ 43 .npins = ((e) - (s) + 1), \ 44 .gpps = (g), \ 45 .ngpps = ARRAY_SIZE(g), \ 46 } 47 48 /* Ice Lake-LP */ 49 static const struct pinctrl_pin_desc icllp_pins[] = { 50 /* GPP_G */ 51 PINCTRL_PIN(0, "SD3_CMD"), 52 PINCTRL_PIN(1, "SD3_D0"), 53 PINCTRL_PIN(2, "SD3_D1"), 54 PINCTRL_PIN(3, "SD3_D2"), 55 PINCTRL_PIN(4, "SD3_D3"), 56 PINCTRL_PIN(5, "SD3_CDB"), 57 PINCTRL_PIN(6, "SD3_CLK"), 58 PINCTRL_PIN(7, "SD3_WP"), 59 /* GPP_B */ 60 PINCTRL_PIN(8, "CORE_VID_0"), 61 PINCTRL_PIN(9, "CORE_VID_1"), 62 PINCTRL_PIN(10, "VRALERTB"), 63 PINCTRL_PIN(11, "CPU_GP_2"), 64 PINCTRL_PIN(12, "CPU_GP_3"), 65 PINCTRL_PIN(13, "ISH_I2C0_SDA"), 66 PINCTRL_PIN(14, "ISH_I2C0_SCL"), 67 PINCTRL_PIN(15, "ISH_I2C1_SDA"), 68 PINCTRL_PIN(16, "ISH_I2C1_SCL"), 69 PINCTRL_PIN(17, "I2C5_SDA"), 70 PINCTRL_PIN(18, "I2C5_SCL"), 71 PINCTRL_PIN(19, "PMCALERTB"), 72 PINCTRL_PIN(20, "SLP_S0B"), 73 PINCTRL_PIN(21, "PLTRSTB"), 74 PINCTRL_PIN(22, "SPKR"), 75 PINCTRL_PIN(23, "GSPI0_CS0B"), 76 PINCTRL_PIN(24, "GSPI0_CLK"), 77 PINCTRL_PIN(25, "GSPI0_MISO"), 78 PINCTRL_PIN(26, "GSPI0_MOSI"), 79 PINCTRL_PIN(27, "GSPI1_CS0B"), 80 PINCTRL_PIN(28, "GSPI1_CLK"), 81 PINCTRL_PIN(29, "GSPI1_MISO"), 82 PINCTRL_PIN(30, "GSPI1_MOSI"), 83 PINCTRL_PIN(31, "SML1ALERTB"), 84 PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"), 85 PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"), 86 /* GPP_A */ 87 PINCTRL_PIN(34, "ESPI_IO_0"), 88 PINCTRL_PIN(35, "ESPI_IO_1"), 89 PINCTRL_PIN(36, "ESPI_IO_2"), 90 PINCTRL_PIN(37, "ESPI_IO_3"), 91 PINCTRL_PIN(38, "ESPI_CSB"), 92 PINCTRL_PIN(39, "ESPI_CLK"), 93 PINCTRL_PIN(40, "ESPI_RESETB"), 94 PINCTRL_PIN(41, "I2S2_SCLK"), 95 PINCTRL_PIN(42, "I2S2_SFRM"), 96 PINCTRL_PIN(43, "I2S2_TXD"), 97 PINCTRL_PIN(44, "I2S2_RXD"), 98 PINCTRL_PIN(45, "SATA_DEVSLP_2"), 99 PINCTRL_PIN(46, "SATAXPCIE_1"), 100 PINCTRL_PIN(47, "SATAXPCIE_2"), 101 PINCTRL_PIN(48, "USB2_OCB_1"), 102 PINCTRL_PIN(49, "USB2_OCB_2"), 103 PINCTRL_PIN(50, "USB2_OCB_3"), 104 PINCTRL_PIN(51, "DDSP_HPD_C"), 105 PINCTRL_PIN(52, "DDSP_HPD_B"), 106 PINCTRL_PIN(53, "DDSP_HPD_1"), 107 PINCTRL_PIN(54, "DDSP_HPD_2"), 108 PINCTRL_PIN(55, "I2S5_TXD"), 109 PINCTRL_PIN(56, "I2S5_RXD"), 110 PINCTRL_PIN(57, "I2S1_SCLK"), 111 PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"), 112 /* GPP_H */ 113 PINCTRL_PIN(59, "SD_1P8_SEL"), 114 PINCTRL_PIN(60, "SD_PWR_EN_B"), 115 PINCTRL_PIN(61, "GPPC_H_2"), 116 PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"), 117 PINCTRL_PIN(63, "I2C2_SDA"), 118 PINCTRL_PIN(64, "I2C2_SCL"), 119 PINCTRL_PIN(65, "I2C3_SDA"), 120 PINCTRL_PIN(66, "I2C3_SCL"), 121 PINCTRL_PIN(67, "I2C4_SDA"), 122 PINCTRL_PIN(68, "I2C4_SCL"), 123 PINCTRL_PIN(69, "SRCCLKREQB_4"), 124 PINCTRL_PIN(70, "SRCCLKREQB_5"), 125 PINCTRL_PIN(71, "M2_SKT2_CFG_0"), 126 PINCTRL_PIN(72, "M2_SKT2_CFG_1"), 127 PINCTRL_PIN(73, "M2_SKT2_CFG_2"), 128 PINCTRL_PIN(74, "M2_SKT2_CFG_3"), 129 PINCTRL_PIN(75, "DDPB_CTRLCLK"), 130 PINCTRL_PIN(76, "DDPB_CTRLDATA"), 131 PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"), 132 PINCTRL_PIN(78, "TIME_SYNC_0"), 133 PINCTRL_PIN(79, "IMGCLKOUT_1"), 134 PINCTRL_PIN(80, "IMGCLKOUT_2"), 135 PINCTRL_PIN(81, "IMGCLKOUT_3"), 136 PINCTRL_PIN(82, "IMGCLKOUT_4"), 137 /* GPP_D */ 138 PINCTRL_PIN(83, "ISH_GP_0"), 139 PINCTRL_PIN(84, "ISH_GP_1"), 140 PINCTRL_PIN(85, "ISH_GP_2"), 141 PINCTRL_PIN(86, "ISH_GP_3"), 142 PINCTRL_PIN(87, "IMGCLKOUT_0"), 143 PINCTRL_PIN(88, "SRCCLKREQB_0"), 144 PINCTRL_PIN(89, "SRCCLKREQB_1"), 145 PINCTRL_PIN(90, "SRCCLKREQB_2"), 146 PINCTRL_PIN(91, "SRCCLKREQB_3"), 147 PINCTRL_PIN(92, "ISH_SPI_CSB"), 148 PINCTRL_PIN(93, "ISH_SPI_CLK"), 149 PINCTRL_PIN(94, "ISH_SPI_MISO"), 150 PINCTRL_PIN(95, "ISH_SPI_MOSI"), 151 PINCTRL_PIN(96, "ISH_UART0_RXD"), 152 PINCTRL_PIN(97, "ISH_UART0_TXD"), 153 PINCTRL_PIN(98, "ISH_UART0_RTSB"), 154 PINCTRL_PIN(99, "ISH_UART0_CTSB"), 155 PINCTRL_PIN(100, "ISH_GP_4"), 156 PINCTRL_PIN(101, "ISH_GP_5"), 157 PINCTRL_PIN(102, "I2S_MCLK"), 158 PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"), 159 /* GPP_F */ 160 PINCTRL_PIN(104, "CNV_BRI_DT"), 161 PINCTRL_PIN(105, "CNV_BRI_RSP"), 162 PINCTRL_PIN(106, "CNV_RGI_DT"), 163 PINCTRL_PIN(107, "CNV_RGI_RSP"), 164 PINCTRL_PIN(108, "CNV_RF_RESET_B"), 165 PINCTRL_PIN(109, "EMMC_HIP_MON"), 166 PINCTRL_PIN(110, "CNV_PA_BLANKING"), 167 PINCTRL_PIN(111, "EMMC_CMD"), 168 PINCTRL_PIN(112, "EMMC_DATA0"), 169 PINCTRL_PIN(113, "EMMC_DATA1"), 170 PINCTRL_PIN(114, "EMMC_DATA2"), 171 PINCTRL_PIN(115, "EMMC_DATA3"), 172 PINCTRL_PIN(116, "EMMC_DATA4"), 173 PINCTRL_PIN(117, "EMMC_DATA5"), 174 PINCTRL_PIN(118, "EMMC_DATA6"), 175 PINCTRL_PIN(119, "EMMC_DATA7"), 176 PINCTRL_PIN(120, "EMMC_RCLK"), 177 PINCTRL_PIN(121, "EMMC_CLK"), 178 PINCTRL_PIN(122, "EMMC_RESETB"), 179 PINCTRL_PIN(123, "A4WP_PRESENT"), 180 /* vGPIO */ 181 PINCTRL_PIN(124, "CNV_BTEN"), 182 PINCTRL_PIN(125, "CNV_WCEN"), 183 PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"), 184 PINCTRL_PIN(127, "CNV_BT_IF_SELECT"), 185 PINCTRL_PIN(128, "vCNV_BT_UART_TXD"), 186 PINCTRL_PIN(129, "vCNV_BT_UART_RXD"), 187 PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"), 188 PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"), 189 PINCTRL_PIN(132, "vCNV_MFUART1_TXD"), 190 PINCTRL_PIN(133, "vCNV_MFUART1_RXD"), 191 PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"), 192 PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"), 193 PINCTRL_PIN(136, "vUART0_TXD"), 194 PINCTRL_PIN(137, "vUART0_RXD"), 195 PINCTRL_PIN(138, "vUART0_CTS_B"), 196 PINCTRL_PIN(139, "vUART0_RTS_B"), 197 PINCTRL_PIN(140, "vISH_UART0_TXD"), 198 PINCTRL_PIN(141, "vISH_UART0_RXD"), 199 PINCTRL_PIN(142, "vISH_UART0_CTS_B"), 200 PINCTRL_PIN(143, "vISH_UART0_RTS_B"), 201 PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"), 202 PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"), 203 PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"), 204 PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"), 205 PINCTRL_PIN(148, "vI2S2_SCLK"), 206 PINCTRL_PIN(149, "vI2S2_SFRM"), 207 PINCTRL_PIN(150, "vI2S2_TXD"), 208 PINCTRL_PIN(151, "vI2S2_RXD"), 209 PINCTRL_PIN(152, "vSD3_CD_B"), 210 /* GPP_C */ 211 PINCTRL_PIN(153, "SMBCLK"), 212 PINCTRL_PIN(154, "SMBDATA"), 213 PINCTRL_PIN(155, "SMBALERTB"), 214 PINCTRL_PIN(156, "SML0CLK"), 215 PINCTRL_PIN(157, "SML0DATA"), 216 PINCTRL_PIN(158, "SML0ALERTB"), 217 PINCTRL_PIN(159, "SML1CLK"), 218 PINCTRL_PIN(160, "SML1DATA"), 219 PINCTRL_PIN(161, "UART0_RXD"), 220 PINCTRL_PIN(162, "UART0_TXD"), 221 PINCTRL_PIN(163, "UART0_RTSB"), 222 PINCTRL_PIN(164, "UART0_CTSB"), 223 PINCTRL_PIN(165, "UART1_RXD"), 224 PINCTRL_PIN(166, "UART1_TXD"), 225 PINCTRL_PIN(167, "UART1_RTSB"), 226 PINCTRL_PIN(168, "UART1_CTSB"), 227 PINCTRL_PIN(169, "I2C0_SDA"), 228 PINCTRL_PIN(170, "I2C0_SCL"), 229 PINCTRL_PIN(171, "I2C1_SDA"), 230 PINCTRL_PIN(172, "I2C1_SCL"), 231 PINCTRL_PIN(173, "UART2_RXD"), 232 PINCTRL_PIN(174, "UART2_TXD"), 233 PINCTRL_PIN(175, "UART2_RTSB"), 234 PINCTRL_PIN(176, "UART2_CTSB"), 235 /* HVCMOS */ 236 PINCTRL_PIN(177, "L_BKLTEN"), 237 PINCTRL_PIN(178, "L_BKLTCTL"), 238 PINCTRL_PIN(179, "L_VDDEN"), 239 PINCTRL_PIN(180, "SYS_PWROK"), 240 PINCTRL_PIN(181, "SYS_RESETB"), 241 PINCTRL_PIN(182, "MLK_RSTB"), 242 /* GPP_E */ 243 PINCTRL_PIN(183, "SATAXPCIE_0"), 244 PINCTRL_PIN(184, "SPI1_IO_2"), 245 PINCTRL_PIN(185, "SPI1_IO_3"), 246 PINCTRL_PIN(186, "CPU_GP_0"), 247 PINCTRL_PIN(187, "SATA_DEVSLP_0"), 248 PINCTRL_PIN(188, "SATA_DEVSLP_1"), 249 PINCTRL_PIN(189, "GPPC_E_6"), 250 PINCTRL_PIN(190, "CPU_GP_1"), 251 PINCTRL_PIN(191, "SATA_LEDB"), 252 PINCTRL_PIN(192, "USB2_OCB_0"), 253 PINCTRL_PIN(193, "SPI1_CSB"), 254 PINCTRL_PIN(194, "SPI1_CLK"), 255 PINCTRL_PIN(195, "SPI1_MISO_IO_1"), 256 PINCTRL_PIN(196, "SPI1_MOSI_IO_0"), 257 PINCTRL_PIN(197, "DDSP_HPD_A"), 258 PINCTRL_PIN(198, "ISH_GP_6"), 259 PINCTRL_PIN(199, "ISH_GP_7"), 260 PINCTRL_PIN(200, "DISP_MISC_4"), 261 PINCTRL_PIN(201, "DDP1_CTRLCLK"), 262 PINCTRL_PIN(202, "DDP1_CTRLDATA"), 263 PINCTRL_PIN(203, "DDP2_CTRLCLK"), 264 PINCTRL_PIN(204, "DDP2_CTRLDATA"), 265 PINCTRL_PIN(205, "DDPA_CTRLCLK"), 266 PINCTRL_PIN(206, "DDPA_CTRLDATA"), 267 /* JTAG */ 268 PINCTRL_PIN(207, "JTAG_TDO"), 269 PINCTRL_PIN(208, "JTAGX"), 270 PINCTRL_PIN(209, "PRDYB"), 271 PINCTRL_PIN(210, "PREQB"), 272 PINCTRL_PIN(211, "CPU_TRSTB"), 273 PINCTRL_PIN(212, "JTAG_TDI"), 274 PINCTRL_PIN(213, "JTAG_TMS"), 275 PINCTRL_PIN(214, "JTAG_TCK"), 276 PINCTRL_PIN(215, "ITP_PMODE"), 277 /* GPP_R */ 278 PINCTRL_PIN(216, "HDA_BCLK"), 279 PINCTRL_PIN(217, "HDA_SYNC"), 280 PINCTRL_PIN(218, "HDA_SDO"), 281 PINCTRL_PIN(219, "HDA_SDI_0"), 282 PINCTRL_PIN(220, "HDA_RSTB"), 283 PINCTRL_PIN(221, "HDA_SDI_1"), 284 PINCTRL_PIN(222, "I2S1_TXD"), 285 PINCTRL_PIN(223, "I2S1_RXD"), 286 /* GPP_S */ 287 PINCTRL_PIN(224, "SNDW1_CLK"), 288 PINCTRL_PIN(225, "SNDW1_DATA"), 289 PINCTRL_PIN(226, "SNDW2_CLK"), 290 PINCTRL_PIN(227, "SNDW2_DATA"), 291 PINCTRL_PIN(228, "SNDW3_CLK"), 292 PINCTRL_PIN(229, "SNDW3_DATA"), 293 PINCTRL_PIN(230, "SNDW4_CLK"), 294 PINCTRL_PIN(231, "SNDW4_DATA"), 295 /* SPI */ 296 PINCTRL_PIN(232, "SPI0_IO_2"), 297 PINCTRL_PIN(233, "SPI0_IO_3"), 298 PINCTRL_PIN(234, "SPI0_MOSI_IO_0"), 299 PINCTRL_PIN(235, "SPI0_MISO_IO_1"), 300 PINCTRL_PIN(236, "SPI0_TPM_CSB"), 301 PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"), 302 PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"), 303 PINCTRL_PIN(239, "SPI0_CLK"), 304 PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"), 305 }; 306 307 static const struct intel_padgroup icllp_community0_gpps[] = { 308 ICL_GPP(0, 0, 7, 0), /* GPP_G */ 309 ICL_GPP(1, 8, 33, 32), /* GPP_B */ 310 ICL_GPP(2, 34, 58, 64), /* GPP_A */ 311 }; 312 313 static const struct intel_padgroup icllp_community1_gpps[] = { 314 ICL_GPP(0, 59, 82, 96), /* GPP_H */ 315 ICL_GPP(1, 83, 103, 128), /* GPP_D */ 316 ICL_GPP(2, 104, 123, 160), /* GPP_F */ 317 ICL_GPP(3, 124, 152, 192), /* vGPIO */ 318 }; 319 320 static const struct intel_padgroup icllp_community4_gpps[] = { 321 ICL_GPP(0, 153, 176, 224), /* GPP_C */ 322 ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */ 323 ICL_GPP(2, 183, 206, 256), /* GPP_E */ 324 ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */ 325 }; 326 327 static const struct intel_padgroup icllp_community5_gpps[] = { 328 ICL_GPP(0, 216, 223, 288), /* GPP_R */ 329 ICL_GPP(1, 224, 231, 320), /* GPP_S */ 330 ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */ 331 }; 332 333 static const struct intel_community icllp_communities[] = { 334 ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps), 335 ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps), 336 ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps), 337 ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps), 338 }; 339 340 static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 }; 341 static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 }; 342 static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 }; 343 static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 }; 344 static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 }; 345 static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 }; 346 347 static const unsigned int icllp_i2c0_pins[] = { 169, 170 }; 348 static const unsigned int icllp_i2c1_pins[] = { 171, 172 }; 349 static const unsigned int icllp_i2c2_pins[] = { 63, 64 }; 350 static const unsigned int icllp_i2c3_pins[] = { 65, 66 }; 351 static const unsigned int icllp_i2c4_pins[] = { 67, 68 }; 352 353 static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 }; 354 static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 }; 355 static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 }; 356 357 static const struct intel_pingroup icllp_groups[] = { 358 PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes), 359 PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes), 360 PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes), 361 PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1), 362 PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1), 363 PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1), 364 PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1), 365 PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1), 366 PIN_GROUP("uart0_grp", icllp_uart0_pins, 1), 367 PIN_GROUP("uart1_grp", icllp_uart1_pins, 1), 368 PIN_GROUP("uart2_grp", icllp_uart2_pins, 1), 369 }; 370 371 static const char * const icllp_spi0_groups[] = { "spi0_grp" }; 372 static const char * const icllp_spi1_groups[] = { "spi1_grp" }; 373 static const char * const icllp_spi2_groups[] = { "spi2_grp" }; 374 static const char * const icllp_i2c0_groups[] = { "i2c0_grp" }; 375 static const char * const icllp_i2c1_groups[] = { "i2c1_grp" }; 376 static const char * const icllp_i2c2_groups[] = { "i2c2_grp" }; 377 static const char * const icllp_i2c3_groups[] = { "i2c3_grp" }; 378 static const char * const icllp_i2c4_groups[] = { "i2c4_grp" }; 379 static const char * const icllp_uart0_groups[] = { "uart0_grp" }; 380 static const char * const icllp_uart1_groups[] = { "uart1_grp" }; 381 static const char * const icllp_uart2_groups[] = { "uart2_grp" }; 382 383 static const struct intel_function icllp_functions[] = { 384 FUNCTION("spi0", icllp_spi0_groups), 385 FUNCTION("spi1", icllp_spi1_groups), 386 FUNCTION("spi2", icllp_spi2_groups), 387 FUNCTION("i2c0", icllp_i2c0_groups), 388 FUNCTION("i2c1", icllp_i2c1_groups), 389 FUNCTION("i2c2", icllp_i2c2_groups), 390 FUNCTION("i2c3", icllp_i2c3_groups), 391 FUNCTION("i2c4", icllp_i2c4_groups), 392 FUNCTION("uart0", icllp_uart0_groups), 393 FUNCTION("uart1", icllp_uart1_groups), 394 FUNCTION("uart2", icllp_uart2_groups), 395 }; 396 397 static const struct intel_pinctrl_soc_data icllp_soc_data = { 398 .pins = icllp_pins, 399 .npins = ARRAY_SIZE(icllp_pins), 400 .groups = icllp_groups, 401 .ngroups = ARRAY_SIZE(icllp_groups), 402 .functions = icllp_functions, 403 .nfunctions = ARRAY_SIZE(icllp_functions), 404 .communities = icllp_communities, 405 .ncommunities = ARRAY_SIZE(icllp_communities), 406 }; 407 408 static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops); 409 410 static const struct acpi_device_id icl_pinctrl_acpi_match[] = { 411 { "INT3455", (kernel_ulong_t)&icllp_soc_data }, 412 { } 413 }; 414 MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match); 415 416 static struct platform_driver icl_pinctrl_driver = { 417 .probe = intel_pinctrl_probe_by_hid, 418 .driver = { 419 .name = "icelake-pinctrl", 420 .acpi_match_table = icl_pinctrl_acpi_match, 421 .pm = &icl_pinctrl_pm_ops, 422 }, 423 }; 424 425 module_platform_driver(icl_pinctrl_driver); 426 427 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 428 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 429 MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver"); 430 MODULE_LICENSE("GPL v2"); 431