1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Gemini Lake SoC pinctrl/GPIO driver 4 * 5 * Copyright (C) 2017 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-intel.h" 16 17 #define GLK_PAD_OWN 0x020 18 #define GLK_PADCFGLOCK 0x080 19 #define GLK_HOSTSW_OWN 0x0b0 20 #define GLK_GPI_IE 0x110 21 22 #define GLK_COMMUNITY(s, e) \ 23 { \ 24 .padown_offset = GLK_PAD_OWN, \ 25 .padcfglock_offset = GLK_PADCFGLOCK, \ 26 .hostown_offset = GLK_HOSTSW_OWN, \ 27 .ie_offset = GLK_GPI_IE, \ 28 .gpp_size = 32, \ 29 .pin_base = (s), \ 30 .npins = ((e) - (s) + 1), \ 31 } 32 33 /* GLK */ 34 static const struct pinctrl_pin_desc glk_northwest_pins[] = { 35 PINCTRL_PIN(0, "TCK"), 36 PINCTRL_PIN(1, "TRST_B"), 37 PINCTRL_PIN(2, "TMS"), 38 PINCTRL_PIN(3, "TDI"), 39 PINCTRL_PIN(4, "TDO"), 40 PINCTRL_PIN(5, "JTAGX"), 41 PINCTRL_PIN(6, "CX_PREQ_B"), 42 PINCTRL_PIN(7, "CX_PRDY_B"), 43 PINCTRL_PIN(8, "GPIO_8"), 44 PINCTRL_PIN(9, "GPIO_9"), 45 PINCTRL_PIN(10, "GPIO_10"), 46 PINCTRL_PIN(11, "GPIO_11"), 47 PINCTRL_PIN(12, "GPIO_12"), 48 PINCTRL_PIN(13, "GPIO_13"), 49 PINCTRL_PIN(14, "GPIO_14"), 50 PINCTRL_PIN(15, "GPIO_15"), 51 PINCTRL_PIN(16, "GPIO_16"), 52 PINCTRL_PIN(17, "GPIO_17"), 53 PINCTRL_PIN(18, "GPIO_18"), 54 PINCTRL_PIN(19, "GPIO_19"), 55 PINCTRL_PIN(20, "GPIO_20"), 56 PINCTRL_PIN(21, "GPIO_21"), 57 PINCTRL_PIN(22, "GPIO_22"), 58 PINCTRL_PIN(23, "GPIO_23"), 59 PINCTRL_PIN(24, "GPIO_24"), 60 PINCTRL_PIN(25, "GPIO_25"), 61 PINCTRL_PIN(26, "ISH_GPIO_0"), 62 PINCTRL_PIN(27, "ISH_GPIO_1"), 63 PINCTRL_PIN(28, "ISH_GPIO_2"), 64 PINCTRL_PIN(29, "ISH_GPIO_3"), 65 PINCTRL_PIN(30, "ISH_GPIO_4"), 66 PINCTRL_PIN(31, "ISH_GPIO_5"), 67 PINCTRL_PIN(32, "ISH_GPIO_6"), 68 PINCTRL_PIN(33, "ISH_GPIO_7"), 69 PINCTRL_PIN(34, "ISH_GPIO_8"), 70 PINCTRL_PIN(35, "ISH_GPIO_9"), 71 PINCTRL_PIN(36, "GPIO_36"), 72 PINCTRL_PIN(37, "GPIO_37"), 73 PINCTRL_PIN(38, "GPIO_38"), 74 PINCTRL_PIN(39, "GPIO_39"), 75 PINCTRL_PIN(40, "GPIO_40"), 76 PINCTRL_PIN(41, "GPIO_41"), 77 PINCTRL_PIN(42, "GP_INTD_DSI_TE1"), 78 PINCTRL_PIN(43, "GP_INTD_DSI_TE2"), 79 PINCTRL_PIN(44, "USB_OC0_B"), 80 PINCTRL_PIN(45, "USB_OC1_B"), 81 PINCTRL_PIN(46, "DSI_I2C_SDA"), 82 PINCTRL_PIN(47, "DSI_I2C_SCL"), 83 PINCTRL_PIN(48, "PMC_I2C_SDA"), 84 PINCTRL_PIN(49, "PMC_I2C_SCL"), 85 PINCTRL_PIN(50, "LPSS_I2C0_SDA"), 86 PINCTRL_PIN(51, "LPSS_I2C0_SCL"), 87 PINCTRL_PIN(52, "LPSS_I2C1_SDA"), 88 PINCTRL_PIN(53, "LPSS_I2C1_SCL"), 89 PINCTRL_PIN(54, "LPSS_I2C2_SDA"), 90 PINCTRL_PIN(55, "LPSS_I2C2_SCL"), 91 PINCTRL_PIN(56, "LPSS_I2C3_SDA"), 92 PINCTRL_PIN(57, "LPSS_I2C3_SCL"), 93 PINCTRL_PIN(58, "LPSS_I2C4_SDA"), 94 PINCTRL_PIN(59, "LPSS_I2C4_SCL"), 95 PINCTRL_PIN(60, "LPSS_UART0_RXD"), 96 PINCTRL_PIN(61, "LPSS_UART0_TXD"), 97 PINCTRL_PIN(62, "LPSS_UART0_RTS_B"), 98 PINCTRL_PIN(63, "LPSS_UART0_CTS_B"), 99 PINCTRL_PIN(64, "LPSS_UART2_RXD"), 100 PINCTRL_PIN(65, "LPSS_UART2_TXD"), 101 PINCTRL_PIN(66, "LPSS_UART2_RTS_B"), 102 PINCTRL_PIN(67, "LPSS_UART2_CTS_B"), 103 PINCTRL_PIN(68, "PMC_SPI_FS0"), 104 PINCTRL_PIN(69, "PMC_SPI_FS1"), 105 PINCTRL_PIN(70, "PMC_SPI_FS2"), 106 PINCTRL_PIN(71, "PMC_SPI_RXD"), 107 PINCTRL_PIN(72, "PMC_SPI_TXD"), 108 PINCTRL_PIN(73, "PMC_SPI_CLK"), 109 PINCTRL_PIN(74, "THERMTRIP_B"), 110 PINCTRL_PIN(75, "PROCHOT_B"), 111 PINCTRL_PIN(76, "EMMC_RST_B"), 112 PINCTRL_PIN(77, "GPIO_212"), 113 PINCTRL_PIN(78, "GPIO_213"), 114 PINCTRL_PIN(79, "GPIO_214"), 115 }; 116 117 static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 }; 118 static const unsigned int glk_northwest_pwm0_pins[] = { 42 }; 119 static const unsigned int glk_northwest_pwm1_pins[] = { 43 }; 120 static const unsigned int glk_northwest_pwm2_pins[] = { 44 }; 121 static const unsigned int glk_northwest_pwm3_pins[] = { 45 }; 122 static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 }; 123 static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 }; 124 static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 }; 125 static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 }; 126 static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 }; 127 static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 }; 128 static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 }; 129 130 static const struct intel_pingroup glk_northwest_groups[] = { 131 PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2), 132 PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2), 133 PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2), 134 PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2), 135 PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2), 136 PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1), 137 PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1), 138 PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1), 139 PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1), 140 PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1), 141 PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1), 142 PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1), 143 }; 144 145 static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" }; 146 static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" }; 147 static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" }; 148 static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" }; 149 static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" }; 150 static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" }; 151 static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" }; 152 static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" }; 153 static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" }; 154 static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" }; 155 static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" }; 156 static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" }; 157 158 static const struct intel_function glk_northwest_functions[] = { 159 FUNCTION("uart1", glk_northwest_uart1_groups), 160 FUNCTION("pmw0", glk_northwest_pwm0_groups), 161 FUNCTION("pmw1", glk_northwest_pwm1_groups), 162 FUNCTION("pmw2", glk_northwest_pwm2_groups), 163 FUNCTION("pmw3", glk_northwest_pwm3_groups), 164 FUNCTION("i2c0", glk_northwest_i2c0_groups), 165 FUNCTION("i2c1", glk_northwest_i2c1_groups), 166 FUNCTION("i2c2", glk_northwest_i2c2_groups), 167 FUNCTION("i2c3", glk_northwest_i2c3_groups), 168 FUNCTION("i2c4", glk_northwest_i2c4_groups), 169 FUNCTION("uart0", glk_northwest_uart0_groups), 170 FUNCTION("uart2", glk_northwest_uart2_groups), 171 }; 172 173 static const struct intel_community glk_northwest_communities[] = { 174 GLK_COMMUNITY(0, 79), 175 }; 176 177 static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { 178 .uid = "1", 179 .pins = glk_northwest_pins, 180 .npins = ARRAY_SIZE(glk_northwest_pins), 181 .groups = glk_northwest_groups, 182 .ngroups = ARRAY_SIZE(glk_northwest_groups), 183 .functions = glk_northwest_functions, 184 .nfunctions = ARRAY_SIZE(glk_northwest_functions), 185 .communities = glk_northwest_communities, 186 .ncommunities = ARRAY_SIZE(glk_northwest_communities), 187 }; 188 189 static const struct pinctrl_pin_desc glk_north_pins[] = { 190 PINCTRL_PIN(0, "SVID0_ALERT_B"), 191 PINCTRL_PIN(1, "SVID0_DATA"), 192 PINCTRL_PIN(2, "SVID0_CLK"), 193 PINCTRL_PIN(3, "LPSS_SPI_0_CLK"), 194 PINCTRL_PIN(4, "LPSS_SPI_0_FS0"), 195 PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), 196 PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), 197 PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), 198 PINCTRL_PIN(8, "LPSS_SPI_2_CLK"), 199 PINCTRL_PIN(9, "LPSS_SPI_2_FS0"), 200 PINCTRL_PIN(10, "LPSS_SPI_2_FS1"), 201 PINCTRL_PIN(11, "LPSS_SPI_2_FS2"), 202 PINCTRL_PIN(12, "LPSS_SPI_2_RXD"), 203 PINCTRL_PIN(13, "LPSS_SPI_2_TXD"), 204 PINCTRL_PIN(14, "FST_SPI_CS0_B"), 205 PINCTRL_PIN(15, "FST_SPI_CS1_B"), 206 PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), 207 PINCTRL_PIN(17, "FST_SPI_MISO_IO1"), 208 PINCTRL_PIN(18, "FST_SPI_IO2"), 209 PINCTRL_PIN(19, "FST_SPI_IO3"), 210 PINCTRL_PIN(20, "FST_SPI_CLK"), 211 PINCTRL_PIN(21, "FST_SPI_CLK_FB"), 212 PINCTRL_PIN(22, "PMU_PLTRST_B"), 213 PINCTRL_PIN(23, "PMU_PWRBTN_B"), 214 PINCTRL_PIN(24, "PMU_SLP_S0_B"), 215 PINCTRL_PIN(25, "PMU_SLP_S3_B"), 216 PINCTRL_PIN(26, "PMU_SLP_S4_B"), 217 PINCTRL_PIN(27, "SUSPWRDNACK"), 218 PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"), 219 PINCTRL_PIN(29, "GPIO_105"), 220 PINCTRL_PIN(30, "PMU_BATLOW_B"), 221 PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), 222 PINCTRL_PIN(32, "PMU_SUSCLK"), 223 PINCTRL_PIN(33, "SUS_STAT_B"), 224 PINCTRL_PIN(34, "LPSS_I2C5_SDA"), 225 PINCTRL_PIN(35, "LPSS_I2C5_SCL"), 226 PINCTRL_PIN(36, "LPSS_I2C6_SDA"), 227 PINCTRL_PIN(37, "LPSS_I2C6_SCL"), 228 PINCTRL_PIN(38, "LPSS_I2C7_SDA"), 229 PINCTRL_PIN(39, "LPSS_I2C7_SCL"), 230 PINCTRL_PIN(40, "PCIE_WAKE0_B"), 231 PINCTRL_PIN(41, "PCIE_WAKE1_B"), 232 PINCTRL_PIN(42, "PCIE_WAKE2_B"), 233 PINCTRL_PIN(43, "PCIE_WAKE3_B"), 234 PINCTRL_PIN(44, "PCIE_CLKREQ0_B"), 235 PINCTRL_PIN(45, "PCIE_CLKREQ1_B"), 236 PINCTRL_PIN(46, "PCIE_CLKREQ2_B"), 237 PINCTRL_PIN(47, "PCIE_CLKREQ3_B"), 238 PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"), 239 PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"), 240 PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"), 241 PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"), 242 PINCTRL_PIN(52, "PANEL0_VDDEN"), 243 PINCTRL_PIN(53, "PANEL0_BKLTEN"), 244 PINCTRL_PIN(54, "PANEL0_BKLTCTL"), 245 PINCTRL_PIN(55, "HV_DDI0_HPD"), 246 PINCTRL_PIN(56, "HV_DDI1_HPD"), 247 PINCTRL_PIN(57, "HV_EDP_HPD"), 248 PINCTRL_PIN(58, "GPIO_134"), 249 PINCTRL_PIN(59, "GPIO_135"), 250 PINCTRL_PIN(60, "GPIO_136"), 251 PINCTRL_PIN(61, "GPIO_137"), 252 PINCTRL_PIN(62, "GPIO_138"), 253 PINCTRL_PIN(63, "GPIO_139"), 254 PINCTRL_PIN(64, "GPIO_140"), 255 PINCTRL_PIN(65, "GPIO_141"), 256 PINCTRL_PIN(66, "GPIO_142"), 257 PINCTRL_PIN(67, "GPIO_143"), 258 PINCTRL_PIN(68, "GPIO_144"), 259 PINCTRL_PIN(69, "GPIO_145"), 260 PINCTRL_PIN(70, "GPIO_146"), 261 PINCTRL_PIN(71, "LPC_ILB_SERIRQ"), 262 PINCTRL_PIN(72, "LPC_CLKOUT0"), 263 PINCTRL_PIN(73, "LPC_CLKOUT1"), 264 PINCTRL_PIN(74, "LPC_AD0"), 265 PINCTRL_PIN(75, "LPC_AD1"), 266 PINCTRL_PIN(76, "LPC_AD2"), 267 PINCTRL_PIN(77, "LPC_AD3"), 268 PINCTRL_PIN(78, "LPC_CLKRUNB"), 269 PINCTRL_PIN(79, "LPC_FRAMEB"), 270 }; 271 272 static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 }; 273 static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 }; 274 static const unsigned int glk_north_i2c5_pins[] = { 34, 35 }; 275 static const unsigned int glk_north_i2c6_pins[] = { 36, 37 }; 276 static const unsigned int glk_north_i2c7_pins[] = { 38, 39 }; 277 static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 }; 278 static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 }; 279 280 static const struct intel_pingroup glk_north_groups[] = { 281 PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1), 282 PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1), 283 PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1), 284 PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1), 285 PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1), 286 PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2), 287 PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2), 288 }; 289 290 static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" }; 291 static const char * const glk_north_spi1_groups[] = { "spi1_grp" }; 292 static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" }; 293 static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" }; 294 static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" }; 295 static const char * const glk_north_uart0_groups[] = { "uart0_grp" }; 296 297 static const struct intel_function glk_north_functions[] = { 298 FUNCTION("spi0", glk_north_spi0_groups), 299 FUNCTION("spi1", glk_north_spi1_groups), 300 FUNCTION("i2c5", glk_north_i2c5_groups), 301 FUNCTION("i2c6", glk_north_i2c6_groups), 302 FUNCTION("i2c7", glk_north_i2c7_groups), 303 FUNCTION("uart0", glk_north_uart0_groups), 304 }; 305 306 static const struct intel_community glk_north_communities[] = { 307 GLK_COMMUNITY(0, 79), 308 }; 309 310 static const struct intel_pinctrl_soc_data glk_north_soc_data = { 311 .uid = "2", 312 .pins = glk_north_pins, 313 .npins = ARRAY_SIZE(glk_north_pins), 314 .groups = glk_north_groups, 315 .ngroups = ARRAY_SIZE(glk_north_groups), 316 .functions = glk_north_functions, 317 .nfunctions = ARRAY_SIZE(glk_north_functions), 318 .communities = glk_north_communities, 319 .ncommunities = ARRAY_SIZE(glk_north_communities), 320 }; 321 322 static const struct pinctrl_pin_desc glk_audio_pins[] = { 323 PINCTRL_PIN(0, "AVS_I2S0_MCLK"), 324 PINCTRL_PIN(1, "AVS_I2S0_BCLK"), 325 PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"), 326 PINCTRL_PIN(3, "AVS_I2S0_SDI"), 327 PINCTRL_PIN(4, "AVS_I2S0_SDO"), 328 PINCTRL_PIN(5, "AVS_I2S1_MCLK"), 329 PINCTRL_PIN(6, "AVS_I2S1_BCLK"), 330 PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"), 331 PINCTRL_PIN(8, "AVS_I2S1_SDI"), 332 PINCTRL_PIN(9, "AVS_I2S1_SDO"), 333 PINCTRL_PIN(10, "AVS_HDA_BCLK"), 334 PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"), 335 PINCTRL_PIN(12, "AVS_HDA_SDI"), 336 PINCTRL_PIN(13, "AVS_HDA_SDO"), 337 PINCTRL_PIN(14, "AVS_HDA_RSTB"), 338 PINCTRL_PIN(15, "AVS_M_CLK_A1"), 339 PINCTRL_PIN(16, "AVS_M_CLK_B1"), 340 PINCTRL_PIN(17, "AVS_M_DATA_1"), 341 PINCTRL_PIN(18, "AVS_M_CLK_AB2"), 342 PINCTRL_PIN(19, "AVS_M_DATA_2"), 343 }; 344 345 static const struct intel_community glk_audio_communities[] = { 346 GLK_COMMUNITY(0, 19), 347 }; 348 349 static const struct intel_pinctrl_soc_data glk_audio_soc_data = { 350 .uid = "3", 351 .pins = glk_audio_pins, 352 .npins = ARRAY_SIZE(glk_audio_pins), 353 .communities = glk_audio_communities, 354 .ncommunities = ARRAY_SIZE(glk_audio_communities), 355 }; 356 357 static const struct pinctrl_pin_desc glk_scc_pins[] = { 358 PINCTRL_PIN(0, "SMB_ALERTB"), 359 PINCTRL_PIN(1, "SMB_CLK"), 360 PINCTRL_PIN(2, "SMB_DATA"), 361 PINCTRL_PIN(3, "SDCARD_LVL_WP"), 362 PINCTRL_PIN(4, "SDCARD_CLK"), 363 PINCTRL_PIN(5, "SDCARD_CLK_FB"), 364 PINCTRL_PIN(6, "SDCARD_D0"), 365 PINCTRL_PIN(7, "SDCARD_D1"), 366 PINCTRL_PIN(8, "SDCARD_D2"), 367 PINCTRL_PIN(9, "SDCARD_D3"), 368 PINCTRL_PIN(10, "SDCARD_CMD"), 369 PINCTRL_PIN(11, "SDCARD_CD_B"), 370 PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"), 371 PINCTRL_PIN(13, "GPIO_210"), 372 PINCTRL_PIN(14, "OSC_CLK_OUT_0"), 373 PINCTRL_PIN(15, "OSC_CLK_OUT_1"), 374 PINCTRL_PIN(16, "CNV_BRI_DT"), 375 PINCTRL_PIN(17, "CNV_BRI_RSP"), 376 PINCTRL_PIN(18, "CNV_RGI_DT"), 377 PINCTRL_PIN(19, "CNV_RGI_RSP"), 378 PINCTRL_PIN(20, "CNV_RF_RESET_B"), 379 PINCTRL_PIN(21, "XTAL_CLKREQ"), 380 PINCTRL_PIN(22, "SDIO_CLK_FB"), 381 PINCTRL_PIN(23, "EMMC0_CLK"), 382 PINCTRL_PIN(24, "EMMC0_CLK_FB"), 383 PINCTRL_PIN(25, "EMMC0_D0"), 384 PINCTRL_PIN(26, "EMMC0_D1"), 385 PINCTRL_PIN(27, "EMMC0_D2"), 386 PINCTRL_PIN(28, "EMMC0_D3"), 387 PINCTRL_PIN(29, "EMMC0_D4"), 388 PINCTRL_PIN(30, "EMMC0_D5"), 389 PINCTRL_PIN(31, "EMMC0_D6"), 390 PINCTRL_PIN(32, "EMMC0_D7"), 391 PINCTRL_PIN(33, "EMMC0_CMD"), 392 PINCTRL_PIN(34, "EMMC0_STROBE"), 393 }; 394 395 static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 }; 396 static const unsigned int glk_scc_sdcard_pins[] = { 397 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 398 }; 399 static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 }; 400 static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 }; 401 static const unsigned int glk_scc_emmc_pins[] = { 402 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 403 }; 404 405 static const struct intel_pingroup glk_scc_groups[] = { 406 PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2), 407 PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1), 408 PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2), 409 PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3), 410 PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1), 411 }; 412 413 static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" }; 414 static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" }; 415 static const char * const glk_scc_sdio_groups[] = { "sdio_grp" }; 416 static const char * const glk_scc_uart1_groups[] = { "uart1_grp" }; 417 static const char * const glk_scc_emmc_groups[] = { "emmc_grp" }; 418 419 static const struct intel_function glk_scc_functions[] = { 420 FUNCTION("i2c7", glk_scc_i2c7_groups), 421 FUNCTION("sdcard", glk_scc_sdcard_groups), 422 FUNCTION("sdio", glk_scc_sdio_groups), 423 FUNCTION("uart1", glk_scc_uart1_groups), 424 FUNCTION("emmc", glk_scc_emmc_groups), 425 }; 426 427 static const struct intel_community glk_scc_communities[] = { 428 GLK_COMMUNITY(0, 34), 429 }; 430 431 static const struct intel_pinctrl_soc_data glk_scc_soc_data = { 432 .uid = "4", 433 .pins = glk_scc_pins, 434 .npins = ARRAY_SIZE(glk_scc_pins), 435 .groups = glk_scc_groups, 436 .ngroups = ARRAY_SIZE(glk_scc_groups), 437 .functions = glk_scc_functions, 438 .nfunctions = ARRAY_SIZE(glk_scc_functions), 439 .communities = glk_scc_communities, 440 .ncommunities = ARRAY_SIZE(glk_scc_communities), 441 }; 442 443 static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { 444 &glk_northwest_soc_data, 445 &glk_north_soc_data, 446 &glk_audio_soc_data, 447 &glk_scc_soc_data, 448 NULL 449 }; 450 451 static const struct acpi_device_id glk_pinctrl_acpi_match[] = { 452 { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data }, 453 { } 454 }; 455 MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); 456 457 static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops); 458 459 static struct platform_driver glk_pinctrl_driver = { 460 .probe = intel_pinctrl_probe_by_uid, 461 .driver = { 462 .name = "geminilake-pinctrl", 463 .acpi_match_table = glk_pinctrl_acpi_match, 464 .pm = &glk_pinctrl_pm_ops, 465 }, 466 }; 467 468 static int __init glk_pinctrl_init(void) 469 { 470 return platform_driver_register(&glk_pinctrl_driver); 471 } 472 subsys_initcall(glk_pinctrl_init); 473 474 static void __exit glk_pinctrl_exit(void) 475 { 476 platform_driver_unregister(&glk_pinctrl_driver); 477 } 478 module_exit(glk_pinctrl_exit); 479 480 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 481 MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); 482 MODULE_LICENSE("GPL v2"); 483