1 /* 2 * Intel Gemini Lake SoC pinctrl/GPIO driver 3 * 4 * Copyright (C) 2017 Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/acpi.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm.h> 16 #include <linux/pinctrl/pinctrl.h> 17 18 #include "pinctrl-intel.h" 19 20 #define GLK_PAD_OWN 0x020 21 #define GLK_HOSTSW_OWN 0x0b0 22 #define GLK_PADCFGLOCK 0x080 23 #define GLK_GPI_IE 0x110 24 25 #define GLK_COMMUNITY(s, e) \ 26 { \ 27 .padown_offset = GLK_PAD_OWN, \ 28 .padcfglock_offset = GLK_PADCFGLOCK, \ 29 .hostown_offset = GLK_HOSTSW_OWN, \ 30 .ie_offset = GLK_GPI_IE, \ 31 .gpp_size = 32, \ 32 .pin_base = (s), \ 33 .npins = ((e) - (s) + 1), \ 34 } 35 36 /* GLK */ 37 static const struct pinctrl_pin_desc glk_northwest_pins[] = { 38 PINCTRL_PIN(0, "TCK"), 39 PINCTRL_PIN(1, "TRST_B"), 40 PINCTRL_PIN(2, "TMS"), 41 PINCTRL_PIN(3, "TDI"), 42 PINCTRL_PIN(4, "TDO"), 43 PINCTRL_PIN(5, "JTAGX"), 44 PINCTRL_PIN(6, "CX_PREQ_B"), 45 PINCTRL_PIN(7, "CX_PRDY_B"), 46 PINCTRL_PIN(8, "GPIO_8"), 47 PINCTRL_PIN(9, "GPIO_9"), 48 PINCTRL_PIN(10, "GPIO_10"), 49 PINCTRL_PIN(11, "GPIO_11"), 50 PINCTRL_PIN(12, "GPIO_12"), 51 PINCTRL_PIN(13, "GPIO_13"), 52 PINCTRL_PIN(14, "GPIO_14"), 53 PINCTRL_PIN(15, "GPIO_15"), 54 PINCTRL_PIN(16, "GPIO_16"), 55 PINCTRL_PIN(17, "GPIO_17"), 56 PINCTRL_PIN(18, "GPIO_18"), 57 PINCTRL_PIN(19, "GPIO_19"), 58 PINCTRL_PIN(20, "GPIO_20"), 59 PINCTRL_PIN(21, "GPIO_21"), 60 PINCTRL_PIN(22, "GPIO_22"), 61 PINCTRL_PIN(23, "GPIO_23"), 62 PINCTRL_PIN(24, "GPIO_24"), 63 PINCTRL_PIN(25, "GPIO_25"), 64 PINCTRL_PIN(26, "GPIO_26"), 65 PINCTRL_PIN(27, "GPIO_27"), 66 PINCTRL_PIN(28, "GPIO_28"), 67 PINCTRL_PIN(29, "GPIO_29"), 68 PINCTRL_PIN(30, "GPIO_30"), 69 PINCTRL_PIN(31, "GPIO_31"), 70 PINCTRL_PIN(32, "GPIO_32"), 71 PINCTRL_PIN(33, "GPIO_33"), 72 PINCTRL_PIN(34, "GPIO_34"), 73 PINCTRL_PIN(35, "GPIO_35"), 74 PINCTRL_PIN(36, "GPIO_36"), 75 PINCTRL_PIN(37, "GPIO_37"), 76 PINCTRL_PIN(38, "GPIO_38"), 77 PINCTRL_PIN(39, "GPIO_39"), 78 PINCTRL_PIN(40, "GPIO_40"), 79 PINCTRL_PIN(41, "GPIO_41"), 80 PINCTRL_PIN(42, "GP_INTD_DSI_TE1"), 81 PINCTRL_PIN(43, "GP_INTD_DSI_TE2"), 82 PINCTRL_PIN(44, "USB_OC0_B"), 83 PINCTRL_PIN(45, "USB_OC1_B"), 84 PINCTRL_PIN(46, "DSI_I2C_SDA"), 85 PINCTRL_PIN(47, "DSI_I2C_SCL"), 86 PINCTRL_PIN(48, "PMC_I2C_SDA"), 87 PINCTRL_PIN(49, "PMC_I2C_SCL"), 88 PINCTRL_PIN(50, "LPSS_I2C0_SDA"), 89 PINCTRL_PIN(51, "LPSS_I2C0_SCL"), 90 PINCTRL_PIN(52, "LPSS_I2C1_SDA"), 91 PINCTRL_PIN(53, "LPSS_I2C1_SCL"), 92 PINCTRL_PIN(54, "LPSS_I2C2_SDA"), 93 PINCTRL_PIN(55, "LPSS_I2C2_SCL"), 94 PINCTRL_PIN(56, "LPSS_I2C3_SDA"), 95 PINCTRL_PIN(57, "LPSS_I2C3_SCL"), 96 PINCTRL_PIN(58, "LPSS_I2C4_SDA"), 97 PINCTRL_PIN(59, "LPSS_I2C4_SCL"), 98 PINCTRL_PIN(60, "LPSS_UART0_RXD"), 99 PINCTRL_PIN(61, "LPSS_UART0_TXD"), 100 PINCTRL_PIN(62, "LPSS_UART0_RTS_B"), 101 PINCTRL_PIN(63, "LPSS_UART0_CTS_B"), 102 PINCTRL_PIN(64, "LPSS_UART2_RXD"), 103 PINCTRL_PIN(65, "LPSS_UART2_TXD"), 104 PINCTRL_PIN(66, "LPSS_UART2_RTS_B"), 105 PINCTRL_PIN(67, "LPSS_UART2_CTS_B"), 106 PINCTRL_PIN(68, "PMC_SPI_FS0"), 107 PINCTRL_PIN(69, "PMC_SPI_FS1"), 108 PINCTRL_PIN(70, "PMC_SPI_FS2"), 109 PINCTRL_PIN(71, "PMC_SPI_RXD"), 110 PINCTRL_PIN(72, "PMC_SPI_TXD"), 111 PINCTRL_PIN(73, "PMC_SPI_CLK"), 112 PINCTRL_PIN(74, "THERMTRIP_B"), 113 PINCTRL_PIN(75, "PROCHOT_B"), 114 PINCTRL_PIN(76, "EMMC_RST_B"), 115 PINCTRL_PIN(77, "GPIO_212"), 116 PINCTRL_PIN(78, "GPIO_213"), 117 PINCTRL_PIN(79, "GPIO_214"), 118 }; 119 120 static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 }; 121 static const unsigned int glk_northwest_pwm0_pins[] = { 42 }; 122 static const unsigned int glk_northwest_pwm1_pins[] = { 43 }; 123 static const unsigned int glk_northwest_pwm2_pins[] = { 44 }; 124 static const unsigned int glk_northwest_pwm3_pins[] = { 45 }; 125 static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 }; 126 static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 }; 127 static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 }; 128 static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 }; 129 static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 }; 130 static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 }; 131 static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 }; 132 133 static const struct intel_pingroup glk_northwest_groups[] = { 134 PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2), 135 PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2), 136 PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2), 137 PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2), 138 PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2), 139 PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1), 140 PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1), 141 PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1), 142 PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1), 143 PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1), 144 PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1), 145 PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1), 146 }; 147 148 static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" }; 149 static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" }; 150 static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" }; 151 static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" }; 152 static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" }; 153 static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" }; 154 static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" }; 155 static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" }; 156 static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" }; 157 static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" }; 158 static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" }; 159 static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" }; 160 161 static const struct intel_function glk_northwest_functions[] = { 162 FUNCTION("uart1", glk_northwest_uart1_groups), 163 FUNCTION("pmw0", glk_northwest_pwm0_groups), 164 FUNCTION("pmw1", glk_northwest_pwm1_groups), 165 FUNCTION("pmw2", glk_northwest_pwm2_groups), 166 FUNCTION("pmw3", glk_northwest_pwm3_groups), 167 FUNCTION("i2c0", glk_northwest_i2c0_groups), 168 FUNCTION("i2c1", glk_northwest_i2c1_groups), 169 FUNCTION("i2c2", glk_northwest_i2c2_groups), 170 FUNCTION("i2c3", glk_northwest_i2c3_groups), 171 FUNCTION("i2c4", glk_northwest_i2c4_groups), 172 FUNCTION("uart0", glk_northwest_uart0_groups), 173 FUNCTION("uart2", glk_northwest_uart2_groups), 174 }; 175 176 static const struct intel_community glk_northwest_communities[] = { 177 GLK_COMMUNITY(0, 79), 178 }; 179 180 static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { 181 .uid = "1", 182 .pins = glk_northwest_pins, 183 .npins = ARRAY_SIZE(glk_northwest_pins), 184 .groups = glk_northwest_groups, 185 .ngroups = ARRAY_SIZE(glk_northwest_groups), 186 .functions = glk_northwest_functions, 187 .nfunctions = ARRAY_SIZE(glk_northwest_functions), 188 .communities = glk_northwest_communities, 189 .ncommunities = ARRAY_SIZE(glk_northwest_communities), 190 }; 191 192 static const struct pinctrl_pin_desc glk_north_pins[] = { 193 PINCTRL_PIN(0, "SVID0_ALERT_B"), 194 PINCTRL_PIN(1, "SVID0_DATA"), 195 PINCTRL_PIN(2, "SVID0_CLK"), 196 PINCTRL_PIN(3, "LPSS_SPI_0_CLK"), 197 PINCTRL_PIN(4, "LPSS_SPI_0_FS0"), 198 PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), 199 PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), 200 PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), 201 PINCTRL_PIN(8, "LPSS_SPI_1_CLK"), 202 PINCTRL_PIN(9, "LPSS_SPI_1_FS0"), 203 PINCTRL_PIN(10, "LPSS_SPI_1_FS1"), 204 PINCTRL_PIN(11, "LPSS_SPI_1_FS2"), 205 PINCTRL_PIN(12, "LPSS_SPI_1_RXD"), 206 PINCTRL_PIN(13, "LPSS_SPI_1_TXD"), 207 PINCTRL_PIN(14, "FST_SPI_CS0_B"), 208 PINCTRL_PIN(15, "FST_SPI_CS1_B"), 209 PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), 210 PINCTRL_PIN(17, "FST_SPI_MISO_IO1"), 211 PINCTRL_PIN(18, "FST_SPI_IO2"), 212 PINCTRL_PIN(19, "FST_SPI_IO3"), 213 PINCTRL_PIN(20, "FST_SPI_CLK"), 214 PINCTRL_PIN(21, "FST_SPI_CLK_FB"), 215 PINCTRL_PIN(22, "PMU_PLTRST_B"), 216 PINCTRL_PIN(23, "PMU_PWRBTN_B"), 217 PINCTRL_PIN(24, "PMU_SLP_S0_B"), 218 PINCTRL_PIN(25, "PMU_SLP_S3_B"), 219 PINCTRL_PIN(26, "PMU_SLP_S4_B"), 220 PINCTRL_PIN(27, "SUSPWRDNACK"), 221 PINCTRL_PIN(28, "EMMC_PWR_EN_B"), 222 PINCTRL_PIN(29, "PMU_AC_PRESENT"), 223 PINCTRL_PIN(30, "PMU_BATLOW_B"), 224 PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), 225 PINCTRL_PIN(32, "PMU_SUSCLK"), 226 PINCTRL_PIN(33, "SUS_STAT_B"), 227 PINCTRL_PIN(34, "LPSS_I2C5_SDA"), 228 PINCTRL_PIN(35, "LPSS_I2C5_SCL"), 229 PINCTRL_PIN(36, "LPSS_I2C6_SDA"), 230 PINCTRL_PIN(37, "LPSS_I2C6_SCL"), 231 PINCTRL_PIN(38, "LPSS_I2C7_SDA"), 232 PINCTRL_PIN(39, "LPSS_I2C7_SCL"), 233 PINCTRL_PIN(40, "PCIE_WAKE0_B"), 234 PINCTRL_PIN(41, "PCIE_WAKE1_B"), 235 PINCTRL_PIN(42, "PCIE_WAKE2_B"), 236 PINCTRL_PIN(43, "PCIE_WAKE3_B"), 237 PINCTRL_PIN(44, "PCIE_CLKREQ0_B"), 238 PINCTRL_PIN(45, "PCIE_CLKREQ1_B"), 239 PINCTRL_PIN(46, "PCIE_CLKREQ2_B"), 240 PINCTRL_PIN(47, "PCIE_CLKREQ3_B"), 241 PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"), 242 PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"), 243 PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"), 244 PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"), 245 PINCTRL_PIN(52, "PANEL0_VDDEN"), 246 PINCTRL_PIN(53, "PANEL0_BKLTEN"), 247 PINCTRL_PIN(54, "PANEL0_BKLTCTL"), 248 PINCTRL_PIN(55, "HV_DDI0_HPD"), 249 PINCTRL_PIN(56, "HV_DDI1_HPD"), 250 PINCTRL_PIN(57, "HV_EDP_HPD"), 251 PINCTRL_PIN(58, "GPIO_134"), 252 PINCTRL_PIN(59, "GPIO_135"), 253 PINCTRL_PIN(60, "GPIO_136"), 254 PINCTRL_PIN(61, "GPIO_137"), 255 PINCTRL_PIN(62, "GPIO_138"), 256 PINCTRL_PIN(63, "GPIO_139"), 257 PINCTRL_PIN(64, "GPIO_140"), 258 PINCTRL_PIN(65, "GPIO_141"), 259 PINCTRL_PIN(66, "GPIO_142"), 260 PINCTRL_PIN(67, "GPIO_143"), 261 PINCTRL_PIN(68, "GPIO_144"), 262 PINCTRL_PIN(69, "GPIO_145"), 263 PINCTRL_PIN(70, "GPIO_146"), 264 PINCTRL_PIN(71, "LPC_ILB_SERIRQ"), 265 PINCTRL_PIN(72, "LPC_CLKOUT0"), 266 PINCTRL_PIN(73, "LPC_CLKOUT1"), 267 PINCTRL_PIN(74, "LPC_AD0"), 268 PINCTRL_PIN(75, "LPC_AD1"), 269 PINCTRL_PIN(76, "LPC_AD2"), 270 PINCTRL_PIN(77, "LPC_AD3"), 271 PINCTRL_PIN(78, "LPC_CLKRUNB"), 272 PINCTRL_PIN(79, "LPC_FRAMEB"), 273 }; 274 275 static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 }; 276 static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 }; 277 static const unsigned int glk_north_i2c5_pins[] = { 34, 35 }; 278 static const unsigned int glk_north_i2c6_pins[] = { 36, 37 }; 279 static const unsigned int glk_north_i2c7_pins[] = { 38, 39 }; 280 static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 }; 281 static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 }; 282 283 static const struct intel_pingroup glk_north_groups[] = { 284 PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1), 285 PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1), 286 PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1), 287 PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1), 288 PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1), 289 PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2), 290 PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2), 291 }; 292 293 static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" }; 294 static const char * const glk_north_spi1_groups[] = { "spi1_grp" }; 295 static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" }; 296 static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" }; 297 static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" }; 298 static const char * const glk_north_uart0_groups[] = { "uart0_grp" }; 299 300 static const struct intel_function glk_north_functions[] = { 301 FUNCTION("spi0", glk_north_spi0_groups), 302 FUNCTION("spi1", glk_north_spi1_groups), 303 FUNCTION("i2c5", glk_north_i2c5_groups), 304 FUNCTION("i2c6", glk_north_i2c6_groups), 305 FUNCTION("i2c7", glk_north_i2c7_groups), 306 FUNCTION("uart0", glk_north_uart0_groups), 307 }; 308 309 static const struct intel_community glk_north_communities[] = { 310 GLK_COMMUNITY(0, 79), 311 }; 312 313 static const struct intel_pinctrl_soc_data glk_north_soc_data = { 314 .uid = "2", 315 .pins = glk_north_pins, 316 .npins = ARRAY_SIZE(glk_north_pins), 317 .groups = glk_north_groups, 318 .ngroups = ARRAY_SIZE(glk_north_groups), 319 .functions = glk_north_functions, 320 .nfunctions = ARRAY_SIZE(glk_north_functions), 321 .communities = glk_north_communities, 322 .ncommunities = ARRAY_SIZE(glk_north_communities), 323 }; 324 325 static const struct pinctrl_pin_desc glk_audio_pins[] = { 326 PINCTRL_PIN(0, "AVS_I2S0_MCLK"), 327 PINCTRL_PIN(1, "AVS_I2S0_BCLK"), 328 PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"), 329 PINCTRL_PIN(3, "AVS_I2S0_SDI"), 330 PINCTRL_PIN(4, "AVS_I2S0_SDO"), 331 PINCTRL_PIN(5, "AVS_I2S1_MCLK"), 332 PINCTRL_PIN(6, "AVS_I2S1_BCLK"), 333 PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"), 334 PINCTRL_PIN(8, "AVS_I2S1_SDI"), 335 PINCTRL_PIN(9, "AVS_I2S1_SDO"), 336 PINCTRL_PIN(10, "AVS_HDA_BCLK"), 337 PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"), 338 PINCTRL_PIN(12, "AVS_HDA_SDI"), 339 PINCTRL_PIN(13, "AVS_HDA_SDO"), 340 PINCTRL_PIN(14, "AVS_HDA_RSTB"), 341 PINCTRL_PIN(15, "AVS_M_CLK_A1"), 342 PINCTRL_PIN(16, "AVS_M_CLK_B1"), 343 PINCTRL_PIN(17, "AVS_M_DATA_1"), 344 PINCTRL_PIN(18, "AVS_M_CLK_AB2"), 345 PINCTRL_PIN(19, "AVS_M_DATA_2"), 346 }; 347 348 static const struct intel_community glk_audio_communities[] = { 349 GLK_COMMUNITY(0, 19), 350 }; 351 352 static const struct intel_pinctrl_soc_data glk_audio_soc_data = { 353 .uid = "3", 354 .pins = glk_audio_pins, 355 .npins = ARRAY_SIZE(glk_audio_pins), 356 .communities = glk_audio_communities, 357 .ncommunities = ARRAY_SIZE(glk_audio_communities), 358 }; 359 360 static const struct pinctrl_pin_desc glk_scc_pins[] = { 361 PINCTRL_PIN(0, "SMB_ALERTB"), 362 PINCTRL_PIN(1, "SMB_CLK"), 363 PINCTRL_PIN(2, "SMB_DATA"), 364 PINCTRL_PIN(3, "SDCARD_LVL_WP"), 365 PINCTRL_PIN(4, "SDCARD_CLK"), 366 PINCTRL_PIN(5, "SDCARD_CLK_FB"), 367 PINCTRL_PIN(6, "SDCARD_D0"), 368 PINCTRL_PIN(7, "SDCARD_D1"), 369 PINCTRL_PIN(8, "SDCARD_D2"), 370 PINCTRL_PIN(9, "SDCARD_D3"), 371 PINCTRL_PIN(10, "SDCARD_CMD"), 372 PINCTRL_PIN(11, "SDCARD_CD_B"), 373 PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"), 374 PINCTRL_PIN(13, "GPIO_210"), 375 PINCTRL_PIN(14, "OSC_CLK_OUT_0"), 376 PINCTRL_PIN(15, "OSC_CLK_OUT_1"), 377 PINCTRL_PIN(16, "CNV_BRI_DT"), 378 PINCTRL_PIN(17, "CNV_BRI_RSP"), 379 PINCTRL_PIN(18, "CNV_RGI_DT"), 380 PINCTRL_PIN(19, "CNV_RGI_RSP"), 381 PINCTRL_PIN(20, "CNV_RF_RESET_B"), 382 PINCTRL_PIN(21, "XTAL_CLKREQ"), 383 PINCTRL_PIN(22, "SDIO_CLK_FB"), 384 PINCTRL_PIN(23, "EMMC0_CLK"), 385 PINCTRL_PIN(24, "EMMC0_CLK_FB"), 386 PINCTRL_PIN(25, "EMMC0_D0"), 387 PINCTRL_PIN(26, "EMMC0_D1"), 388 PINCTRL_PIN(27, "EMMC0_D2"), 389 PINCTRL_PIN(28, "EMMC0_D3"), 390 PINCTRL_PIN(29, "EMMC0_D4"), 391 PINCTRL_PIN(30, "EMMC0_D5"), 392 PINCTRL_PIN(31, "EMMC0_D6"), 393 PINCTRL_PIN(32, "EMMC0_D7"), 394 PINCTRL_PIN(33, "EMMC0_CMD"), 395 PINCTRL_PIN(34, "EMMC0_STROBE"), 396 }; 397 398 static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 }; 399 static const unsigned int glk_scc_sdcard_pins[] = { 400 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 401 }; 402 static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 }; 403 static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 }; 404 static const unsigned int glk_scc_emmc_pins[] = { 405 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 406 }; 407 408 static const struct intel_pingroup glk_scc_groups[] = { 409 PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2), 410 PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1), 411 PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2), 412 PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3), 413 PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1), 414 }; 415 416 static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" }; 417 static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" }; 418 static const char * const glk_scc_sdio_groups[] = { "sdio_grp" }; 419 static const char * const glk_scc_uart1_groups[] = { "uart1_grp" }; 420 static const char * const glk_scc_emmc_groups[] = { "emmc_grp" }; 421 422 static const struct intel_function glk_scc_functions[] = { 423 FUNCTION("i2c7", glk_scc_i2c7_groups), 424 FUNCTION("sdcard", glk_scc_sdcard_groups), 425 FUNCTION("sdio", glk_scc_sdio_groups), 426 FUNCTION("uart1", glk_scc_uart1_groups), 427 FUNCTION("emmc", glk_scc_emmc_groups), 428 }; 429 430 static const struct intel_community glk_scc_communities[] = { 431 GLK_COMMUNITY(0, 34), 432 }; 433 434 static const struct intel_pinctrl_soc_data glk_scc_soc_data = { 435 .uid = "4", 436 .pins = glk_scc_pins, 437 .npins = ARRAY_SIZE(glk_scc_pins), 438 .groups = glk_scc_groups, 439 .ngroups = ARRAY_SIZE(glk_scc_groups), 440 .functions = glk_scc_functions, 441 .nfunctions = ARRAY_SIZE(glk_scc_functions), 442 .communities = glk_scc_communities, 443 .ncommunities = ARRAY_SIZE(glk_scc_communities), 444 }; 445 446 static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { 447 &glk_northwest_soc_data, 448 &glk_north_soc_data, 449 &glk_audio_soc_data, 450 &glk_scc_soc_data, 451 NULL, 452 }; 453 454 static const struct acpi_device_id glk_pinctrl_acpi_match[] = { 455 { "INT3453" }, 456 { } 457 }; 458 MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); 459 460 static int glk_pinctrl_probe(struct platform_device *pdev) 461 { 462 const struct intel_pinctrl_soc_data *soc_data = NULL; 463 struct acpi_device *adev; 464 int i; 465 466 adev = ACPI_COMPANION(&pdev->dev); 467 if (!adev) 468 return -ENODEV; 469 470 for (i = 0; glk_pinctrl_soc_data[i]; i++) { 471 if (!strcmp(adev->pnp.unique_id, 472 glk_pinctrl_soc_data[i]->uid)) { 473 soc_data = glk_pinctrl_soc_data[i]; 474 break; 475 } 476 } 477 478 if (!soc_data) 479 return -ENODEV; 480 481 return intel_pinctrl_probe(pdev, soc_data); 482 } 483 484 static const struct dev_pm_ops glk_pinctrl_pm_ops = { 485 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, 486 intel_pinctrl_resume) 487 }; 488 489 static struct platform_driver glk_pinctrl_driver = { 490 .probe = glk_pinctrl_probe, 491 .driver = { 492 .name = "geminilake-pinctrl", 493 .acpi_match_table = glk_pinctrl_acpi_match, 494 .pm = &glk_pinctrl_pm_ops, 495 }, 496 }; 497 498 static int __init glk_pinctrl_init(void) 499 { 500 return platform_driver_register(&glk_pinctrl_driver); 501 } 502 subsys_initcall(glk_pinctrl_init); 503 504 static void __exit glk_pinctrl_exit(void) 505 { 506 platform_driver_unregister(&glk_pinctrl_driver); 507 } 508 module_exit(glk_pinctrl_exit); 509 510 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 511 MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); 512 MODULE_LICENSE("GPL v2"); 513