1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Elkhart Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-intel.h" 16 17 #define EHL_PAD_OWN 0x020 18 #define EHL_PADCFGLOCK 0x080 19 #define EHL_HOSTSW_OWN 0x0b0 20 #define EHL_GPI_IS 0x100 21 #define EHL_GPI_IE 0x120 22 23 #define EHL_GPP(r, s, e) \ 24 { \ 25 .reg_num = (r), \ 26 .base = (s), \ 27 .size = ((e) - (s) + 1), \ 28 } 29 30 #define EHL_COMMUNITY(s, e, g) \ 31 { \ 32 .padown_offset = EHL_PAD_OWN, \ 33 .padcfglock_offset = EHL_PADCFGLOCK, \ 34 .hostown_offset = EHL_HOSTSW_OWN, \ 35 .is_offset = EHL_GPI_IS, \ 36 .ie_offset = EHL_GPI_IE, \ 37 .pin_base = (s), \ 38 .npins = ((e) - (s) + 1), \ 39 .gpps = (g), \ 40 .ngpps = ARRAY_SIZE(g), \ 41 } 42 43 /* Elkhart Lake */ 44 static const struct pinctrl_pin_desc ehl_community0_pins[] = { 45 /* GPP_B */ 46 PINCTRL_PIN(0, "CORE_VID_0"), 47 PINCTRL_PIN(1, "CORE_VID_1"), 48 PINCTRL_PIN(2, "VRALERTB"), 49 PINCTRL_PIN(3, "CPU_GP_2"), 50 PINCTRL_PIN(4, "CPU_GP_3"), 51 PINCTRL_PIN(5, "OSE_I2C0_SCLK"), 52 PINCTRL_PIN(6, "OSE_I2C0_SDAT"), 53 PINCTRL_PIN(7, "OSE_I2C1_SCLK"), 54 PINCTRL_PIN(8, "OSE_I2C1_SDAT"), 55 PINCTRL_PIN(9, "I2C5_SDA"), 56 PINCTRL_PIN(10, "I2C5_SCL"), 57 PINCTRL_PIN(11, "PMCALERTB"), 58 PINCTRL_PIN(12, "SLP_S0B"), 59 PINCTRL_PIN(13, "PLTRSTB"), 60 PINCTRL_PIN(14, "SPKR"), 61 PINCTRL_PIN(15, "GSPI0_CS0B"), 62 PINCTRL_PIN(16, "GSPI0_CLK"), 63 PINCTRL_PIN(17, "GSPI0_MISO"), 64 PINCTRL_PIN(18, "GSPI0_MOSI"), 65 PINCTRL_PIN(19, "GSPI1_CS0B"), 66 PINCTRL_PIN(20, "GSPI1_CLK"), 67 PINCTRL_PIN(21, "GSPI1_MISO"), 68 PINCTRL_PIN(22, "GSPI1_MOSI"), 69 PINCTRL_PIN(23, "GPPC_B_23"), 70 PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), 71 PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), 72 /* GPP_T */ 73 PINCTRL_PIN(26, "OSE_QEPA_2"), 74 PINCTRL_PIN(27, "OSE_QEPB_2"), 75 PINCTRL_PIN(28, "OSE_QEPI_2"), 76 PINCTRL_PIN(29, "GPPC_T_3"), 77 PINCTRL_PIN(30, "RGMII0_INT"), 78 PINCTRL_PIN(31, "RGMII0_RESETB"), 79 PINCTRL_PIN(32, "RGMII0_AUXTS"), 80 PINCTRL_PIN(33, "RGMII0_PPS"), 81 PINCTRL_PIN(34, "USB2_OCB_2"), 82 PINCTRL_PIN(35, "OSE_HSUART2_EN"), 83 PINCTRL_PIN(36, "OSE_HSUART2_RE"), 84 PINCTRL_PIN(37, "USB2_OCB_3"), 85 PINCTRL_PIN(38, "OSE_UART2_RXD"), 86 PINCTRL_PIN(39, "OSE_UART2_TXD"), 87 PINCTRL_PIN(40, "OSE_UART2_RTSB"), 88 PINCTRL_PIN(41, "OSE_UART2_CTSB"), 89 /* GPP_G */ 90 PINCTRL_PIN(42, "SD3_CMD"), 91 PINCTRL_PIN(43, "SD3_D0"), 92 PINCTRL_PIN(44, "SD3_D1"), 93 PINCTRL_PIN(45, "SD3_D2"), 94 PINCTRL_PIN(46, "SD3_D3"), 95 PINCTRL_PIN(47, "SD3_CDB"), 96 PINCTRL_PIN(48, "SD3_CLK"), 97 PINCTRL_PIN(49, "I2S2_SCLK"), 98 PINCTRL_PIN(50, "I2S2_SFRM"), 99 PINCTRL_PIN(51, "I2S2_TXD"), 100 PINCTRL_PIN(52, "I2S2_RXD"), 101 PINCTRL_PIN(53, "I2S3_SCLK"), 102 PINCTRL_PIN(54, "I2S3_SFRM"), 103 PINCTRL_PIN(55, "I2S3_TXD"), 104 PINCTRL_PIN(56, "I2S3_RXD"), 105 PINCTRL_PIN(57, "ESPI_IO_0"), 106 PINCTRL_PIN(58, "ESPI_IO_1"), 107 PINCTRL_PIN(59, "ESPI_IO_2"), 108 PINCTRL_PIN(60, "ESPI_IO_3"), 109 PINCTRL_PIN(61, "I2S1_SCLK"), 110 PINCTRL_PIN(62, "ESPI_CSB"), 111 PINCTRL_PIN(63, "ESPI_CLK"), 112 PINCTRL_PIN(64, "ESPI_RESETB"), 113 PINCTRL_PIN(65, "SD3_WP"), 114 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), 115 }; 116 117 static const struct intel_padgroup ehl_community0_gpps[] = { 118 EHL_GPP(0, 0, 25), /* GPP_B */ 119 EHL_GPP(1, 26, 41), /* GPP_T */ 120 EHL_GPP(2, 42, 66), /* GPP_G */ 121 }; 122 123 static const struct intel_community ehl_community0[] = { 124 EHL_COMMUNITY(0, 66, ehl_community0_gpps), 125 }; 126 127 static const struct intel_pinctrl_soc_data ehl_community0_soc_data = { 128 .uid = "0", 129 .pins = ehl_community0_pins, 130 .npins = ARRAY_SIZE(ehl_community0_pins), 131 .communities = ehl_community0, 132 .ncommunities = ARRAY_SIZE(ehl_community0), 133 }; 134 135 static const struct pinctrl_pin_desc ehl_community1_pins[] = { 136 /* GPP_V */ 137 PINCTRL_PIN(0, "EMMC_CMD"), 138 PINCTRL_PIN(1, "EMMC_DATA0"), 139 PINCTRL_PIN(2, "EMMC_DATA1"), 140 PINCTRL_PIN(3, "EMMC_DATA2"), 141 PINCTRL_PIN(4, "EMMC_DATA3"), 142 PINCTRL_PIN(5, "EMMC_DATA4"), 143 PINCTRL_PIN(6, "EMMC_DATA5"), 144 PINCTRL_PIN(7, "EMMC_DATA6"), 145 PINCTRL_PIN(8, "EMMC_DATA7"), 146 PINCTRL_PIN(9, "EMMC_RCLK"), 147 PINCTRL_PIN(10, "EMMC_CLK"), 148 PINCTRL_PIN(11, "EMMC_RESETB"), 149 PINCTRL_PIN(12, "OSE_TGPIO0"), 150 PINCTRL_PIN(13, "OSE_TGPIO1"), 151 PINCTRL_PIN(14, "OSE_TGPIO2"), 152 PINCTRL_PIN(15, "OSE_TGPIO3"), 153 /* GPP_H */ 154 PINCTRL_PIN(16, "RGMII1_INT"), 155 PINCTRL_PIN(17, "RGMII1_RESETB"), 156 PINCTRL_PIN(18, "RGMII1_AUXTS"), 157 PINCTRL_PIN(19, "RGMII1_PPS"), 158 PINCTRL_PIN(20, "I2C2_SDA"), 159 PINCTRL_PIN(21, "I2C2_SCL"), 160 PINCTRL_PIN(22, "I2C3_SDA"), 161 PINCTRL_PIN(23, "I2C3_SCL"), 162 PINCTRL_PIN(24, "I2C4_SDA"), 163 PINCTRL_PIN(25, "I2C4_SCL"), 164 PINCTRL_PIN(26, "SRCCLKREQB_4"), 165 PINCTRL_PIN(27, "SRCCLKREQB_5"), 166 PINCTRL_PIN(28, "OSE_UART1_RXD"), 167 PINCTRL_PIN(29, "OSE_UART1_TXD"), 168 PINCTRL_PIN(30, "GPPC_H_14"), 169 PINCTRL_PIN(31, "OSE_UART1_CTSB"), 170 PINCTRL_PIN(32, "PCIE_LNK_DOWN"), 171 PINCTRL_PIN(33, "SD_PWR_EN_B"), 172 PINCTRL_PIN(34, "CPU_C10_GATEB"), 173 PINCTRL_PIN(35, "GPPC_H_19"), 174 PINCTRL_PIN(36, "OSE_PWM7"), 175 PINCTRL_PIN(37, "OSE_HSUART1_DE"), 176 PINCTRL_PIN(38, "OSE_HSUART1_RE"), 177 PINCTRL_PIN(39, "OSE_HSUART1_EN"), 178 /* GPP_D */ 179 PINCTRL_PIN(40, "OSE_QEPA_0"), 180 PINCTRL_PIN(41, "OSE_QEPB_0"), 181 PINCTRL_PIN(42, "OSE_QEPI_0"), 182 PINCTRL_PIN(43, "OSE_PWM6"), 183 PINCTRL_PIN(44, "OSE_PWM2"), 184 PINCTRL_PIN(45, "SRCCLKREQB_0"), 185 PINCTRL_PIN(46, "SRCCLKREQB_1"), 186 PINCTRL_PIN(47, "SRCCLKREQB_2"), 187 PINCTRL_PIN(48, "SRCCLKREQB_3"), 188 PINCTRL_PIN(49, "OSE_SPI0_CSB"), 189 PINCTRL_PIN(50, "OSE_SPI0_SCLK"), 190 PINCTRL_PIN(51, "OSE_SPI0_MISO"), 191 PINCTRL_PIN(52, "OSE_SPI0_MOSI"), 192 PINCTRL_PIN(53, "OSE_QEPA_1"), 193 PINCTRL_PIN(54, "OSE_QEPB_1"), 194 PINCTRL_PIN(55, "OSE_PWM3"), 195 PINCTRL_PIN(56, "OSE_QEPI_1"), 196 PINCTRL_PIN(57, "OSE_PWM4"), 197 PINCTRL_PIN(58, "OSE_PWM5"), 198 PINCTRL_PIN(59, "I2S_MCLK1_OUT"), 199 PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"), 200 /* GPP_U */ 201 PINCTRL_PIN(61, "RGMII2_INT"), 202 PINCTRL_PIN(62, "RGMII2_RESETB"), 203 PINCTRL_PIN(63, "RGMII2_PPS"), 204 PINCTRL_PIN(64, "RGMII2_AUXTS"), 205 PINCTRL_PIN(65, "ISI_SPIM_CS"), 206 PINCTRL_PIN(66, "ISI_SPIM_SCLK"), 207 PINCTRL_PIN(67, "ISI_SPIM_MISO"), 208 PINCTRL_PIN(68, "OSE_QEPA_3"), 209 PINCTRL_PIN(69, "ISI_SPIS_CS"), 210 PINCTRL_PIN(70, "ISI_SPIS_SCLK"), 211 PINCTRL_PIN(71, "ISI_SPIS_MISO"), 212 PINCTRL_PIN(72, "OSE_QEPB_3"), 213 PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"), 214 PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"), 215 PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"), 216 PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"), 217 PINCTRL_PIN(77, "ISI_OKNOK_0"), 218 PINCTRL_PIN(78, "ISI_OKNOK_1"), 219 PINCTRL_PIN(79, "ISI_ALERT"), 220 PINCTRL_PIN(80, "OSE_QEPI_3"), 221 PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"), 222 PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"), 223 PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"), 224 PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"), 225 /* vGPIO */ 226 PINCTRL_PIN(85, "CNV_BTEN"), 227 PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"), 228 PINCTRL_PIN(87, "CNV_BT_IF_SELECT"), 229 PINCTRL_PIN(88, "vCNV_BT_UART_TXD"), 230 PINCTRL_PIN(89, "vCNV_BT_UART_RXD"), 231 PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"), 232 PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"), 233 PINCTRL_PIN(92, "vCNV_MFUART1_TXD"), 234 PINCTRL_PIN(93, "vCNV_MFUART1_RXD"), 235 PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"), 236 PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"), 237 PINCTRL_PIN(96, "vUART0_TXD"), 238 PINCTRL_PIN(97, "vUART0_RXD"), 239 PINCTRL_PIN(98, "vUART0_CTS_B"), 240 PINCTRL_PIN(99, "vUART0_RTS_B"), 241 PINCTRL_PIN(100, "vOSE_UART0_TXD"), 242 PINCTRL_PIN(101, "vOSE_UART0_RXD"), 243 PINCTRL_PIN(102, "vOSE_UART0_CTS_B"), 244 PINCTRL_PIN(103, "vOSE_UART0_RTS_B"), 245 PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"), 246 PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"), 247 PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"), 248 PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"), 249 PINCTRL_PIN(108, "vI2S2_SCLK"), 250 PINCTRL_PIN(109, "vI2S2_SFRM"), 251 PINCTRL_PIN(110, "vI2S2_TXD"), 252 PINCTRL_PIN(111, "vI2S2_RXD"), 253 PINCTRL_PIN(112, "vSD3_CD_B"), 254 }; 255 256 static const struct intel_padgroup ehl_community1_gpps[] = { 257 EHL_GPP(0, 0, 15), /* GPP_V */ 258 EHL_GPP(1, 16, 39), /* GPP_H */ 259 EHL_GPP(2, 40, 60), /* GPP_D */ 260 EHL_GPP(3, 61, 84), /* GPP_U */ 261 EHL_GPP(4, 85, 112), /* vGPIO */ 262 }; 263 264 static const struct intel_community ehl_community1[] = { 265 EHL_COMMUNITY(0, 112, ehl_community1_gpps), 266 }; 267 268 static const struct intel_pinctrl_soc_data ehl_community1_soc_data = { 269 .uid = "1", 270 .pins = ehl_community1_pins, 271 .npins = ARRAY_SIZE(ehl_community1_pins), 272 .communities = ehl_community1, 273 .ncommunities = ARRAY_SIZE(ehl_community1), 274 }; 275 276 static const struct pinctrl_pin_desc ehl_community3_pins[] = { 277 /* CPU */ 278 PINCTRL_PIN(0, "HDACPU_SDI"), 279 PINCTRL_PIN(1, "HDACPU_SDO"), 280 PINCTRL_PIN(2, "HDACPU_BCLK"), 281 PINCTRL_PIN(3, "PM_SYNC"), 282 PINCTRL_PIN(4, "PECI"), 283 PINCTRL_PIN(5, "CPUPWRGD"), 284 PINCTRL_PIN(6, "THRMTRIPB"), 285 PINCTRL_PIN(7, "PLTRST_CPUB"), 286 PINCTRL_PIN(8, "PM_DOWN"), 287 PINCTRL_PIN(9, "TRIGGER_IN"), 288 PINCTRL_PIN(10, "TRIGGER_OUT"), 289 PINCTRL_PIN(11, "UFS_RESETB"), 290 PINCTRL_PIN(12, "CLKOUT_CPURTC"), 291 PINCTRL_PIN(13, "VCCST_OVERRIDE"), 292 PINCTRL_PIN(14, "C10_WAKE"), 293 PINCTRL_PIN(15, "PROCHOTB"), 294 PINCTRL_PIN(16, "CATERRB"), 295 /* GPP_S */ 296 PINCTRL_PIN(17, "UFS_REF_CLK_0"), 297 PINCTRL_PIN(18, "UFS_REF_CLK_1"), 298 /* GPP_A */ 299 PINCTRL_PIN(19, "RGMII0_TXDATA_3"), 300 PINCTRL_PIN(20, "RGMII0_TXDATA_2"), 301 PINCTRL_PIN(21, "RGMII0_TXDATA_1"), 302 PINCTRL_PIN(22, "RGMII0_TXDATA_0"), 303 PINCTRL_PIN(23, "RGMII0_TXCLK"), 304 PINCTRL_PIN(24, "RGMII0_TXCTL"), 305 PINCTRL_PIN(25, "RGMII0_RXCLK"), 306 PINCTRL_PIN(26, "RGMII0_RXDATA_3"), 307 PINCTRL_PIN(27, "RGMII0_RXDATA_2"), 308 PINCTRL_PIN(28, "RGMII0_RXDATA_1"), 309 PINCTRL_PIN(29, "RGMII0_RXDATA_0"), 310 PINCTRL_PIN(30, "RGMII1_TXDATA_3"), 311 PINCTRL_PIN(31, "RGMII1_TXDATA_2"), 312 PINCTRL_PIN(32, "RGMII1_TXDATA_1"), 313 PINCTRL_PIN(33, "RGMII1_TXDATA_0"), 314 PINCTRL_PIN(34, "RGMII1_TXCLK"), 315 PINCTRL_PIN(35, "RGMII1_TXCTL"), 316 PINCTRL_PIN(36, "RGMII1_RXCLK"), 317 PINCTRL_PIN(37, "RGMII1_RXCTL"), 318 PINCTRL_PIN(38, "RGMII1_RXDATA_3"), 319 PINCTRL_PIN(39, "RGMII1_RXDATA_2"), 320 PINCTRL_PIN(40, "RGMII1_RXDATA_1"), 321 PINCTRL_PIN(41, "RGMII1_RXDATA_0"), 322 PINCTRL_PIN(42, "RGMII0_RXCTL"), 323 /* vGPIO_3 */ 324 PINCTRL_PIN(43, "ESPI_USB_OCB_0"), 325 PINCTRL_PIN(44, "ESPI_USB_OCB_1"), 326 PINCTRL_PIN(45, "ESPI_USB_OCB_2"), 327 PINCTRL_PIN(46, "ESPI_USB_OCB_3"), 328 }; 329 330 static const struct intel_padgroup ehl_community3_gpps[] = { 331 EHL_GPP(0, 0, 16), /* CPU */ 332 EHL_GPP(1, 17, 18), /* GPP_S */ 333 EHL_GPP(2, 19, 42), /* GPP_A */ 334 EHL_GPP(3, 43, 46), /* vGPIO_3 */ 335 }; 336 337 static const struct intel_community ehl_community3[] = { 338 EHL_COMMUNITY(0, 46, ehl_community3_gpps), 339 }; 340 341 static const struct intel_pinctrl_soc_data ehl_community3_soc_data = { 342 .uid = "3", 343 .pins = ehl_community3_pins, 344 .npins = ARRAY_SIZE(ehl_community3_pins), 345 .communities = ehl_community3, 346 .ncommunities = ARRAY_SIZE(ehl_community3), 347 }; 348 349 static const struct pinctrl_pin_desc ehl_community4_pins[] = { 350 /* GPP_C */ 351 PINCTRL_PIN(0, "SMBCLK"), 352 PINCTRL_PIN(1, "SMBDATA"), 353 PINCTRL_PIN(2, "OSE_PWM0"), 354 PINCTRL_PIN(3, "RGMII0_MDC"), 355 PINCTRL_PIN(4, "RGMII0_MDIO"), 356 PINCTRL_PIN(5, "OSE_PWM1"), 357 PINCTRL_PIN(6, "RGMII1_MDC"), 358 PINCTRL_PIN(7, "RGMII1_MDIO"), 359 PINCTRL_PIN(8, "OSE_TGPIO4"), 360 PINCTRL_PIN(9, "OSE_HSUART0_EN"), 361 PINCTRL_PIN(10, "OSE_TGPIO5"), 362 PINCTRL_PIN(11, "OSE_HSUART0_RE"), 363 PINCTRL_PIN(12, "OSE_UART0_RXD"), 364 PINCTRL_PIN(13, "OSE_UART0_TXD"), 365 PINCTRL_PIN(14, "OSE_UART0_RTSB"), 366 PINCTRL_PIN(15, "OSE_UART0_CTSB"), 367 PINCTRL_PIN(16, "RGMII2_MDIO"), 368 PINCTRL_PIN(17, "RGMII2_MDC"), 369 PINCTRL_PIN(18, "OSE_I2C4_SDAT"), 370 PINCTRL_PIN(19, "OSE_I2C4_SCLK"), 371 PINCTRL_PIN(20, "OSE_UART4_RXD"), 372 PINCTRL_PIN(21, "OSE_UART4_TXD"), 373 PINCTRL_PIN(22, "OSE_UART4_RTSB"), 374 PINCTRL_PIN(23, "OSE_UART4_CTSB"), 375 /* GPP_F */ 376 PINCTRL_PIN(24, "CNV_BRI_DT"), 377 PINCTRL_PIN(25, "CNV_BRI_RSP"), 378 PINCTRL_PIN(26, "CNV_RGI_DT"), 379 PINCTRL_PIN(27, "CNV_RGI_RSP"), 380 PINCTRL_PIN(28, "CNV_RF_RESET_B"), 381 PINCTRL_PIN(29, "EMMC_HIP_MON"), 382 PINCTRL_PIN(30, "CNV_PA_BLANKING"), 383 PINCTRL_PIN(31, "OSE_I2S1_SCLK"), 384 PINCTRL_PIN(32, "I2S_MCLK2_INOUT"), 385 PINCTRL_PIN(33, "BOOTMPC"), 386 PINCTRL_PIN(34, "OSE_I2S1_SFRM"), 387 PINCTRL_PIN(35, "GPPC_F_11"), 388 PINCTRL_PIN(36, "GSXDOUT"), 389 PINCTRL_PIN(37, "GSXSLOAD"), 390 PINCTRL_PIN(38, "GSXDIN"), 391 PINCTRL_PIN(39, "GSXSRESETB"), 392 PINCTRL_PIN(40, "GSXCLK"), 393 PINCTRL_PIN(41, "GPPC_F_17"), 394 PINCTRL_PIN(42, "OSE_I2S1_TXD"), 395 PINCTRL_PIN(43, "OSE_I2S1_RXD"), 396 PINCTRL_PIN(44, "EXT_PWR_GATEB"), 397 PINCTRL_PIN(45, "EXT_PWR_GATE2B"), 398 PINCTRL_PIN(46, "VNN_CTRL"), 399 PINCTRL_PIN(47, "V1P05_CTRL"), 400 PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"), 401 /* HVCMOS */ 402 PINCTRL_PIN(49, "L_BKLTEN"), 403 PINCTRL_PIN(50, "L_BKLTCTL"), 404 PINCTRL_PIN(51, "L_VDDEN"), 405 PINCTRL_PIN(52, "SYS_PWROK"), 406 PINCTRL_PIN(53, "SYS_RESETB"), 407 PINCTRL_PIN(54, "MLK_RSTB"), 408 /* GPP_E */ 409 PINCTRL_PIN(55, "SATA_LEDB"), 410 PINCTRL_PIN(56, "GPPC_E_1"), 411 PINCTRL_PIN(57, "GPPC_E_2"), 412 PINCTRL_PIN(58, "DDSP_HPD_B"), 413 PINCTRL_PIN(59, "SATA_DEVSLP_0"), 414 PINCTRL_PIN(60, "DDPB_CTRLDATA"), 415 PINCTRL_PIN(61, "GPPC_E_6"), 416 PINCTRL_PIN(62, "DDPB_CTRLCLK"), 417 PINCTRL_PIN(63, "GPPC_E_8"), 418 PINCTRL_PIN(64, "USB2_OCB_0"), 419 PINCTRL_PIN(65, "GPPC_E_10"), 420 PINCTRL_PIN(66, "GPPC_E_11"), 421 PINCTRL_PIN(67, "GPPC_E_12"), 422 PINCTRL_PIN(68, "GPPC_E_13"), 423 PINCTRL_PIN(69, "DDSP_HPD_A"), 424 PINCTRL_PIN(70, "OSE_I2S0_RXD"), 425 PINCTRL_PIN(71, "OSE_I2S0_TXD"), 426 PINCTRL_PIN(72, "DDSP_HPD_C"), 427 PINCTRL_PIN(73, "DDPA_CTRLDATA"), 428 PINCTRL_PIN(74, "DDPA_CTRLCLK"), 429 PINCTRL_PIN(75, "OSE_I2S0_SCLK"), 430 PINCTRL_PIN(76, "OSE_I2S0_SFRM"), 431 PINCTRL_PIN(77, "DDPC_CTRLDATA"), 432 PINCTRL_PIN(78, "DDPC_CTRLCLK"), 433 PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"), 434 }; 435 436 static const struct intel_padgroup ehl_community4_gpps[] = { 437 EHL_GPP(0, 0, 23), /* GPP_C */ 438 EHL_GPP(1, 24, 48), /* GPP_F */ 439 EHL_GPP(2, 49, 54), /* HVCMOS */ 440 EHL_GPP(3, 55, 79), /* GPP_E */ 441 }; 442 443 static const struct intel_community ehl_community4[] = { 444 EHL_COMMUNITY(0, 79, ehl_community4_gpps), 445 }; 446 447 static const struct intel_pinctrl_soc_data ehl_community4_soc_data = { 448 .uid = "4", 449 .pins = ehl_community4_pins, 450 .npins = ARRAY_SIZE(ehl_community4_pins), 451 .communities = ehl_community4, 452 .ncommunities = ARRAY_SIZE(ehl_community4), 453 }; 454 455 static const struct pinctrl_pin_desc ehl_community5_pins[] = { 456 /* GPP_R */ 457 PINCTRL_PIN(0, "HDA_BCLK"), 458 PINCTRL_PIN(1, "HDA_SYNC"), 459 PINCTRL_PIN(2, "HDA_SDO"), 460 PINCTRL_PIN(3, "HDA_SDI_0"), 461 PINCTRL_PIN(4, "HDA_RSTB"), 462 PINCTRL_PIN(5, "HDA_SDI_1"), 463 PINCTRL_PIN(6, "GPP_R_6"), 464 PINCTRL_PIN(7, "GPP_R_7"), 465 }; 466 467 static const struct intel_padgroup ehl_community5_gpps[] = { 468 EHL_GPP(0, 0, 7), /* GPP_R */ 469 }; 470 471 static const struct intel_community ehl_community5[] = { 472 EHL_COMMUNITY(0, 7, ehl_community5_gpps), 473 }; 474 475 static const struct intel_pinctrl_soc_data ehl_community5_soc_data = { 476 .uid = "5", 477 .pins = ehl_community5_pins, 478 .npins = ARRAY_SIZE(ehl_community5_pins), 479 .communities = ehl_community5, 480 .ncommunities = ARRAY_SIZE(ehl_community5), 481 }; 482 483 static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = { 484 &ehl_community0_soc_data, 485 &ehl_community1_soc_data, 486 &ehl_community3_soc_data, 487 &ehl_community4_soc_data, 488 &ehl_community5_soc_data, 489 NULL 490 }; 491 492 static const struct acpi_device_id ehl_pinctrl_acpi_match[] = { 493 { "INTC1020", (kernel_ulong_t)ehl_soc_data_array }, 494 { } 495 }; 496 MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match); 497 498 static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops); 499 500 static struct platform_driver ehl_pinctrl_driver = { 501 .probe = intel_pinctrl_probe_by_uid, 502 .driver = { 503 .name = "elkhartlake-pinctrl", 504 .acpi_match_table = ehl_pinctrl_acpi_match, 505 .pm = &ehl_pinctrl_pm_ops, 506 }, 507 }; 508 509 module_platform_driver(ehl_pinctrl_driver); 510 511 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 512 MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver"); 513 MODULE_LICENSE("GPL v2"); 514