1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Elkhart Lake PCH pinctrl/GPIO driver
4  *
5  * Copyright (C) 2019, Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  */
8 
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 
13 #include <linux/pinctrl/pinctrl.h>
14 
15 #include "pinctrl-intel.h"
16 
17 #define EHL_PAD_OWN	0x020
18 #define EHL_PADCFGLOCK	0x080
19 #define EHL_HOSTSW_OWN	0x0b0
20 #define EHL_GPI_IS	0x100
21 #define EHL_GPI_IE	0x120
22 
23 #define EHL_GPP(r, s, e)				\
24 	{						\
25 		.reg_num = (r),				\
26 		.base = (s),				\
27 		.size = ((e) - (s) + 1),		\
28 	}
29 
30 #define EHL_COMMUNITY(b, s, e, g)			\
31 	INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
32 
33 /* Elkhart Lake */
34 static const struct pinctrl_pin_desc ehl_community0_pins[] = {
35 	/* GPP_B */
36 	PINCTRL_PIN(0, "CORE_VID_0"),
37 	PINCTRL_PIN(1, "CORE_VID_1"),
38 	PINCTRL_PIN(2, "VRALERTB"),
39 	PINCTRL_PIN(3, "CPU_GP_2"),
40 	PINCTRL_PIN(4, "CPU_GP_3"),
41 	PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
42 	PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
43 	PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
44 	PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
45 	PINCTRL_PIN(9, "I2C5_SDA"),
46 	PINCTRL_PIN(10, "I2C5_SCL"),
47 	PINCTRL_PIN(11, "PMCALERTB"),
48 	PINCTRL_PIN(12, "SLP_S0B"),
49 	PINCTRL_PIN(13, "PLTRSTB"),
50 	PINCTRL_PIN(14, "SPKR"),
51 	PINCTRL_PIN(15, "GSPI0_CS0B"),
52 	PINCTRL_PIN(16, "GSPI0_CLK"),
53 	PINCTRL_PIN(17, "GSPI0_MISO"),
54 	PINCTRL_PIN(18, "GSPI0_MOSI"),
55 	PINCTRL_PIN(19, "GSPI1_CS0B"),
56 	PINCTRL_PIN(20, "GSPI1_CLK"),
57 	PINCTRL_PIN(21, "GSPI1_MISO"),
58 	PINCTRL_PIN(22, "GSPI1_MOSI"),
59 	PINCTRL_PIN(23, "GPPC_B_23"),
60 	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
61 	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
62 	/* GPP_T */
63 	PINCTRL_PIN(26, "OSE_QEPA_2"),
64 	PINCTRL_PIN(27, "OSE_QEPB_2"),
65 	PINCTRL_PIN(28, "OSE_QEPI_2"),
66 	PINCTRL_PIN(29, "GPPC_T_3"),
67 	PINCTRL_PIN(30, "RGMII0_INT"),
68 	PINCTRL_PIN(31, "RGMII0_RESETB"),
69 	PINCTRL_PIN(32, "RGMII0_AUXTS"),
70 	PINCTRL_PIN(33, "RGMII0_PPS"),
71 	PINCTRL_PIN(34, "USB2_OCB_2"),
72 	PINCTRL_PIN(35, "OSE_HSUART2_EN"),
73 	PINCTRL_PIN(36, "OSE_HSUART2_RE"),
74 	PINCTRL_PIN(37, "USB2_OCB_3"),
75 	PINCTRL_PIN(38, "OSE_UART2_RXD"),
76 	PINCTRL_PIN(39, "OSE_UART2_TXD"),
77 	PINCTRL_PIN(40, "OSE_UART2_RTSB"),
78 	PINCTRL_PIN(41, "OSE_UART2_CTSB"),
79 	/* GPP_G */
80 	PINCTRL_PIN(42, "SD3_CMD"),
81 	PINCTRL_PIN(43, "SD3_D0"),
82 	PINCTRL_PIN(44, "SD3_D1"),
83 	PINCTRL_PIN(45, "SD3_D2"),
84 	PINCTRL_PIN(46, "SD3_D3"),
85 	PINCTRL_PIN(47, "SD3_CDB"),
86 	PINCTRL_PIN(48, "SD3_CLK"),
87 	PINCTRL_PIN(49, "I2S2_SCLK"),
88 	PINCTRL_PIN(50, "I2S2_SFRM"),
89 	PINCTRL_PIN(51, "I2S2_TXD"),
90 	PINCTRL_PIN(52, "I2S2_RXD"),
91 	PINCTRL_PIN(53, "I2S3_SCLK"),
92 	PINCTRL_PIN(54, "I2S3_SFRM"),
93 	PINCTRL_PIN(55, "I2S3_TXD"),
94 	PINCTRL_PIN(56, "I2S3_RXD"),
95 	PINCTRL_PIN(57, "ESPI_IO_0"),
96 	PINCTRL_PIN(58, "ESPI_IO_1"),
97 	PINCTRL_PIN(59, "ESPI_IO_2"),
98 	PINCTRL_PIN(60, "ESPI_IO_3"),
99 	PINCTRL_PIN(61, "I2S1_SCLK"),
100 	PINCTRL_PIN(62, "ESPI_CSB"),
101 	PINCTRL_PIN(63, "ESPI_CLK"),
102 	PINCTRL_PIN(64, "ESPI_RESETB"),
103 	PINCTRL_PIN(65, "SD3_WP"),
104 	PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
105 };
106 
107 static const struct intel_padgroup ehl_community0_gpps[] = {
108 	EHL_GPP(0, 0, 25),	/* GPP_B */
109 	EHL_GPP(1, 26, 41),	/* GPP_T */
110 	EHL_GPP(2, 42, 66),	/* GPP_G */
111 };
112 
113 static const struct intel_community ehl_community0[] = {
114 	EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps),
115 };
116 
117 static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
118 	.uid = "0",
119 	.pins = ehl_community0_pins,
120 	.npins = ARRAY_SIZE(ehl_community0_pins),
121 	.communities = ehl_community0,
122 	.ncommunities = ARRAY_SIZE(ehl_community0),
123 };
124 
125 static const struct pinctrl_pin_desc ehl_community1_pins[] = {
126 	/* GPP_V */
127 	PINCTRL_PIN(0, "EMMC_CMD"),
128 	PINCTRL_PIN(1, "EMMC_DATA0"),
129 	PINCTRL_PIN(2, "EMMC_DATA1"),
130 	PINCTRL_PIN(3, "EMMC_DATA2"),
131 	PINCTRL_PIN(4, "EMMC_DATA3"),
132 	PINCTRL_PIN(5, "EMMC_DATA4"),
133 	PINCTRL_PIN(6, "EMMC_DATA5"),
134 	PINCTRL_PIN(7, "EMMC_DATA6"),
135 	PINCTRL_PIN(8, "EMMC_DATA7"),
136 	PINCTRL_PIN(9, "EMMC_RCLK"),
137 	PINCTRL_PIN(10, "EMMC_CLK"),
138 	PINCTRL_PIN(11, "EMMC_RESETB"),
139 	PINCTRL_PIN(12, "OSE_TGPIO0"),
140 	PINCTRL_PIN(13, "OSE_TGPIO1"),
141 	PINCTRL_PIN(14, "OSE_TGPIO2"),
142 	PINCTRL_PIN(15, "OSE_TGPIO3"),
143 	/* GPP_H */
144 	PINCTRL_PIN(16, "RGMII1_INT"),
145 	PINCTRL_PIN(17, "RGMII1_RESETB"),
146 	PINCTRL_PIN(18, "RGMII1_AUXTS"),
147 	PINCTRL_PIN(19, "RGMII1_PPS"),
148 	PINCTRL_PIN(20, "I2C2_SDA"),
149 	PINCTRL_PIN(21, "I2C2_SCL"),
150 	PINCTRL_PIN(22, "I2C3_SDA"),
151 	PINCTRL_PIN(23, "I2C3_SCL"),
152 	PINCTRL_PIN(24, "I2C4_SDA"),
153 	PINCTRL_PIN(25, "I2C4_SCL"),
154 	PINCTRL_PIN(26, "SRCCLKREQB_4"),
155 	PINCTRL_PIN(27, "SRCCLKREQB_5"),
156 	PINCTRL_PIN(28, "OSE_UART1_RXD"),
157 	PINCTRL_PIN(29, "OSE_UART1_TXD"),
158 	PINCTRL_PIN(30, "GPPC_H_14"),
159 	PINCTRL_PIN(31, "OSE_UART1_CTSB"),
160 	PINCTRL_PIN(32, "PCIE_LNK_DOWN"),
161 	PINCTRL_PIN(33, "SD_PWR_EN_B"),
162 	PINCTRL_PIN(34, "CPU_C10_GATEB"),
163 	PINCTRL_PIN(35, "GPPC_H_19"),
164 	PINCTRL_PIN(36, "OSE_PWM7"),
165 	PINCTRL_PIN(37, "OSE_HSUART1_DE"),
166 	PINCTRL_PIN(38, "OSE_HSUART1_RE"),
167 	PINCTRL_PIN(39, "OSE_HSUART1_EN"),
168 	/* GPP_D */
169 	PINCTRL_PIN(40, "OSE_QEPA_0"),
170 	PINCTRL_PIN(41, "OSE_QEPB_0"),
171 	PINCTRL_PIN(42, "OSE_QEPI_0"),
172 	PINCTRL_PIN(43, "OSE_PWM6"),
173 	PINCTRL_PIN(44, "OSE_PWM2"),
174 	PINCTRL_PIN(45, "SRCCLKREQB_0"),
175 	PINCTRL_PIN(46, "SRCCLKREQB_1"),
176 	PINCTRL_PIN(47, "SRCCLKREQB_2"),
177 	PINCTRL_PIN(48, "SRCCLKREQB_3"),
178 	PINCTRL_PIN(49, "OSE_SPI0_CSB"),
179 	PINCTRL_PIN(50, "OSE_SPI0_SCLK"),
180 	PINCTRL_PIN(51, "OSE_SPI0_MISO"),
181 	PINCTRL_PIN(52, "OSE_SPI0_MOSI"),
182 	PINCTRL_PIN(53, "OSE_QEPA_1"),
183 	PINCTRL_PIN(54, "OSE_QEPB_1"),
184 	PINCTRL_PIN(55, "OSE_PWM3"),
185 	PINCTRL_PIN(56, "OSE_QEPI_1"),
186 	PINCTRL_PIN(57, "OSE_PWM4"),
187 	PINCTRL_PIN(58, "OSE_PWM5"),
188 	PINCTRL_PIN(59, "I2S_MCLK1_OUT"),
189 	PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"),
190 	/* GPP_U */
191 	PINCTRL_PIN(61, "RGMII2_INT"),
192 	PINCTRL_PIN(62, "RGMII2_RESETB"),
193 	PINCTRL_PIN(63, "RGMII2_PPS"),
194 	PINCTRL_PIN(64, "RGMII2_AUXTS"),
195 	PINCTRL_PIN(65, "ISI_SPIM_CS"),
196 	PINCTRL_PIN(66, "ISI_SPIM_SCLK"),
197 	PINCTRL_PIN(67, "ISI_SPIM_MISO"),
198 	PINCTRL_PIN(68, "OSE_QEPA_3"),
199 	PINCTRL_PIN(69, "ISI_SPIS_CS"),
200 	PINCTRL_PIN(70, "ISI_SPIS_SCLK"),
201 	PINCTRL_PIN(71, "ISI_SPIS_MISO"),
202 	PINCTRL_PIN(72, "OSE_QEPB_3"),
203 	PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"),
204 	PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"),
205 	PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"),
206 	PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"),
207 	PINCTRL_PIN(77, "ISI_OKNOK_0"),
208 	PINCTRL_PIN(78, "ISI_OKNOK_1"),
209 	PINCTRL_PIN(79, "ISI_ALERT"),
210 	PINCTRL_PIN(80, "OSE_QEPI_3"),
211 	PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"),
212 	PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"),
213 	PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"),
214 	PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"),
215 	/* vGPIO */
216 	PINCTRL_PIN(85, "CNV_BTEN"),
217 	PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"),
218 	PINCTRL_PIN(87, "CNV_BT_IF_SELECT"),
219 	PINCTRL_PIN(88, "vCNV_BT_UART_TXD"),
220 	PINCTRL_PIN(89, "vCNV_BT_UART_RXD"),
221 	PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"),
222 	PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"),
223 	PINCTRL_PIN(92, "vCNV_MFUART1_TXD"),
224 	PINCTRL_PIN(93, "vCNV_MFUART1_RXD"),
225 	PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"),
226 	PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"),
227 	PINCTRL_PIN(96, "vUART0_TXD"),
228 	PINCTRL_PIN(97, "vUART0_RXD"),
229 	PINCTRL_PIN(98, "vUART0_CTS_B"),
230 	PINCTRL_PIN(99, "vUART0_RTS_B"),
231 	PINCTRL_PIN(100, "vOSE_UART0_TXD"),
232 	PINCTRL_PIN(101, "vOSE_UART0_RXD"),
233 	PINCTRL_PIN(102, "vOSE_UART0_CTS_B"),
234 	PINCTRL_PIN(103, "vOSE_UART0_RTS_B"),
235 	PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"),
236 	PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"),
237 	PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"),
238 	PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"),
239 	PINCTRL_PIN(108, "vI2S2_SCLK"),
240 	PINCTRL_PIN(109, "vI2S2_SFRM"),
241 	PINCTRL_PIN(110, "vI2S2_TXD"),
242 	PINCTRL_PIN(111, "vI2S2_RXD"),
243 	PINCTRL_PIN(112, "vSD3_CD_B"),
244 };
245 
246 static const struct intel_padgroup ehl_community1_gpps[] = {
247 	EHL_GPP(0, 0, 15),	/* GPP_V */
248 	EHL_GPP(1, 16, 39),	/* GPP_H */
249 	EHL_GPP(2, 40, 60),	/* GPP_D */
250 	EHL_GPP(3, 61, 84),	/* GPP_U */
251 	EHL_GPP(4, 85, 112),	/* vGPIO */
252 };
253 
254 static const struct intel_community ehl_community1[] = {
255 	EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps),
256 };
257 
258 static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
259 	.uid = "1",
260 	.pins = ehl_community1_pins,
261 	.npins = ARRAY_SIZE(ehl_community1_pins),
262 	.communities = ehl_community1,
263 	.ncommunities = ARRAY_SIZE(ehl_community1),
264 };
265 
266 static const struct pinctrl_pin_desc ehl_community3_pins[] = {
267 	/* CPU */
268 	PINCTRL_PIN(0, "HDACPU_SDI"),
269 	PINCTRL_PIN(1, "HDACPU_SDO"),
270 	PINCTRL_PIN(2, "HDACPU_BCLK"),
271 	PINCTRL_PIN(3, "PM_SYNC"),
272 	PINCTRL_PIN(4, "PECI"),
273 	PINCTRL_PIN(5, "CPUPWRGD"),
274 	PINCTRL_PIN(6, "THRMTRIPB"),
275 	PINCTRL_PIN(7, "PLTRST_CPUB"),
276 	PINCTRL_PIN(8, "PM_DOWN"),
277 	PINCTRL_PIN(9, "TRIGGER_IN"),
278 	PINCTRL_PIN(10, "TRIGGER_OUT"),
279 	PINCTRL_PIN(11, "UFS_RESETB"),
280 	PINCTRL_PIN(12, "CLKOUT_CPURTC"),
281 	PINCTRL_PIN(13, "VCCST_OVERRIDE"),
282 	PINCTRL_PIN(14, "C10_WAKE"),
283 	PINCTRL_PIN(15, "PROCHOTB"),
284 	PINCTRL_PIN(16, "CATERRB"),
285 	/* GPP_S */
286 	PINCTRL_PIN(17, "UFS_REF_CLK_0"),
287 	PINCTRL_PIN(18, "UFS_REF_CLK_1"),
288 	/* GPP_A */
289 	PINCTRL_PIN(19, "RGMII0_TXDATA_3"),
290 	PINCTRL_PIN(20, "RGMII0_TXDATA_2"),
291 	PINCTRL_PIN(21, "RGMII0_TXDATA_1"),
292 	PINCTRL_PIN(22, "RGMII0_TXDATA_0"),
293 	PINCTRL_PIN(23, "RGMII0_TXCLK"),
294 	PINCTRL_PIN(24, "RGMII0_TXCTL"),
295 	PINCTRL_PIN(25, "RGMII0_RXCLK"),
296 	PINCTRL_PIN(26, "RGMII0_RXDATA_3"),
297 	PINCTRL_PIN(27, "RGMII0_RXDATA_2"),
298 	PINCTRL_PIN(28, "RGMII0_RXDATA_1"),
299 	PINCTRL_PIN(29, "RGMII0_RXDATA_0"),
300 	PINCTRL_PIN(30, "RGMII1_TXDATA_3"),
301 	PINCTRL_PIN(31, "RGMII1_TXDATA_2"),
302 	PINCTRL_PIN(32, "RGMII1_TXDATA_1"),
303 	PINCTRL_PIN(33, "RGMII1_TXDATA_0"),
304 	PINCTRL_PIN(34, "RGMII1_TXCLK"),
305 	PINCTRL_PIN(35, "RGMII1_TXCTL"),
306 	PINCTRL_PIN(36, "RGMII1_RXCLK"),
307 	PINCTRL_PIN(37, "RGMII1_RXCTL"),
308 	PINCTRL_PIN(38, "RGMII1_RXDATA_3"),
309 	PINCTRL_PIN(39, "RGMII1_RXDATA_2"),
310 	PINCTRL_PIN(40, "RGMII1_RXDATA_1"),
311 	PINCTRL_PIN(41, "RGMII1_RXDATA_0"),
312 	PINCTRL_PIN(42, "RGMII0_RXCTL"),
313 	/* vGPIO_3 */
314 	PINCTRL_PIN(43, "ESPI_USB_OCB_0"),
315 	PINCTRL_PIN(44, "ESPI_USB_OCB_1"),
316 	PINCTRL_PIN(45, "ESPI_USB_OCB_2"),
317 	PINCTRL_PIN(46, "ESPI_USB_OCB_3"),
318 };
319 
320 static const struct intel_padgroup ehl_community3_gpps[] = {
321 	EHL_GPP(0, 0, 16),	/* CPU */
322 	EHL_GPP(1, 17, 18),	/* GPP_S */
323 	EHL_GPP(2, 19, 42),	/* GPP_A */
324 	EHL_GPP(3, 43, 46),	/* vGPIO_3 */
325 };
326 
327 static const struct intel_community ehl_community3[] = {
328 	EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps),
329 };
330 
331 static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
332 	.uid = "3",
333 	.pins = ehl_community3_pins,
334 	.npins = ARRAY_SIZE(ehl_community3_pins),
335 	.communities = ehl_community3,
336 	.ncommunities = ARRAY_SIZE(ehl_community3),
337 };
338 
339 static const struct pinctrl_pin_desc ehl_community4_pins[] = {
340 	/* GPP_C */
341 	PINCTRL_PIN(0, "SMBCLK"),
342 	PINCTRL_PIN(1, "SMBDATA"),
343 	PINCTRL_PIN(2, "OSE_PWM0"),
344 	PINCTRL_PIN(3, "RGMII0_MDC"),
345 	PINCTRL_PIN(4, "RGMII0_MDIO"),
346 	PINCTRL_PIN(5, "OSE_PWM1"),
347 	PINCTRL_PIN(6, "RGMII1_MDC"),
348 	PINCTRL_PIN(7, "RGMII1_MDIO"),
349 	PINCTRL_PIN(8, "OSE_TGPIO4"),
350 	PINCTRL_PIN(9, "OSE_HSUART0_EN"),
351 	PINCTRL_PIN(10, "OSE_TGPIO5"),
352 	PINCTRL_PIN(11, "OSE_HSUART0_RE"),
353 	PINCTRL_PIN(12, "OSE_UART0_RXD"),
354 	PINCTRL_PIN(13, "OSE_UART0_TXD"),
355 	PINCTRL_PIN(14, "OSE_UART0_RTSB"),
356 	PINCTRL_PIN(15, "OSE_UART0_CTSB"),
357 	PINCTRL_PIN(16, "RGMII2_MDIO"),
358 	PINCTRL_PIN(17, "RGMII2_MDC"),
359 	PINCTRL_PIN(18, "OSE_I2C4_SDAT"),
360 	PINCTRL_PIN(19, "OSE_I2C4_SCLK"),
361 	PINCTRL_PIN(20, "OSE_UART4_RXD"),
362 	PINCTRL_PIN(21, "OSE_UART4_TXD"),
363 	PINCTRL_PIN(22, "OSE_UART4_RTSB"),
364 	PINCTRL_PIN(23, "OSE_UART4_CTSB"),
365 	/* GPP_F */
366 	PINCTRL_PIN(24, "CNV_BRI_DT"),
367 	PINCTRL_PIN(25, "CNV_BRI_RSP"),
368 	PINCTRL_PIN(26, "CNV_RGI_DT"),
369 	PINCTRL_PIN(27, "CNV_RGI_RSP"),
370 	PINCTRL_PIN(28, "CNV_RF_RESET_B"),
371 	PINCTRL_PIN(29, "EMMC_HIP_MON"),
372 	PINCTRL_PIN(30, "CNV_PA_BLANKING"),
373 	PINCTRL_PIN(31, "OSE_I2S1_SCLK"),
374 	PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
375 	PINCTRL_PIN(33, "BOOTMPC"),
376 	PINCTRL_PIN(34, "OSE_I2S1_SFRM"),
377 	PINCTRL_PIN(35, "GPPC_F_11"),
378 	PINCTRL_PIN(36, "GSXDOUT"),
379 	PINCTRL_PIN(37, "GSXSLOAD"),
380 	PINCTRL_PIN(38, "GSXDIN"),
381 	PINCTRL_PIN(39, "GSXSRESETB"),
382 	PINCTRL_PIN(40, "GSXCLK"),
383 	PINCTRL_PIN(41, "GPPC_F_17"),
384 	PINCTRL_PIN(42, "OSE_I2S1_TXD"),
385 	PINCTRL_PIN(43, "OSE_I2S1_RXD"),
386 	PINCTRL_PIN(44, "EXT_PWR_GATEB"),
387 	PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
388 	PINCTRL_PIN(46, "VNN_CTRL"),
389 	PINCTRL_PIN(47, "V1P05_CTRL"),
390 	PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
391 	/* HVCMOS */
392 	PINCTRL_PIN(49, "L_BKLTEN"),
393 	PINCTRL_PIN(50, "L_BKLTCTL"),
394 	PINCTRL_PIN(51, "L_VDDEN"),
395 	PINCTRL_PIN(52, "SYS_PWROK"),
396 	PINCTRL_PIN(53, "SYS_RESETB"),
397 	PINCTRL_PIN(54, "MLK_RSTB"),
398 	/* GPP_E */
399 	PINCTRL_PIN(55, "SATA_LEDB"),
400 	PINCTRL_PIN(56, "GPPC_E_1"),
401 	PINCTRL_PIN(57, "GPPC_E_2"),
402 	PINCTRL_PIN(58, "DDSP_HPD_B"),
403 	PINCTRL_PIN(59, "SATA_DEVSLP_0"),
404 	PINCTRL_PIN(60, "DDPB_CTRLDATA"),
405 	PINCTRL_PIN(61, "GPPC_E_6"),
406 	PINCTRL_PIN(62, "DDPB_CTRLCLK"),
407 	PINCTRL_PIN(63, "GPPC_E_8"),
408 	PINCTRL_PIN(64, "USB2_OCB_0"),
409 	PINCTRL_PIN(65, "GPPC_E_10"),
410 	PINCTRL_PIN(66, "GPPC_E_11"),
411 	PINCTRL_PIN(67, "GPPC_E_12"),
412 	PINCTRL_PIN(68, "GPPC_E_13"),
413 	PINCTRL_PIN(69, "DDSP_HPD_A"),
414 	PINCTRL_PIN(70, "OSE_I2S0_RXD"),
415 	PINCTRL_PIN(71, "OSE_I2S0_TXD"),
416 	PINCTRL_PIN(72, "DDSP_HPD_C"),
417 	PINCTRL_PIN(73, "DDPA_CTRLDATA"),
418 	PINCTRL_PIN(74, "DDPA_CTRLCLK"),
419 	PINCTRL_PIN(75, "OSE_I2S0_SCLK"),
420 	PINCTRL_PIN(76, "OSE_I2S0_SFRM"),
421 	PINCTRL_PIN(77, "DDPC_CTRLDATA"),
422 	PINCTRL_PIN(78, "DDPC_CTRLCLK"),
423 	PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
424 };
425 
426 static const struct intel_padgroup ehl_community4_gpps[] = {
427 	EHL_GPP(0, 0, 23),	/* GPP_C */
428 	EHL_GPP(1, 24, 48),	/* GPP_F */
429 	EHL_GPP(2, 49, 54),	/* HVCMOS */
430 	EHL_GPP(3, 55, 79),	/* GPP_E */
431 };
432 
433 static const struct intel_community ehl_community4[] = {
434 	EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps),
435 };
436 
437 static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
438 	.uid = "4",
439 	.pins = ehl_community4_pins,
440 	.npins = ARRAY_SIZE(ehl_community4_pins),
441 	.communities = ehl_community4,
442 	.ncommunities = ARRAY_SIZE(ehl_community4),
443 };
444 
445 static const struct pinctrl_pin_desc ehl_community5_pins[] = {
446 	/* GPP_R */
447 	PINCTRL_PIN(0, "HDA_BCLK"),
448 	PINCTRL_PIN(1, "HDA_SYNC"),
449 	PINCTRL_PIN(2, "HDA_SDO"),
450 	PINCTRL_PIN(3, "HDA_SDI_0"),
451 	PINCTRL_PIN(4, "HDA_RSTB"),
452 	PINCTRL_PIN(5, "HDA_SDI_1"),
453 	PINCTRL_PIN(6, "GPP_R_6"),
454 	PINCTRL_PIN(7, "GPP_R_7"),
455 };
456 
457 static const struct intel_padgroup ehl_community5_gpps[] = {
458 	EHL_GPP(0, 0, 7),	/* GPP_R */
459 };
460 
461 static const struct intel_community ehl_community5[] = {
462 	EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps),
463 };
464 
465 static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
466 	.uid = "5",
467 	.pins = ehl_community5_pins,
468 	.npins = ARRAY_SIZE(ehl_community5_pins),
469 	.communities = ehl_community5,
470 	.ncommunities = ARRAY_SIZE(ehl_community5),
471 };
472 
473 static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
474 	&ehl_community0_soc_data,
475 	&ehl_community1_soc_data,
476 	&ehl_community3_soc_data,
477 	&ehl_community4_soc_data,
478 	&ehl_community5_soc_data,
479 	NULL
480 };
481 
482 static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
483 	{ "INTC1020", (kernel_ulong_t)ehl_soc_data_array },
484 	{ }
485 };
486 MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
487 
488 static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
489 
490 static struct platform_driver ehl_pinctrl_driver = {
491 	.probe = intel_pinctrl_probe_by_uid,
492 	.driver = {
493 		.name = "elkhartlake-pinctrl",
494 		.acpi_match_table = ehl_pinctrl_acpi_match,
495 		.pm = &ehl_pinctrl_pm_ops,
496 	},
497 };
498 
499 module_platform_driver(ehl_pinctrl_driver);
500 
501 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
502 MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver");
503 MODULE_LICENSE("GPL v2");
504