1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13 #include <linux/dmi.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/gpio.h> 19 #include <linux/gpio/driver.h> 20 #include <linux/acpi.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/platform_device.h> 26 27 #define CHV_INTSTAT 0x300 28 #define CHV_INTMASK 0x380 29 30 #define FAMILY_PAD_REGS_OFF 0x4400 31 #define FAMILY_PAD_REGS_SIZE 0x400 32 #define MAX_FAMILY_PAD_GPIO_NO 15 33 #define GPIO_REGS_SIZE 8 34 35 #define CHV_PADCTRL0 0x000 36 #define CHV_PADCTRL0_INTSEL_SHIFT 28 37 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 38 #define CHV_PADCTRL0_TERM_UP BIT(23) 39 #define CHV_PADCTRL0_TERM_SHIFT 20 40 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 41 #define CHV_PADCTRL0_TERM_20K 1 42 #define CHV_PADCTRL0_TERM_5K 2 43 #define CHV_PADCTRL0_TERM_1K 4 44 #define CHV_PADCTRL0_PMODE_SHIFT 16 45 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 46 #define CHV_PADCTRL0_GPIOEN BIT(15) 47 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 48 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 49 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 50 #define CHV_PADCTRL0_GPIOCFG_GPO 1 51 #define CHV_PADCTRL0_GPIOCFG_GPI 2 52 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 53 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 54 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 55 56 #define CHV_PADCTRL1 0x004 57 #define CHV_PADCTRL1_CFGLOCK BIT(31) 58 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 59 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 60 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 61 #define CHV_PADCTRL1_ODEN BIT(3) 62 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 63 #define CHV_PADCTRL1_INTWAKECFG_MASK 7 64 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 65 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 66 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 67 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 68 69 /** 70 * struct chv_alternate_function - A per group or per pin alternate function 71 * @pin: Pin number (only used in per pin configs) 72 * @mode: Mode the pin should be set in 73 * @invert_oe: Invert OE for this pin 74 */ 75 struct chv_alternate_function { 76 unsigned pin; 77 u8 mode; 78 bool invert_oe; 79 }; 80 81 /** 82 * struct chv_pincgroup - describes a CHV pin group 83 * @name: Name of the group 84 * @pins: An array of pins in this group 85 * @npins: Number of pins in this group 86 * @altfunc: Alternate function applied to all pins in this group 87 * @overrides: Alternate function override per pin or %NULL if not used 88 * @noverrides: Number of per pin alternate function overrides if 89 * @overrides != NULL. 90 */ 91 struct chv_pingroup { 92 const char *name; 93 const unsigned *pins; 94 size_t npins; 95 struct chv_alternate_function altfunc; 96 const struct chv_alternate_function *overrides; 97 size_t noverrides; 98 }; 99 100 /** 101 * struct chv_function - A CHV pinmux function 102 * @name: Name of the function 103 * @groups: An array of groups for this function 104 * @ngroups: Number of groups in @groups 105 */ 106 struct chv_function { 107 const char *name; 108 const char * const *groups; 109 size_t ngroups; 110 }; 111 112 /** 113 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 114 * @base: Start pin number 115 * @npins: Number of pins in this range 116 */ 117 struct chv_gpio_pinrange { 118 unsigned base; 119 unsigned npins; 120 }; 121 122 /** 123 * struct chv_community - A community specific configuration 124 * @uid: ACPI _UID used to match the community 125 * @pins: All pins in this community 126 * @npins: Number of pins 127 * @groups: All groups in this community 128 * @ngroups: Number of groups 129 * @functions: All functions in this community 130 * @nfunctions: Number of functions 131 * @gpio_ranges: An array of GPIO ranges in this community 132 * @ngpio_ranges: Number of GPIO ranges 133 * @nirqs: Total number of IRQs this community can generate 134 */ 135 struct chv_community { 136 const char *uid; 137 const struct pinctrl_pin_desc *pins; 138 size_t npins; 139 const struct chv_pingroup *groups; 140 size_t ngroups; 141 const struct chv_function *functions; 142 size_t nfunctions; 143 const struct chv_gpio_pinrange *gpio_ranges; 144 size_t ngpio_ranges; 145 size_t nirqs; 146 acpi_adr_space_type acpi_space_id; 147 }; 148 149 struct chv_pin_context { 150 u32 padctrl0; 151 u32 padctrl1; 152 }; 153 154 /** 155 * struct chv_pinctrl - CHV pinctrl private structure 156 * @dev: Pointer to the parent device 157 * @pctldesc: Pin controller description 158 * @pctldev: Pointer to the pin controller device 159 * @chip: GPIO chip in this pin controller 160 * @regs: MMIO registers 161 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 162 * offset (in GPIO number space) 163 * @community: Community this pinctrl instance represents 164 * 165 * The first group in @groups is expected to contain all pins that can be 166 * used as GPIOs. 167 */ 168 struct chv_pinctrl { 169 struct device *dev; 170 struct pinctrl_desc pctldesc; 171 struct pinctrl_dev *pctldev; 172 struct gpio_chip chip; 173 void __iomem *regs; 174 unsigned intr_lines[16]; 175 const struct chv_community *community; 176 u32 saved_intmask; 177 struct chv_pin_context *saved_pin_context; 178 }; 179 180 #define ALTERNATE_FUNCTION(p, m, i) \ 181 { \ 182 .pin = (p), \ 183 .mode = (m), \ 184 .invert_oe = (i), \ 185 } 186 187 #define PIN_GROUP(n, p, m, i) \ 188 { \ 189 .name = (n), \ 190 .pins = (p), \ 191 .npins = ARRAY_SIZE((p)), \ 192 .altfunc.mode = (m), \ 193 .altfunc.invert_oe = (i), \ 194 } 195 196 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 197 { \ 198 .name = (n), \ 199 .pins = (p), \ 200 .npins = ARRAY_SIZE((p)), \ 201 .altfunc.mode = (m), \ 202 .altfunc.invert_oe = (i), \ 203 .overrides = (o), \ 204 .noverrides = ARRAY_SIZE((o)), \ 205 } 206 207 #define FUNCTION(n, g) \ 208 { \ 209 .name = (n), \ 210 .groups = (g), \ 211 .ngroups = ARRAY_SIZE((g)), \ 212 } 213 214 #define GPIO_PINRANGE(start, end) \ 215 { \ 216 .base = (start), \ 217 .npins = (end) - (start) + 1, \ 218 } 219 220 static const struct pinctrl_pin_desc southwest_pins[] = { 221 PINCTRL_PIN(0, "FST_SPI_D2"), 222 PINCTRL_PIN(1, "FST_SPI_D0"), 223 PINCTRL_PIN(2, "FST_SPI_CLK"), 224 PINCTRL_PIN(3, "FST_SPI_D3"), 225 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 226 PINCTRL_PIN(5, "FST_SPI_D1"), 227 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 228 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 229 230 PINCTRL_PIN(15, "UART1_RTS_B"), 231 PINCTRL_PIN(16, "UART1_RXD"), 232 PINCTRL_PIN(17, "UART2_RXD"), 233 PINCTRL_PIN(18, "UART1_CTS_B"), 234 PINCTRL_PIN(19, "UART2_RTS_B"), 235 PINCTRL_PIN(20, "UART1_TXD"), 236 PINCTRL_PIN(21, "UART2_TXD"), 237 PINCTRL_PIN(22, "UART2_CTS_B"), 238 239 PINCTRL_PIN(30, "MF_HDA_CLK"), 240 PINCTRL_PIN(31, "MF_HDA_RSTB"), 241 PINCTRL_PIN(32, "MF_HDA_SDIO"), 242 PINCTRL_PIN(33, "MF_HDA_SDO"), 243 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 244 PINCTRL_PIN(35, "MF_HDA_SYNC"), 245 PINCTRL_PIN(36, "MF_HDA_SDI1"), 246 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 247 248 PINCTRL_PIN(45, "I2C5_SDA"), 249 PINCTRL_PIN(46, "I2C4_SDA"), 250 PINCTRL_PIN(47, "I2C6_SDA"), 251 PINCTRL_PIN(48, "I2C5_SCL"), 252 PINCTRL_PIN(49, "I2C_NFC_SDA"), 253 PINCTRL_PIN(50, "I2C4_SCL"), 254 PINCTRL_PIN(51, "I2C6_SCL"), 255 PINCTRL_PIN(52, "I2C_NFC_SCL"), 256 257 PINCTRL_PIN(60, "I2C1_SDA"), 258 PINCTRL_PIN(61, "I2C0_SDA"), 259 PINCTRL_PIN(62, "I2C2_SDA"), 260 PINCTRL_PIN(63, "I2C1_SCL"), 261 PINCTRL_PIN(64, "I2C3_SDA"), 262 PINCTRL_PIN(65, "I2C0_SCL"), 263 PINCTRL_PIN(66, "I2C2_SCL"), 264 PINCTRL_PIN(67, "I2C3_SCL"), 265 266 PINCTRL_PIN(75, "SATA_GP0"), 267 PINCTRL_PIN(76, "SATA_GP1"), 268 PINCTRL_PIN(77, "SATA_LEDN"), 269 PINCTRL_PIN(78, "SATA_GP2"), 270 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 271 PINCTRL_PIN(80, "SATA_GP3"), 272 PINCTRL_PIN(81, "MF_SMB_CLK"), 273 PINCTRL_PIN(82, "MF_SMB_DATA"), 274 275 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 276 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 277 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 278 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 279 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 280 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 281 PINCTRL_PIN(96, "GP_SSP_2_FS"), 282 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 283 }; 284 285 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 286 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 287 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 288 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 289 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 290 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 291 static const unsigned southwest_lpe_pins[] = { 292 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 293 }; 294 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 295 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 296 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 297 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 298 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 299 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 300 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 301 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 302 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 303 304 /* LPE I2S TXD pins need to have invert_oe set */ 305 static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 306 ALTERNATE_FUNCTION(30, 1, true), 307 ALTERNATE_FUNCTION(34, 1, true), 308 ALTERNATE_FUNCTION(97, 1, true), 309 }; 310 311 /* 312 * Two spi3 chipselects are available in different mode than the main spi3 313 * functionality, which is using mode 1. 314 */ 315 static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 316 ALTERNATE_FUNCTION(76, 3, false), 317 ALTERNATE_FUNCTION(80, 3, false), 318 }; 319 320 static const struct chv_pingroup southwest_groups[] = { 321 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 322 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 323 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 324 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 325 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 326 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 327 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 328 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 329 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 330 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 331 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 332 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 333 334 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 335 southwest_lpe_altfuncs), 336 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 337 southwest_spi3_altfuncs), 338 }; 339 340 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 341 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 342 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 343 static const char * const southwest_hda_groups[] = { "hda_grp" }; 344 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 345 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 346 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 347 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 348 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 349 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 350 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 351 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 352 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 353 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 354 355 /* 356 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 357 * enabled only as GPIOs. 358 */ 359 static const struct chv_function southwest_functions[] = { 360 FUNCTION("uart0", southwest_uart0_groups), 361 FUNCTION("uart1", southwest_uart1_groups), 362 FUNCTION("uart2", southwest_uart2_groups), 363 FUNCTION("hda", southwest_hda_groups), 364 FUNCTION("lpe", southwest_lpe_groups), 365 FUNCTION("i2c0", southwest_i2c0_groups), 366 FUNCTION("i2c1", southwest_i2c1_groups), 367 FUNCTION("i2c2", southwest_i2c2_groups), 368 FUNCTION("i2c3", southwest_i2c3_groups), 369 FUNCTION("i2c4", southwest_i2c4_groups), 370 FUNCTION("i2c5", southwest_i2c5_groups), 371 FUNCTION("i2c6", southwest_i2c6_groups), 372 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 373 FUNCTION("spi3", southwest_spi3_groups), 374 }; 375 376 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 377 GPIO_PINRANGE(0, 7), 378 GPIO_PINRANGE(15, 22), 379 GPIO_PINRANGE(30, 37), 380 GPIO_PINRANGE(45, 52), 381 GPIO_PINRANGE(60, 67), 382 GPIO_PINRANGE(75, 82), 383 GPIO_PINRANGE(90, 97), 384 }; 385 386 static const struct chv_community southwest_community = { 387 .uid = "1", 388 .pins = southwest_pins, 389 .npins = ARRAY_SIZE(southwest_pins), 390 .groups = southwest_groups, 391 .ngroups = ARRAY_SIZE(southwest_groups), 392 .functions = southwest_functions, 393 .nfunctions = ARRAY_SIZE(southwest_functions), 394 .gpio_ranges = southwest_gpio_ranges, 395 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 396 /* 397 * Southwest community can benerate GPIO interrupts only for the 398 * first 8 interrupts. The upper half (8-15) can only be used to 399 * trigger GPEs. 400 */ 401 .nirqs = 8, 402 .acpi_space_id = 0x91, 403 }; 404 405 static const struct pinctrl_pin_desc north_pins[] = { 406 PINCTRL_PIN(0, "GPIO_DFX_0"), 407 PINCTRL_PIN(1, "GPIO_DFX_3"), 408 PINCTRL_PIN(2, "GPIO_DFX_7"), 409 PINCTRL_PIN(3, "GPIO_DFX_1"), 410 PINCTRL_PIN(4, "GPIO_DFX_5"), 411 PINCTRL_PIN(5, "GPIO_DFX_4"), 412 PINCTRL_PIN(6, "GPIO_DFX_8"), 413 PINCTRL_PIN(7, "GPIO_DFX_2"), 414 PINCTRL_PIN(8, "GPIO_DFX_6"), 415 416 PINCTRL_PIN(15, "GPIO_SUS0"), 417 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 418 PINCTRL_PIN(17, "GPIO_SUS3"), 419 PINCTRL_PIN(18, "GPIO_SUS7"), 420 PINCTRL_PIN(19, "GPIO_SUS1"), 421 PINCTRL_PIN(20, "GPIO_SUS5"), 422 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 423 PINCTRL_PIN(22, "GPIO_SUS4"), 424 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 425 PINCTRL_PIN(24, "GPIO_SUS2"), 426 PINCTRL_PIN(25, "GPIO_SUS6"), 427 PINCTRL_PIN(26, "CX_PREQ_B"), 428 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 429 430 PINCTRL_PIN(30, "TRST_B"), 431 PINCTRL_PIN(31, "TCK"), 432 PINCTRL_PIN(32, "PROCHOT_B"), 433 PINCTRL_PIN(33, "SVIDO_DATA"), 434 PINCTRL_PIN(34, "TMS"), 435 PINCTRL_PIN(35, "CX_PRDY_B_2"), 436 PINCTRL_PIN(36, "TDO_2"), 437 PINCTRL_PIN(37, "CX_PRDY_B"), 438 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 439 PINCTRL_PIN(39, "TDO"), 440 PINCTRL_PIN(40, "SVIDO_CLK"), 441 PINCTRL_PIN(41, "TDI"), 442 443 PINCTRL_PIN(45, "GP_CAMERASB_05"), 444 PINCTRL_PIN(46, "GP_CAMERASB_02"), 445 PINCTRL_PIN(47, "GP_CAMERASB_08"), 446 PINCTRL_PIN(48, "GP_CAMERASB_00"), 447 PINCTRL_PIN(49, "GP_CAMERASB_06"), 448 PINCTRL_PIN(50, "GP_CAMERASB_10"), 449 PINCTRL_PIN(51, "GP_CAMERASB_03"), 450 PINCTRL_PIN(52, "GP_CAMERASB_09"), 451 PINCTRL_PIN(53, "GP_CAMERASB_01"), 452 PINCTRL_PIN(54, "GP_CAMERASB_07"), 453 PINCTRL_PIN(55, "GP_CAMERASB_11"), 454 PINCTRL_PIN(56, "GP_CAMERASB_04"), 455 456 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 457 PINCTRL_PIN(61, "HV_DDI0_HPD"), 458 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 459 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 460 PINCTRL_PIN(64, "HV_DDI1_HPD"), 461 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 462 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 463 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 464 PINCTRL_PIN(68, "HV_DDI2_HPD"), 465 PINCTRL_PIN(69, "PANEL1_VDDEN"), 466 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 467 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 468 PINCTRL_PIN(72, "PANEL0_VDDEN"), 469 }; 470 471 static const struct chv_gpio_pinrange north_gpio_ranges[] = { 472 GPIO_PINRANGE(0, 8), 473 GPIO_PINRANGE(15, 27), 474 GPIO_PINRANGE(30, 41), 475 GPIO_PINRANGE(45, 56), 476 GPIO_PINRANGE(60, 72), 477 }; 478 479 static const struct chv_community north_community = { 480 .uid = "2", 481 .pins = north_pins, 482 .npins = ARRAY_SIZE(north_pins), 483 .gpio_ranges = north_gpio_ranges, 484 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 485 /* 486 * North community can generate GPIO interrupts only for the first 487 * 8 interrupts. The upper half (8-15) can only be used to trigger 488 * GPEs. 489 */ 490 .nirqs = 8, 491 .acpi_space_id = 0x92, 492 }; 493 494 static const struct pinctrl_pin_desc east_pins[] = { 495 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 496 PINCTRL_PIN(1, "PMU_BATLOW_B"), 497 PINCTRL_PIN(2, "SUS_STAT_B"), 498 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 499 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 500 PINCTRL_PIN(5, "PMU_PLTRST_B"), 501 PINCTRL_PIN(6, "PMU_SUSCLK"), 502 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 503 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 504 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 505 PINCTRL_PIN(10, "PMU_WAKE_B"), 506 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 507 508 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 509 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 510 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 511 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 512 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 513 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 514 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 515 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 516 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 517 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 518 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 519 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 520 }; 521 522 static const struct chv_gpio_pinrange east_gpio_ranges[] = { 523 GPIO_PINRANGE(0, 11), 524 GPIO_PINRANGE(15, 26), 525 }; 526 527 static const struct chv_community east_community = { 528 .uid = "3", 529 .pins = east_pins, 530 .npins = ARRAY_SIZE(east_pins), 531 .gpio_ranges = east_gpio_ranges, 532 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 533 .nirqs = 16, 534 .acpi_space_id = 0x93, 535 }; 536 537 static const struct pinctrl_pin_desc southeast_pins[] = { 538 PINCTRL_PIN(0, "MF_PLT_CLK0"), 539 PINCTRL_PIN(1, "PWM1"), 540 PINCTRL_PIN(2, "MF_PLT_CLK1"), 541 PINCTRL_PIN(3, "MF_PLT_CLK4"), 542 PINCTRL_PIN(4, "MF_PLT_CLK3"), 543 PINCTRL_PIN(5, "PWM0"), 544 PINCTRL_PIN(6, "MF_PLT_CLK5"), 545 PINCTRL_PIN(7, "MF_PLT_CLK2"), 546 547 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 548 PINCTRL_PIN(16, "SDMMC1_CLK"), 549 PINCTRL_PIN(17, "SDMMC1_D0"), 550 PINCTRL_PIN(18, "SDMMC2_D1"), 551 PINCTRL_PIN(19, "SDMMC2_CLK"), 552 PINCTRL_PIN(20, "SDMMC1_D2"), 553 PINCTRL_PIN(21, "SDMMC2_D2"), 554 PINCTRL_PIN(22, "SDMMC2_CMD"), 555 PINCTRL_PIN(23, "SDMMC1_CMD"), 556 PINCTRL_PIN(24, "SDMMC1_D1"), 557 PINCTRL_PIN(25, "SDMMC2_D0"), 558 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 559 560 PINCTRL_PIN(30, "SDMMC3_D1"), 561 PINCTRL_PIN(31, "SDMMC3_CLK"), 562 PINCTRL_PIN(32, "SDMMC3_D3"), 563 PINCTRL_PIN(33, "SDMMC3_D2"), 564 PINCTRL_PIN(34, "SDMMC3_CMD"), 565 PINCTRL_PIN(35, "SDMMC3_D0"), 566 567 PINCTRL_PIN(45, "MF_LPC_AD2"), 568 PINCTRL_PIN(46, "LPC_CLKRUNB"), 569 PINCTRL_PIN(47, "MF_LPC_AD0"), 570 PINCTRL_PIN(48, "LPC_FRAMEB"), 571 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 572 PINCTRL_PIN(50, "MF_LPC_AD3"), 573 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 574 PINCTRL_PIN(52, "MF_LPC_AD1"), 575 576 PINCTRL_PIN(60, "SPI1_MISO"), 577 PINCTRL_PIN(61, "SPI1_CSO_B"), 578 PINCTRL_PIN(62, "SPI1_CLK"), 579 PINCTRL_PIN(63, "MMC1_D6"), 580 PINCTRL_PIN(64, "SPI1_MOSI"), 581 PINCTRL_PIN(65, "MMC1_D5"), 582 PINCTRL_PIN(66, "SPI1_CS1_B"), 583 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 584 PINCTRL_PIN(68, "MMC1_D7"), 585 PINCTRL_PIN(69, "MMC1_RCLK"), 586 587 PINCTRL_PIN(75, "USB_OC1_B"), 588 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 589 PINCTRL_PIN(77, "GPIO_ALERT"), 590 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 591 PINCTRL_PIN(79, "ILB_SERIRQ"), 592 PINCTRL_PIN(80, "USB_OC0_B"), 593 PINCTRL_PIN(81, "SDMMC3_CD_B"), 594 PINCTRL_PIN(82, "SPKR"), 595 PINCTRL_PIN(83, "SUSPWRDNACK"), 596 PINCTRL_PIN(84, "SPARE_PIN"), 597 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 598 }; 599 600 static const unsigned southeast_pwm0_pins[] = { 5 }; 601 static const unsigned southeast_pwm1_pins[] = { 1 }; 602 static const unsigned southeast_sdmmc1_pins[] = { 603 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 604 }; 605 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 606 static const unsigned southeast_sdmmc3_pins[] = { 607 30, 31, 32, 33, 34, 35, 78, 81, 85, 608 }; 609 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 610 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 611 612 static const struct chv_pingroup southeast_groups[] = { 613 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 614 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 615 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 616 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 617 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 618 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 619 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 620 }; 621 622 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 623 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 624 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 625 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 626 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 627 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 628 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 629 630 static const struct chv_function southeast_functions[] = { 631 FUNCTION("pwm0", southeast_pwm0_groups), 632 FUNCTION("pwm1", southeast_pwm1_groups), 633 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 634 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 635 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 636 FUNCTION("spi1", southeast_spi1_groups), 637 FUNCTION("spi2", southeast_spi2_groups), 638 }; 639 640 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 641 GPIO_PINRANGE(0, 7), 642 GPIO_PINRANGE(15, 26), 643 GPIO_PINRANGE(30, 35), 644 GPIO_PINRANGE(45, 52), 645 GPIO_PINRANGE(60, 69), 646 GPIO_PINRANGE(75, 85), 647 }; 648 649 static const struct chv_community southeast_community = { 650 .uid = "4", 651 .pins = southeast_pins, 652 .npins = ARRAY_SIZE(southeast_pins), 653 .groups = southeast_groups, 654 .ngroups = ARRAY_SIZE(southeast_groups), 655 .functions = southeast_functions, 656 .nfunctions = ARRAY_SIZE(southeast_functions), 657 .gpio_ranges = southeast_gpio_ranges, 658 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 659 .nirqs = 16, 660 .acpi_space_id = 0x94, 661 }; 662 663 static const struct chv_community *chv_communities[] = { 664 &southwest_community, 665 &north_community, 666 &east_community, 667 &southeast_community, 668 }; 669 670 /* 671 * Lock to serialize register accesses 672 * 673 * Due to a silicon issue, a shared lock must be used to prevent 674 * concurrent accesses across the 4 GPIO controllers. 675 * 676 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 677 * errata #CHT34, for further information. 678 */ 679 static DEFINE_RAW_SPINLOCK(chv_lock); 680 681 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 682 unsigned reg) 683 { 684 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 685 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 686 687 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 688 GPIO_REGS_SIZE * pad_no; 689 690 return pctrl->regs + offset + reg; 691 } 692 693 static void chv_writel(u32 value, void __iomem *reg) 694 { 695 writel(value, reg); 696 /* simple readback to confirm the bus transferring done */ 697 readl(reg); 698 } 699 700 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 701 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 702 { 703 void __iomem *reg; 704 705 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 706 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 707 } 708 709 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 710 { 711 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 712 713 return pctrl->community->ngroups; 714 } 715 716 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 717 unsigned group) 718 { 719 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 720 721 return pctrl->community->groups[group].name; 722 } 723 724 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 725 const unsigned **pins, unsigned *npins) 726 { 727 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 728 729 *pins = pctrl->community->groups[group].pins; 730 *npins = pctrl->community->groups[group].npins; 731 return 0; 732 } 733 734 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 735 unsigned offset) 736 { 737 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 738 unsigned long flags; 739 u32 ctrl0, ctrl1; 740 bool locked; 741 742 raw_spin_lock_irqsave(&chv_lock, flags); 743 744 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 745 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 746 locked = chv_pad_locked(pctrl, offset); 747 748 raw_spin_unlock_irqrestore(&chv_lock, flags); 749 750 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 751 seq_puts(s, "GPIO "); 752 } else { 753 u32 mode; 754 755 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 756 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 757 758 seq_printf(s, "mode %d ", mode); 759 } 760 761 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 762 763 if (locked) 764 seq_puts(s, " [LOCKED]"); 765 } 766 767 static const struct pinctrl_ops chv_pinctrl_ops = { 768 .get_groups_count = chv_get_groups_count, 769 .get_group_name = chv_get_group_name, 770 .get_group_pins = chv_get_group_pins, 771 .pin_dbg_show = chv_pin_dbg_show, 772 }; 773 774 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 775 { 776 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 777 778 return pctrl->community->nfunctions; 779 } 780 781 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 782 unsigned function) 783 { 784 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 785 786 return pctrl->community->functions[function].name; 787 } 788 789 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 790 unsigned function, 791 const char * const **groups, 792 unsigned * const ngroups) 793 { 794 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 795 796 *groups = pctrl->community->functions[function].groups; 797 *ngroups = pctrl->community->functions[function].ngroups; 798 return 0; 799 } 800 801 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 802 unsigned group) 803 { 804 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 805 const struct chv_pingroup *grp; 806 unsigned long flags; 807 int i; 808 809 grp = &pctrl->community->groups[group]; 810 811 raw_spin_lock_irqsave(&chv_lock, flags); 812 813 /* Check first that the pad is not locked */ 814 for (i = 0; i < grp->npins; i++) { 815 if (chv_pad_locked(pctrl, grp->pins[i])) { 816 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 817 grp->pins[i]); 818 raw_spin_unlock_irqrestore(&chv_lock, flags); 819 return -EBUSY; 820 } 821 } 822 823 for (i = 0; i < grp->npins; i++) { 824 const struct chv_alternate_function *altfunc = &grp->altfunc; 825 int pin = grp->pins[i]; 826 void __iomem *reg; 827 u32 value; 828 829 /* Check if there is pin-specific config */ 830 if (grp->overrides) { 831 int j; 832 833 for (j = 0; j < grp->noverrides; j++) { 834 if (grp->overrides[j].pin == pin) { 835 altfunc = &grp->overrides[j]; 836 break; 837 } 838 } 839 } 840 841 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 842 value = readl(reg); 843 /* Disable GPIO mode */ 844 value &= ~CHV_PADCTRL0_GPIOEN; 845 /* Set to desired mode */ 846 value &= ~CHV_PADCTRL0_PMODE_MASK; 847 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 848 chv_writel(value, reg); 849 850 /* Update for invert_oe */ 851 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 852 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 853 if (altfunc->invert_oe) 854 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 855 chv_writel(value, reg); 856 857 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 858 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 859 } 860 861 raw_spin_unlock_irqrestore(&chv_lock, flags); 862 863 return 0; 864 } 865 866 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 867 struct pinctrl_gpio_range *range, 868 unsigned offset) 869 { 870 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 871 unsigned long flags; 872 void __iomem *reg; 873 u32 value; 874 875 raw_spin_lock_irqsave(&chv_lock, flags); 876 877 if (chv_pad_locked(pctrl, offset)) { 878 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 879 if (!(value & CHV_PADCTRL0_GPIOEN)) { 880 /* Locked so cannot enable */ 881 raw_spin_unlock_irqrestore(&chv_lock, flags); 882 return -EBUSY; 883 } 884 } else { 885 int i; 886 887 /* Reset the interrupt mapping */ 888 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 889 if (pctrl->intr_lines[i] == offset) { 890 pctrl->intr_lines[i] = 0; 891 break; 892 } 893 } 894 895 /* Disable interrupt generation */ 896 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 897 value = readl(reg); 898 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 899 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 900 chv_writel(value, reg); 901 902 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 903 value = readl(reg); 904 905 /* 906 * If the pin is in HiZ mode (both TX and RX buffers are 907 * disabled) we turn it to be input now. 908 */ 909 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 910 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 911 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 912 value |= CHV_PADCTRL0_GPIOCFG_GPI << 913 CHV_PADCTRL0_GPIOCFG_SHIFT; 914 } 915 916 /* Switch to a GPIO mode */ 917 value |= CHV_PADCTRL0_GPIOEN; 918 chv_writel(value, reg); 919 } 920 921 raw_spin_unlock_irqrestore(&chv_lock, flags); 922 923 return 0; 924 } 925 926 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 927 struct pinctrl_gpio_range *range, 928 unsigned offset) 929 { 930 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 931 unsigned long flags; 932 void __iomem *reg; 933 u32 value; 934 935 raw_spin_lock_irqsave(&chv_lock, flags); 936 937 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 938 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 939 chv_writel(value, reg); 940 941 raw_spin_unlock_irqrestore(&chv_lock, flags); 942 } 943 944 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 945 struct pinctrl_gpio_range *range, 946 unsigned offset, bool input) 947 { 948 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 949 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 950 unsigned long flags; 951 u32 ctrl0; 952 953 raw_spin_lock_irqsave(&chv_lock, flags); 954 955 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 956 if (input) 957 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 958 else 959 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 960 chv_writel(ctrl0, reg); 961 962 raw_spin_unlock_irqrestore(&chv_lock, flags); 963 964 return 0; 965 } 966 967 static const struct pinmux_ops chv_pinmux_ops = { 968 .get_functions_count = chv_get_functions_count, 969 .get_function_name = chv_get_function_name, 970 .get_function_groups = chv_get_function_groups, 971 .set_mux = chv_pinmux_set_mux, 972 .gpio_request_enable = chv_gpio_request_enable, 973 .gpio_disable_free = chv_gpio_disable_free, 974 .gpio_set_direction = chv_gpio_set_direction, 975 }; 976 977 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 978 unsigned long *config) 979 { 980 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 981 enum pin_config_param param = pinconf_to_config_param(*config); 982 unsigned long flags; 983 u32 ctrl0, ctrl1; 984 u16 arg = 0; 985 u32 term; 986 987 raw_spin_lock_irqsave(&chv_lock, flags); 988 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 989 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 990 raw_spin_unlock_irqrestore(&chv_lock, flags); 991 992 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 993 994 switch (param) { 995 case PIN_CONFIG_BIAS_DISABLE: 996 if (term) 997 return -EINVAL; 998 break; 999 1000 case PIN_CONFIG_BIAS_PULL_UP: 1001 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 1002 return -EINVAL; 1003 1004 switch (term) { 1005 case CHV_PADCTRL0_TERM_20K: 1006 arg = 20000; 1007 break; 1008 case CHV_PADCTRL0_TERM_5K: 1009 arg = 5000; 1010 break; 1011 case CHV_PADCTRL0_TERM_1K: 1012 arg = 1000; 1013 break; 1014 } 1015 1016 break; 1017 1018 case PIN_CONFIG_BIAS_PULL_DOWN: 1019 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 1020 return -EINVAL; 1021 1022 switch (term) { 1023 case CHV_PADCTRL0_TERM_20K: 1024 arg = 20000; 1025 break; 1026 case CHV_PADCTRL0_TERM_5K: 1027 arg = 5000; 1028 break; 1029 } 1030 1031 break; 1032 1033 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1034 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 1035 return -EINVAL; 1036 break; 1037 1038 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1039 u32 cfg; 1040 1041 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1042 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1043 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1044 return -EINVAL; 1045 1046 break; 1047 } 1048 1049 default: 1050 return -ENOTSUPP; 1051 } 1052 1053 *config = pinconf_to_config_packed(param, arg); 1054 return 0; 1055 } 1056 1057 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 1058 enum pin_config_param param, u32 arg) 1059 { 1060 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1061 unsigned long flags; 1062 u32 ctrl0, pull; 1063 1064 raw_spin_lock_irqsave(&chv_lock, flags); 1065 ctrl0 = readl(reg); 1066 1067 switch (param) { 1068 case PIN_CONFIG_BIAS_DISABLE: 1069 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1070 break; 1071 1072 case PIN_CONFIG_BIAS_PULL_UP: 1073 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1074 1075 switch (arg) { 1076 case 1000: 1077 /* For 1k there is only pull up */ 1078 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1079 break; 1080 case 5000: 1081 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1082 break; 1083 case 20000: 1084 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1085 break; 1086 default: 1087 raw_spin_unlock_irqrestore(&chv_lock, flags); 1088 return -EINVAL; 1089 } 1090 1091 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1092 break; 1093 1094 case PIN_CONFIG_BIAS_PULL_DOWN: 1095 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1096 1097 switch (arg) { 1098 case 5000: 1099 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1100 break; 1101 case 20000: 1102 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1103 break; 1104 default: 1105 raw_spin_unlock_irqrestore(&chv_lock, flags); 1106 return -EINVAL; 1107 } 1108 1109 ctrl0 |= pull; 1110 break; 1111 1112 default: 1113 raw_spin_unlock_irqrestore(&chv_lock, flags); 1114 return -EINVAL; 1115 } 1116 1117 chv_writel(ctrl0, reg); 1118 raw_spin_unlock_irqrestore(&chv_lock, flags); 1119 1120 return 0; 1121 } 1122 1123 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1124 bool enable) 1125 { 1126 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1127 unsigned long flags; 1128 u32 ctrl1; 1129 1130 raw_spin_lock_irqsave(&chv_lock, flags); 1131 ctrl1 = readl(reg); 1132 1133 if (enable) 1134 ctrl1 |= CHV_PADCTRL1_ODEN; 1135 else 1136 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1137 1138 chv_writel(ctrl1, reg); 1139 raw_spin_unlock_irqrestore(&chv_lock, flags); 1140 1141 return 0; 1142 } 1143 1144 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1145 unsigned long *configs, unsigned nconfigs) 1146 { 1147 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1148 enum pin_config_param param; 1149 int i, ret; 1150 u32 arg; 1151 1152 if (chv_pad_locked(pctrl, pin)) 1153 return -EBUSY; 1154 1155 for (i = 0; i < nconfigs; i++) { 1156 param = pinconf_to_config_param(configs[i]); 1157 arg = pinconf_to_config_argument(configs[i]); 1158 1159 switch (param) { 1160 case PIN_CONFIG_BIAS_DISABLE: 1161 case PIN_CONFIG_BIAS_PULL_UP: 1162 case PIN_CONFIG_BIAS_PULL_DOWN: 1163 ret = chv_config_set_pull(pctrl, pin, param, arg); 1164 if (ret) 1165 return ret; 1166 break; 1167 1168 case PIN_CONFIG_DRIVE_PUSH_PULL: 1169 ret = chv_config_set_oden(pctrl, pin, false); 1170 if (ret) 1171 return ret; 1172 break; 1173 1174 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1175 ret = chv_config_set_oden(pctrl, pin, true); 1176 if (ret) 1177 return ret; 1178 break; 1179 1180 default: 1181 return -ENOTSUPP; 1182 } 1183 1184 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1185 param, arg); 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1192 unsigned int group, 1193 unsigned long *config) 1194 { 1195 const unsigned int *pins; 1196 unsigned int npins; 1197 int ret; 1198 1199 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1200 if (ret) 1201 return ret; 1202 1203 ret = chv_config_get(pctldev, pins[0], config); 1204 if (ret) 1205 return ret; 1206 1207 return 0; 1208 } 1209 1210 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1211 unsigned int group, unsigned long *configs, 1212 unsigned int num_configs) 1213 { 1214 const unsigned int *pins; 1215 unsigned int npins; 1216 int i, ret; 1217 1218 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1219 if (ret) 1220 return ret; 1221 1222 for (i = 0; i < npins; i++) { 1223 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1224 if (ret) 1225 return ret; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static const struct pinconf_ops chv_pinconf_ops = { 1232 .is_generic = true, 1233 .pin_config_set = chv_config_set, 1234 .pin_config_get = chv_config_get, 1235 .pin_config_group_get = chv_config_group_get, 1236 .pin_config_group_set = chv_config_group_set, 1237 }; 1238 1239 static struct pinctrl_desc chv_pinctrl_desc = { 1240 .pctlops = &chv_pinctrl_ops, 1241 .pmxops = &chv_pinmux_ops, 1242 .confops = &chv_pinconf_ops, 1243 .owner = THIS_MODULE, 1244 }; 1245 1246 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1247 { 1248 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1249 unsigned long flags; 1250 u32 ctrl0, cfg; 1251 1252 raw_spin_lock_irqsave(&chv_lock, flags); 1253 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1254 raw_spin_unlock_irqrestore(&chv_lock, flags); 1255 1256 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1257 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1258 1259 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1260 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1261 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1262 } 1263 1264 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1265 { 1266 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1267 unsigned long flags; 1268 void __iomem *reg; 1269 u32 ctrl0; 1270 1271 raw_spin_lock_irqsave(&chv_lock, flags); 1272 1273 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 1274 ctrl0 = readl(reg); 1275 1276 if (value) 1277 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1278 else 1279 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1280 1281 chv_writel(ctrl0, reg); 1282 1283 raw_spin_unlock_irqrestore(&chv_lock, flags); 1284 } 1285 1286 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1287 { 1288 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1289 u32 ctrl0, direction; 1290 unsigned long flags; 1291 1292 raw_spin_lock_irqsave(&chv_lock, flags); 1293 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1294 raw_spin_unlock_irqrestore(&chv_lock, flags); 1295 1296 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1297 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1298 1299 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1300 } 1301 1302 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1303 { 1304 return pinctrl_gpio_direction_input(chip->base + offset); 1305 } 1306 1307 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1308 int value) 1309 { 1310 chv_gpio_set(chip, offset, value); 1311 return pinctrl_gpio_direction_output(chip->base + offset); 1312 } 1313 1314 static const struct gpio_chip chv_gpio_chip = { 1315 .owner = THIS_MODULE, 1316 .request = gpiochip_generic_request, 1317 .free = gpiochip_generic_free, 1318 .get_direction = chv_gpio_get_direction, 1319 .direction_input = chv_gpio_direction_input, 1320 .direction_output = chv_gpio_direction_output, 1321 .get = chv_gpio_get, 1322 .set = chv_gpio_set, 1323 }; 1324 1325 static void chv_gpio_irq_ack(struct irq_data *d) 1326 { 1327 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1328 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1329 int pin = irqd_to_hwirq(d); 1330 u32 intr_line; 1331 1332 raw_spin_lock(&chv_lock); 1333 1334 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1335 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1336 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1337 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1338 1339 raw_spin_unlock(&chv_lock); 1340 } 1341 1342 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1343 { 1344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1345 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1346 int pin = irqd_to_hwirq(d); 1347 u32 value, intr_line; 1348 unsigned long flags; 1349 1350 raw_spin_lock_irqsave(&chv_lock, flags); 1351 1352 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1353 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1354 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1355 1356 value = readl(pctrl->regs + CHV_INTMASK); 1357 if (mask) 1358 value &= ~BIT(intr_line); 1359 else 1360 value |= BIT(intr_line); 1361 chv_writel(value, pctrl->regs + CHV_INTMASK); 1362 1363 raw_spin_unlock_irqrestore(&chv_lock, flags); 1364 } 1365 1366 static void chv_gpio_irq_mask(struct irq_data *d) 1367 { 1368 chv_gpio_irq_mask_unmask(d, true); 1369 } 1370 1371 static void chv_gpio_irq_unmask(struct irq_data *d) 1372 { 1373 chv_gpio_irq_mask_unmask(d, false); 1374 } 1375 1376 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1377 { 1378 /* 1379 * Check if the interrupt has been requested with 0 as triggering 1380 * type. In that case it is assumed that the current values 1381 * programmed to the hardware are used (e.g BIOS configured 1382 * defaults). 1383 * 1384 * In that case ->irq_set_type() will never be called so we need to 1385 * read back the values from hardware now, set correct flow handler 1386 * and update mappings before the interrupt is being used. 1387 */ 1388 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1390 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1391 unsigned pin = irqd_to_hwirq(d); 1392 irq_flow_handler_t handler; 1393 unsigned long flags; 1394 u32 intsel, value; 1395 1396 raw_spin_lock_irqsave(&chv_lock, flags); 1397 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1398 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1399 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1400 1401 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1402 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1403 handler = handle_level_irq; 1404 else 1405 handler = handle_edge_irq; 1406 1407 if (!pctrl->intr_lines[intsel]) { 1408 irq_set_handler_locked(d, handler); 1409 pctrl->intr_lines[intsel] = pin; 1410 } 1411 raw_spin_unlock_irqrestore(&chv_lock, flags); 1412 } 1413 1414 chv_gpio_irq_unmask(d); 1415 return 0; 1416 } 1417 1418 static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 1419 { 1420 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1421 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1422 unsigned pin = irqd_to_hwirq(d); 1423 unsigned long flags; 1424 u32 value; 1425 1426 raw_spin_lock_irqsave(&chv_lock, flags); 1427 1428 /* 1429 * Pins which can be used as shared interrupt are configured in 1430 * BIOS. Driver trusts BIOS configurations and assigns different 1431 * handler according to the irq type. 1432 * 1433 * Driver needs to save the mapping between each pin and 1434 * its interrupt line. 1435 * 1. If the pin cfg is locked in BIOS: 1436 * Trust BIOS has programmed IntWakeCfg bits correctly, 1437 * driver just needs to save the mapping. 1438 * 2. If the pin cfg is not locked in BIOS: 1439 * Driver programs the IntWakeCfg bits and save the mapping. 1440 */ 1441 if (!chv_pad_locked(pctrl, pin)) { 1442 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1443 1444 value = readl(reg); 1445 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1446 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1447 1448 if (type & IRQ_TYPE_EDGE_BOTH) { 1449 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1450 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1451 else if (type & IRQ_TYPE_EDGE_RISING) 1452 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1453 else if (type & IRQ_TYPE_EDGE_FALLING) 1454 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1455 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1456 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1457 if (type & IRQ_TYPE_LEVEL_LOW) 1458 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1459 } 1460 1461 chv_writel(value, reg); 1462 } 1463 1464 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1465 value &= CHV_PADCTRL0_INTSEL_MASK; 1466 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1467 1468 pctrl->intr_lines[value] = pin; 1469 1470 if (type & IRQ_TYPE_EDGE_BOTH) 1471 irq_set_handler_locked(d, handle_edge_irq); 1472 else if (type & IRQ_TYPE_LEVEL_MASK) 1473 irq_set_handler_locked(d, handle_level_irq); 1474 1475 raw_spin_unlock_irqrestore(&chv_lock, flags); 1476 1477 return 0; 1478 } 1479 1480 static struct irq_chip chv_gpio_irqchip = { 1481 .name = "chv-gpio", 1482 .irq_startup = chv_gpio_irq_startup, 1483 .irq_ack = chv_gpio_irq_ack, 1484 .irq_mask = chv_gpio_irq_mask, 1485 .irq_unmask = chv_gpio_irq_unmask, 1486 .irq_set_type = chv_gpio_irq_type, 1487 .flags = IRQCHIP_SKIP_SET_WAKE, 1488 }; 1489 1490 static void chv_gpio_irq_handler(struct irq_desc *desc) 1491 { 1492 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1493 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1494 struct irq_chip *chip = irq_desc_get_chip(desc); 1495 unsigned long pending; 1496 u32 intr_line; 1497 1498 chained_irq_enter(chip, desc); 1499 1500 pending = readl(pctrl->regs + CHV_INTSTAT); 1501 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 1502 unsigned irq, offset; 1503 1504 offset = pctrl->intr_lines[intr_line]; 1505 irq = irq_find_mapping(gc->irq.domain, offset); 1506 generic_handle_irq(irq); 1507 } 1508 1509 chained_irq_exit(chip, desc); 1510 } 1511 1512 /* 1513 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1514 * tables. Since we leave GPIOs that are not capable of generating 1515 * interrupts out of the irqdomain the numbering will be different and 1516 * cause devices using the hardcoded IRQ numbers fail. In order not to 1517 * break such machines we will only mask pins from irqdomain if the machine 1518 * is not listed below. 1519 */ 1520 static const struct dmi_system_id chv_no_valid_mask[] = { 1521 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1522 { 1523 .ident = "Intel_Strago based Chromebooks (All models)", 1524 .matches = { 1525 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1526 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1527 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1528 }, 1529 }, 1530 { 1531 .ident = "HP Chromebook 11 G5 (Setzer)", 1532 .matches = { 1533 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1534 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1535 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1536 }, 1537 }, 1538 { 1539 .ident = "Acer Chromebook R11 (Cyan)", 1540 .matches = { 1541 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1542 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1543 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1544 }, 1545 }, 1546 { 1547 .ident = "Samsung Chromebook 3 (Celes)", 1548 .matches = { 1549 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1550 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1551 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1552 }, 1553 }, 1554 {} 1555 }; 1556 1557 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1558 { 1559 const struct chv_gpio_pinrange *range; 1560 struct gpio_chip *chip = &pctrl->chip; 1561 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1562 const struct chv_community *community = pctrl->community; 1563 int ret, i, irq_base; 1564 1565 *chip = chv_gpio_chip; 1566 1567 chip->ngpio = community->pins[community->npins - 1].number + 1; 1568 chip->label = dev_name(pctrl->dev); 1569 chip->parent = pctrl->dev; 1570 chip->base = -1; 1571 chip->irq.need_valid_mask = need_valid_mask; 1572 1573 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1574 if (ret) { 1575 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1576 return ret; 1577 } 1578 1579 for (i = 0; i < community->ngpio_ranges; i++) { 1580 range = &community->gpio_ranges[i]; 1581 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), 1582 range->base, range->base, 1583 range->npins); 1584 if (ret) { 1585 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1586 return ret; 1587 } 1588 } 1589 1590 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1591 for (i = 0; i < community->npins; i++) { 1592 const struct pinctrl_pin_desc *desc; 1593 u32 intsel; 1594 1595 desc = &community->pins[i]; 1596 1597 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 1598 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1599 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1600 1601 if (need_valid_mask && intsel >= community->nirqs) 1602 clear_bit(i, chip->irq.valid_mask); 1603 } 1604 1605 /* 1606 * The same set of machines in chv_no_valid_mask[] have incorrectly 1607 * configured GPIOs that generate spurious interrupts so we use 1608 * this same list to apply another quirk for them. 1609 * 1610 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1611 */ 1612 if (!need_valid_mask) { 1613 /* 1614 * Mask all interrupts the community is able to generate 1615 * but leave the ones that can only generate GPEs unmasked. 1616 */ 1617 chv_writel(GENMASK(31, pctrl->community->nirqs), 1618 pctrl->regs + CHV_INTMASK); 1619 } 1620 1621 /* Clear all interrupts */ 1622 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1623 1624 if (!need_valid_mask) { 1625 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 1626 community->npins, NUMA_NO_NODE); 1627 if (irq_base < 0) { 1628 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1629 return irq_base; 1630 } 1631 } 1632 1633 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1634 handle_bad_irq, IRQ_TYPE_NONE); 1635 if (ret) { 1636 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1637 return ret; 1638 } 1639 1640 if (!need_valid_mask) { 1641 for (i = 0; i < community->ngpio_ranges; i++) { 1642 range = &community->gpio_ranges[i]; 1643 1644 irq_domain_associate_many(chip->irq.domain, irq_base, 1645 range->base, range->npins); 1646 irq_base += range->npins; 1647 } 1648 } 1649 1650 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1651 chv_gpio_irq_handler); 1652 return 0; 1653 } 1654 1655 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1656 acpi_physical_address address, u32 bits, u64 *value, 1657 void *handler_context, void *region_context) 1658 { 1659 struct chv_pinctrl *pctrl = region_context; 1660 unsigned long flags; 1661 acpi_status ret = AE_OK; 1662 1663 raw_spin_lock_irqsave(&chv_lock, flags); 1664 1665 if (function == ACPI_WRITE) 1666 chv_writel((u32)(*value), pctrl->regs + (u32)address); 1667 else if (function == ACPI_READ) 1668 *value = readl(pctrl->regs + (u32)address); 1669 else 1670 ret = AE_BAD_PARAMETER; 1671 1672 raw_spin_unlock_irqrestore(&chv_lock, flags); 1673 1674 return ret; 1675 } 1676 1677 static int chv_pinctrl_probe(struct platform_device *pdev) 1678 { 1679 struct chv_pinctrl *pctrl; 1680 struct acpi_device *adev; 1681 struct resource *res; 1682 acpi_status status; 1683 int ret, irq, i; 1684 1685 adev = ACPI_COMPANION(&pdev->dev); 1686 if (!adev) 1687 return -ENODEV; 1688 1689 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1690 if (!pctrl) 1691 return -ENOMEM; 1692 1693 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1694 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1695 pctrl->community = chv_communities[i]; 1696 break; 1697 } 1698 if (i == ARRAY_SIZE(chv_communities)) 1699 return -ENODEV; 1700 1701 pctrl->dev = &pdev->dev; 1702 1703 #ifdef CONFIG_PM_SLEEP 1704 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 1705 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 1706 GFP_KERNEL); 1707 if (!pctrl->saved_pin_context) 1708 return -ENOMEM; 1709 #endif 1710 1711 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1712 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1713 if (IS_ERR(pctrl->regs)) 1714 return PTR_ERR(pctrl->regs); 1715 1716 irq = platform_get_irq(pdev, 0); 1717 if (irq < 0) { 1718 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1719 return irq; 1720 } 1721 1722 pctrl->pctldesc = chv_pinctrl_desc; 1723 pctrl->pctldesc.name = dev_name(&pdev->dev); 1724 pctrl->pctldesc.pins = pctrl->community->pins; 1725 pctrl->pctldesc.npins = pctrl->community->npins; 1726 1727 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1728 pctrl); 1729 if (IS_ERR(pctrl->pctldev)) { 1730 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1731 return PTR_ERR(pctrl->pctldev); 1732 } 1733 1734 ret = chv_gpio_probe(pctrl, irq); 1735 if (ret) 1736 return ret; 1737 1738 status = acpi_install_address_space_handler(adev->handle, 1739 pctrl->community->acpi_space_id, 1740 chv_pinctrl_mmio_access_handler, 1741 NULL, pctrl); 1742 if (ACPI_FAILURE(status)) 1743 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1744 1745 platform_set_drvdata(pdev, pctrl); 1746 1747 return 0; 1748 } 1749 1750 static int chv_pinctrl_remove(struct platform_device *pdev) 1751 { 1752 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1753 1754 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1755 pctrl->community->acpi_space_id, 1756 chv_pinctrl_mmio_access_handler); 1757 1758 return 0; 1759 } 1760 1761 #ifdef CONFIG_PM_SLEEP 1762 static int chv_pinctrl_suspend_noirq(struct device *dev) 1763 { 1764 struct platform_device *pdev = to_platform_device(dev); 1765 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1766 unsigned long flags; 1767 int i; 1768 1769 raw_spin_lock_irqsave(&chv_lock, flags); 1770 1771 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1772 1773 for (i = 0; i < pctrl->community->npins; i++) { 1774 const struct pinctrl_pin_desc *desc; 1775 struct chv_pin_context *ctx; 1776 void __iomem *reg; 1777 1778 desc = &pctrl->community->pins[i]; 1779 if (chv_pad_locked(pctrl, desc->number)) 1780 continue; 1781 1782 ctx = &pctrl->saved_pin_context[i]; 1783 1784 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1785 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1786 1787 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1788 ctx->padctrl1 = readl(reg); 1789 } 1790 1791 raw_spin_unlock_irqrestore(&chv_lock, flags); 1792 1793 return 0; 1794 } 1795 1796 static int chv_pinctrl_resume_noirq(struct device *dev) 1797 { 1798 struct platform_device *pdev = to_platform_device(dev); 1799 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1800 unsigned long flags; 1801 int i; 1802 1803 raw_spin_lock_irqsave(&chv_lock, flags); 1804 1805 /* 1806 * Mask all interrupts before restoring per-pin configuration 1807 * registers because we don't know in which state BIOS left them 1808 * upon exiting suspend. 1809 */ 1810 chv_writel(0, pctrl->regs + CHV_INTMASK); 1811 1812 for (i = 0; i < pctrl->community->npins; i++) { 1813 const struct pinctrl_pin_desc *desc; 1814 const struct chv_pin_context *ctx; 1815 void __iomem *reg; 1816 u32 val; 1817 1818 desc = &pctrl->community->pins[i]; 1819 if (chv_pad_locked(pctrl, desc->number)) 1820 continue; 1821 1822 ctx = &pctrl->saved_pin_context[i]; 1823 1824 /* Only restore if our saved state differs from the current */ 1825 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1826 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1827 if (ctx->padctrl0 != val) { 1828 chv_writel(ctx->padctrl0, reg); 1829 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1830 desc->number, readl(reg)); 1831 } 1832 1833 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1834 val = readl(reg); 1835 if (ctx->padctrl1 != val) { 1836 chv_writel(ctx->padctrl1, reg); 1837 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1838 desc->number, readl(reg)); 1839 } 1840 } 1841 1842 /* 1843 * Now that all pins are restored to known state, we can restore 1844 * the interrupt mask register as well. 1845 */ 1846 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1847 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1848 1849 raw_spin_unlock_irqrestore(&chv_lock, flags); 1850 1851 return 0; 1852 } 1853 #endif 1854 1855 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1856 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1857 chv_pinctrl_resume_noirq) 1858 }; 1859 1860 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1861 { "INT33FF" }, 1862 { } 1863 }; 1864 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1865 1866 static struct platform_driver chv_pinctrl_driver = { 1867 .probe = chv_pinctrl_probe, 1868 .remove = chv_pinctrl_remove, 1869 .driver = { 1870 .name = "cherryview-pinctrl", 1871 .pm = &chv_pinctrl_pm_ops, 1872 .acpi_match_table = chv_pinctrl_acpi_match, 1873 }, 1874 }; 1875 1876 static int __init chv_pinctrl_init(void) 1877 { 1878 return platform_driver_register(&chv_pinctrl_driver); 1879 } 1880 subsys_initcall(chv_pinctrl_init); 1881 1882 static void __exit chv_pinctrl_exit(void) 1883 { 1884 platform_driver_unregister(&chv_pinctrl_driver); 1885 } 1886 module_exit(chv_pinctrl_exit); 1887 1888 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1889 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1890 MODULE_LICENSE("GPL v2"); 1891