1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, 2020 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/dmi.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/types.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include "pinctrl-intel.h" 29 30 #define CHV_INTSTAT 0x300 31 #define CHV_INTMASK 0x380 32 33 #define FAMILY_PAD_REGS_OFF 0x4400 34 #define FAMILY_PAD_REGS_SIZE 0x400 35 #define MAX_FAMILY_PAD_GPIO_NO 15 36 #define GPIO_REGS_SIZE 8 37 38 #define CHV_PADCTRL0 0x000 39 #define CHV_PADCTRL0_INTSEL_SHIFT 28 40 #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) 41 #define CHV_PADCTRL0_TERM_UP BIT(23) 42 #define CHV_PADCTRL0_TERM_SHIFT 20 43 #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) 44 #define CHV_PADCTRL0_TERM_20K 1 45 #define CHV_PADCTRL0_TERM_5K 2 46 #define CHV_PADCTRL0_TERM_1K 4 47 #define CHV_PADCTRL0_PMODE_SHIFT 16 48 #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) 49 #define CHV_PADCTRL0_GPIOEN BIT(15) 50 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 51 #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) 52 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 53 #define CHV_PADCTRL0_GPIOCFG_GPO 1 54 #define CHV_PADCTRL0_GPIOCFG_GPI 2 55 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 56 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 57 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 58 59 #define CHV_PADCTRL1 0x004 60 #define CHV_PADCTRL1_CFGLOCK BIT(31) 61 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 62 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) 63 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) 64 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) 65 #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) 66 #define CHV_PADCTRL1_ODEN BIT(3) 67 #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) 68 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 69 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 70 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 71 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 72 73 struct intel_pad_context { 74 u32 padctrl0; 75 u32 padctrl1; 76 }; 77 78 #define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ) 79 80 /** 81 * struct intel_community_context - community context for Cherryview 82 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) 83 * @saved_intmask: Interrupt mask saved for system sleep 84 */ 85 struct intel_community_context { 86 unsigned int intr_lines[16]; 87 u32 saved_intmask; 88 }; 89 90 #define PINMODE_INVERT_OE BIT(15) 91 92 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 93 94 #define CHV_GPP(start, end) \ 95 { \ 96 .base = (start), \ 97 .size = (end) - (start) + 1, \ 98 } 99 100 #define CHV_COMMUNITY(g, i, a) \ 101 { \ 102 .gpps = (g), \ 103 .ngpps = ARRAY_SIZE(g), \ 104 .nirqs = (i), \ 105 .acpi_space_id = (a), \ 106 } 107 108 static const struct pinctrl_pin_desc southwest_pins[] = { 109 PINCTRL_PIN(0, "FST_SPI_D2"), 110 PINCTRL_PIN(1, "FST_SPI_D0"), 111 PINCTRL_PIN(2, "FST_SPI_CLK"), 112 PINCTRL_PIN(3, "FST_SPI_D3"), 113 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 114 PINCTRL_PIN(5, "FST_SPI_D1"), 115 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 116 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 117 118 PINCTRL_PIN(15, "UART1_RTS_B"), 119 PINCTRL_PIN(16, "UART1_RXD"), 120 PINCTRL_PIN(17, "UART2_RXD"), 121 PINCTRL_PIN(18, "UART1_CTS_B"), 122 PINCTRL_PIN(19, "UART2_RTS_B"), 123 PINCTRL_PIN(20, "UART1_TXD"), 124 PINCTRL_PIN(21, "UART2_TXD"), 125 PINCTRL_PIN(22, "UART2_CTS_B"), 126 127 PINCTRL_PIN(30, "MF_HDA_CLK"), 128 PINCTRL_PIN(31, "MF_HDA_RSTB"), 129 PINCTRL_PIN(32, "MF_HDA_SDIO"), 130 PINCTRL_PIN(33, "MF_HDA_SDO"), 131 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 132 PINCTRL_PIN(35, "MF_HDA_SYNC"), 133 PINCTRL_PIN(36, "MF_HDA_SDI1"), 134 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 135 136 PINCTRL_PIN(45, "I2C5_SDA"), 137 PINCTRL_PIN(46, "I2C4_SDA"), 138 PINCTRL_PIN(47, "I2C6_SDA"), 139 PINCTRL_PIN(48, "I2C5_SCL"), 140 PINCTRL_PIN(49, "I2C_NFC_SDA"), 141 PINCTRL_PIN(50, "I2C4_SCL"), 142 PINCTRL_PIN(51, "I2C6_SCL"), 143 PINCTRL_PIN(52, "I2C_NFC_SCL"), 144 145 PINCTRL_PIN(60, "I2C1_SDA"), 146 PINCTRL_PIN(61, "I2C0_SDA"), 147 PINCTRL_PIN(62, "I2C2_SDA"), 148 PINCTRL_PIN(63, "I2C1_SCL"), 149 PINCTRL_PIN(64, "I2C3_SDA"), 150 PINCTRL_PIN(65, "I2C0_SCL"), 151 PINCTRL_PIN(66, "I2C2_SCL"), 152 PINCTRL_PIN(67, "I2C3_SCL"), 153 154 PINCTRL_PIN(75, "SATA_GP0"), 155 PINCTRL_PIN(76, "SATA_GP1"), 156 PINCTRL_PIN(77, "SATA_LEDN"), 157 PINCTRL_PIN(78, "SATA_GP2"), 158 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 159 PINCTRL_PIN(80, "SATA_GP3"), 160 PINCTRL_PIN(81, "MF_SMB_CLK"), 161 PINCTRL_PIN(82, "MF_SMB_DATA"), 162 163 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 164 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 165 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 166 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 167 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 168 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 169 PINCTRL_PIN(96, "GP_SSP_2_FS"), 170 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 171 }; 172 173 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 174 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 175 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 176 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 177 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 178 static const unsigned southwest_lpe_pins[] = { 179 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 180 }; 181 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 182 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 183 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 184 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 185 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 186 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 187 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 188 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 189 190 /* Some of LPE I2S TXD pins need to have OE inversion set */ 191 static const unsigned int southwest_lpe_altfuncs[] = { 192 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ 193 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ 194 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ 195 }; 196 197 /* 198 * Two spi3 chipselects are available in different mode than the main spi3 199 * functionality, which is using mode 2. 200 */ 201 static const unsigned int southwest_spi3_altfuncs[] = { 202 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ 203 PINMODE(2, 0), /* 82 */ 204 }; 205 206 static const struct intel_pingroup southwest_groups[] = { 207 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), 208 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), 209 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), 210 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), 211 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), 212 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), 213 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), 214 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), 215 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), 216 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), 217 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), 218 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), 219 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), 220 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), 221 }; 222 223 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 224 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 225 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 226 static const char * const southwest_hda_groups[] = { "hda_grp" }; 227 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 228 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 229 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 230 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 231 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 232 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 233 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 234 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 235 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 236 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 237 238 /* 239 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 240 * enabled only as GPIOs. 241 */ 242 static const struct intel_function southwest_functions[] = { 243 FUNCTION("uart0", southwest_uart0_groups), 244 FUNCTION("uart1", southwest_uart1_groups), 245 FUNCTION("uart2", southwest_uart2_groups), 246 FUNCTION("hda", southwest_hda_groups), 247 FUNCTION("lpe", southwest_lpe_groups), 248 FUNCTION("i2c0", southwest_i2c0_groups), 249 FUNCTION("i2c1", southwest_i2c1_groups), 250 FUNCTION("i2c2", southwest_i2c2_groups), 251 FUNCTION("i2c3", southwest_i2c3_groups), 252 FUNCTION("i2c4", southwest_i2c4_groups), 253 FUNCTION("i2c5", southwest_i2c5_groups), 254 FUNCTION("i2c6", southwest_i2c6_groups), 255 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 256 FUNCTION("spi3", southwest_spi3_groups), 257 }; 258 259 static const struct intel_padgroup southwest_gpps[] = { 260 CHV_GPP(0, 7), 261 CHV_GPP(15, 22), 262 CHV_GPP(30, 37), 263 CHV_GPP(45, 52), 264 CHV_GPP(60, 67), 265 CHV_GPP(75, 82), 266 CHV_GPP(90, 97), 267 }; 268 269 /* 270 * Southwest community can generate GPIO interrupts only for the first 8 271 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 272 */ 273 static const struct intel_community southwest_communities[] = { 274 CHV_COMMUNITY(southwest_gpps, 8, 0x91), 275 }; 276 277 static const struct intel_pinctrl_soc_data southwest_soc_data = { 278 .uid = "1", 279 .pins = southwest_pins, 280 .npins = ARRAY_SIZE(southwest_pins), 281 .groups = southwest_groups, 282 .ngroups = ARRAY_SIZE(southwest_groups), 283 .functions = southwest_functions, 284 .nfunctions = ARRAY_SIZE(southwest_functions), 285 .communities = southwest_communities, 286 .ncommunities = ARRAY_SIZE(southwest_communities), 287 }; 288 289 static const struct pinctrl_pin_desc north_pins[] = { 290 PINCTRL_PIN(0, "GPIO_DFX_0"), 291 PINCTRL_PIN(1, "GPIO_DFX_3"), 292 PINCTRL_PIN(2, "GPIO_DFX_7"), 293 PINCTRL_PIN(3, "GPIO_DFX_1"), 294 PINCTRL_PIN(4, "GPIO_DFX_5"), 295 PINCTRL_PIN(5, "GPIO_DFX_4"), 296 PINCTRL_PIN(6, "GPIO_DFX_8"), 297 PINCTRL_PIN(7, "GPIO_DFX_2"), 298 PINCTRL_PIN(8, "GPIO_DFX_6"), 299 300 PINCTRL_PIN(15, "GPIO_SUS0"), 301 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 302 PINCTRL_PIN(17, "GPIO_SUS3"), 303 PINCTRL_PIN(18, "GPIO_SUS7"), 304 PINCTRL_PIN(19, "GPIO_SUS1"), 305 PINCTRL_PIN(20, "GPIO_SUS5"), 306 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 307 PINCTRL_PIN(22, "GPIO_SUS4"), 308 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 309 PINCTRL_PIN(24, "GPIO_SUS2"), 310 PINCTRL_PIN(25, "GPIO_SUS6"), 311 PINCTRL_PIN(26, "CX_PREQ_B"), 312 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 313 314 PINCTRL_PIN(30, "TRST_B"), 315 PINCTRL_PIN(31, "TCK"), 316 PINCTRL_PIN(32, "PROCHOT_B"), 317 PINCTRL_PIN(33, "SVIDO_DATA"), 318 PINCTRL_PIN(34, "TMS"), 319 PINCTRL_PIN(35, "CX_PRDY_B_2"), 320 PINCTRL_PIN(36, "TDO_2"), 321 PINCTRL_PIN(37, "CX_PRDY_B"), 322 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 323 PINCTRL_PIN(39, "TDO"), 324 PINCTRL_PIN(40, "SVIDO_CLK"), 325 PINCTRL_PIN(41, "TDI"), 326 327 PINCTRL_PIN(45, "GP_CAMERASB_05"), 328 PINCTRL_PIN(46, "GP_CAMERASB_02"), 329 PINCTRL_PIN(47, "GP_CAMERASB_08"), 330 PINCTRL_PIN(48, "GP_CAMERASB_00"), 331 PINCTRL_PIN(49, "GP_CAMERASB_06"), 332 PINCTRL_PIN(50, "GP_CAMERASB_10"), 333 PINCTRL_PIN(51, "GP_CAMERASB_03"), 334 PINCTRL_PIN(52, "GP_CAMERASB_09"), 335 PINCTRL_PIN(53, "GP_CAMERASB_01"), 336 PINCTRL_PIN(54, "GP_CAMERASB_07"), 337 PINCTRL_PIN(55, "GP_CAMERASB_11"), 338 PINCTRL_PIN(56, "GP_CAMERASB_04"), 339 340 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 341 PINCTRL_PIN(61, "HV_DDI0_HPD"), 342 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 343 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 344 PINCTRL_PIN(64, "HV_DDI1_HPD"), 345 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 346 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 347 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 348 PINCTRL_PIN(68, "HV_DDI2_HPD"), 349 PINCTRL_PIN(69, "PANEL1_VDDEN"), 350 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 351 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 352 PINCTRL_PIN(72, "PANEL0_VDDEN"), 353 }; 354 355 static const struct intel_padgroup north_gpps[] = { 356 CHV_GPP(0, 8), 357 CHV_GPP(15, 27), 358 CHV_GPP(30, 41), 359 CHV_GPP(45, 56), 360 CHV_GPP(60, 72), 361 }; 362 363 /* 364 * North community can generate GPIO interrupts only for the first 8 365 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 366 */ 367 static const struct intel_community north_communities[] = { 368 CHV_COMMUNITY(north_gpps, 8, 0x92), 369 }; 370 371 static const struct intel_pinctrl_soc_data north_soc_data = { 372 .uid = "2", 373 .pins = north_pins, 374 .npins = ARRAY_SIZE(north_pins), 375 .communities = north_communities, 376 .ncommunities = ARRAY_SIZE(north_communities), 377 }; 378 379 static const struct pinctrl_pin_desc east_pins[] = { 380 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 381 PINCTRL_PIN(1, "PMU_BATLOW_B"), 382 PINCTRL_PIN(2, "SUS_STAT_B"), 383 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 384 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 385 PINCTRL_PIN(5, "PMU_PLTRST_B"), 386 PINCTRL_PIN(6, "PMU_SUSCLK"), 387 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 388 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 389 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 390 PINCTRL_PIN(10, "PMU_WAKE_B"), 391 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 392 393 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 394 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 395 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 396 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 397 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 398 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 399 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 400 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 401 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 402 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 403 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 404 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 405 }; 406 407 static const struct intel_padgroup east_gpps[] = { 408 CHV_GPP(0, 11), 409 CHV_GPP(15, 26), 410 }; 411 412 static const struct intel_community east_communities[] = { 413 CHV_COMMUNITY(east_gpps, 16, 0x93), 414 }; 415 416 static const struct intel_pinctrl_soc_data east_soc_data = { 417 .uid = "3", 418 .pins = east_pins, 419 .npins = ARRAY_SIZE(east_pins), 420 .communities = east_communities, 421 .ncommunities = ARRAY_SIZE(east_communities), 422 }; 423 424 static const struct pinctrl_pin_desc southeast_pins[] = { 425 PINCTRL_PIN(0, "MF_PLT_CLK0"), 426 PINCTRL_PIN(1, "PWM1"), 427 PINCTRL_PIN(2, "MF_PLT_CLK1"), 428 PINCTRL_PIN(3, "MF_PLT_CLK4"), 429 PINCTRL_PIN(4, "MF_PLT_CLK3"), 430 PINCTRL_PIN(5, "PWM0"), 431 PINCTRL_PIN(6, "MF_PLT_CLK5"), 432 PINCTRL_PIN(7, "MF_PLT_CLK2"), 433 434 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 435 PINCTRL_PIN(16, "SDMMC1_CLK"), 436 PINCTRL_PIN(17, "SDMMC1_D0"), 437 PINCTRL_PIN(18, "SDMMC2_D1"), 438 PINCTRL_PIN(19, "SDMMC2_CLK"), 439 PINCTRL_PIN(20, "SDMMC1_D2"), 440 PINCTRL_PIN(21, "SDMMC2_D2"), 441 PINCTRL_PIN(22, "SDMMC2_CMD"), 442 PINCTRL_PIN(23, "SDMMC1_CMD"), 443 PINCTRL_PIN(24, "SDMMC1_D1"), 444 PINCTRL_PIN(25, "SDMMC2_D0"), 445 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 446 447 PINCTRL_PIN(30, "SDMMC3_D1"), 448 PINCTRL_PIN(31, "SDMMC3_CLK"), 449 PINCTRL_PIN(32, "SDMMC3_D3"), 450 PINCTRL_PIN(33, "SDMMC3_D2"), 451 PINCTRL_PIN(34, "SDMMC3_CMD"), 452 PINCTRL_PIN(35, "SDMMC3_D0"), 453 454 PINCTRL_PIN(45, "MF_LPC_AD2"), 455 PINCTRL_PIN(46, "LPC_CLKRUNB"), 456 PINCTRL_PIN(47, "MF_LPC_AD0"), 457 PINCTRL_PIN(48, "LPC_FRAMEB"), 458 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 459 PINCTRL_PIN(50, "MF_LPC_AD3"), 460 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 461 PINCTRL_PIN(52, "MF_LPC_AD1"), 462 463 PINCTRL_PIN(60, "SPI1_MISO"), 464 PINCTRL_PIN(61, "SPI1_CSO_B"), 465 PINCTRL_PIN(62, "SPI1_CLK"), 466 PINCTRL_PIN(63, "MMC1_D6"), 467 PINCTRL_PIN(64, "SPI1_MOSI"), 468 PINCTRL_PIN(65, "MMC1_D5"), 469 PINCTRL_PIN(66, "SPI1_CS1_B"), 470 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 471 PINCTRL_PIN(68, "MMC1_D7"), 472 PINCTRL_PIN(69, "MMC1_RCLK"), 473 474 PINCTRL_PIN(75, "USB_OC1_B"), 475 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 476 PINCTRL_PIN(77, "GPIO_ALERT"), 477 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 478 PINCTRL_PIN(79, "ILB_SERIRQ"), 479 PINCTRL_PIN(80, "USB_OC0_B"), 480 PINCTRL_PIN(81, "SDMMC3_CD_B"), 481 PINCTRL_PIN(82, "SPKR"), 482 PINCTRL_PIN(83, "SUSPWRDNACK"), 483 PINCTRL_PIN(84, "SPARE_PIN"), 484 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 485 }; 486 487 static const unsigned southeast_pwm0_pins[] = { 5 }; 488 static const unsigned southeast_pwm1_pins[] = { 1 }; 489 static const unsigned southeast_sdmmc1_pins[] = { 490 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 491 }; 492 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 493 static const unsigned southeast_sdmmc3_pins[] = { 494 30, 31, 32, 33, 34, 35, 78, 81, 85, 495 }; 496 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 497 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 498 499 static const struct intel_pingroup southeast_groups[] = { 500 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), 501 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), 502 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), 503 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), 504 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), 505 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), 506 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), 507 }; 508 509 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 510 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 511 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 512 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 513 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 514 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 515 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 516 517 static const struct intel_function southeast_functions[] = { 518 FUNCTION("pwm0", southeast_pwm0_groups), 519 FUNCTION("pwm1", southeast_pwm1_groups), 520 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 521 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 522 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 523 FUNCTION("spi1", southeast_spi1_groups), 524 FUNCTION("spi2", southeast_spi2_groups), 525 }; 526 527 static const struct intel_padgroup southeast_gpps[] = { 528 CHV_GPP(0, 7), 529 CHV_GPP(15, 26), 530 CHV_GPP(30, 35), 531 CHV_GPP(45, 52), 532 CHV_GPP(60, 69), 533 CHV_GPP(75, 85), 534 }; 535 536 static const struct intel_community southeast_communities[] = { 537 CHV_COMMUNITY(southeast_gpps, 16, 0x94), 538 }; 539 540 static const struct intel_pinctrl_soc_data southeast_soc_data = { 541 .uid = "4", 542 .pins = southeast_pins, 543 .npins = ARRAY_SIZE(southeast_pins), 544 .groups = southeast_groups, 545 .ngroups = ARRAY_SIZE(southeast_groups), 546 .functions = southeast_functions, 547 .nfunctions = ARRAY_SIZE(southeast_functions), 548 .communities = southeast_communities, 549 .ncommunities = ARRAY_SIZE(southeast_communities), 550 }; 551 552 static const struct intel_pinctrl_soc_data *chv_soc_data[] = { 553 &southwest_soc_data, 554 &north_soc_data, 555 &east_soc_data, 556 &southeast_soc_data, 557 NULL 558 }; 559 560 /* 561 * Lock to serialize register accesses 562 * 563 * Due to a silicon issue, a shared lock must be used to prevent 564 * concurrent accesses across the 4 GPIO controllers. 565 * 566 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 567 * errata #CHT34, for further information. 568 */ 569 static DEFINE_RAW_SPINLOCK(chv_lock); 570 571 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) 572 { 573 const struct intel_community *community = &pctrl->communities[0]; 574 575 return readl(community->regs + offset); 576 } 577 578 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) 579 { 580 const struct intel_community *community = &pctrl->communities[0]; 581 void __iomem *reg = community->regs + offset; 582 583 /* Write and simple read back to confirm the bus transferring done */ 584 writel(value, reg); 585 readl(reg); 586 } 587 588 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, 589 unsigned int reg) 590 { 591 const struct intel_community *community = &pctrl->communities[0]; 592 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 593 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 594 595 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; 596 597 return community->pad_regs + offset + reg; 598 } 599 600 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) 601 { 602 return readl(chv_padreg(pctrl, pin, offset)); 603 } 604 605 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) 606 { 607 void __iomem *reg = chv_padreg(pctrl, pin, offset); 608 609 /* Write and simple read back to confirm the bus transferring done */ 610 writel(value, reg); 611 readl(reg); 612 } 613 614 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 615 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) 616 { 617 return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; 618 } 619 620 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 621 { 622 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 623 624 return pctrl->soc->ngroups; 625 } 626 627 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 628 unsigned int group) 629 { 630 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 631 632 return pctrl->soc->groups[group].grp.name; 633 } 634 635 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 636 const unsigned int **pins, unsigned int *npins) 637 { 638 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 639 640 *pins = pctrl->soc->groups[group].grp.pins; 641 *npins = pctrl->soc->groups[group].grp.npins; 642 return 0; 643 } 644 645 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 646 unsigned int offset) 647 { 648 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 649 unsigned long flags; 650 u32 ctrl0, ctrl1; 651 bool locked; 652 653 raw_spin_lock_irqsave(&chv_lock, flags); 654 655 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 656 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); 657 locked = chv_pad_locked(pctrl, offset); 658 659 raw_spin_unlock_irqrestore(&chv_lock, flags); 660 661 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 662 seq_puts(s, "GPIO "); 663 } else { 664 u32 mode; 665 666 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 667 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 668 669 seq_printf(s, "mode %d ", mode); 670 } 671 672 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 673 674 if (locked) 675 seq_puts(s, " [LOCKED]"); 676 } 677 678 static const struct pinctrl_ops chv_pinctrl_ops = { 679 .get_groups_count = chv_get_groups_count, 680 .get_group_name = chv_get_group_name, 681 .get_group_pins = chv_get_group_pins, 682 .pin_dbg_show = chv_pin_dbg_show, 683 }; 684 685 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 686 { 687 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 688 689 return pctrl->soc->nfunctions; 690 } 691 692 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 693 unsigned int function) 694 { 695 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 696 697 return pctrl->soc->functions[function].func.name; 698 } 699 700 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 701 unsigned int function, 702 const char * const **groups, 703 unsigned int * const ngroups) 704 { 705 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 706 707 *groups = pctrl->soc->functions[function].func.groups; 708 *ngroups = pctrl->soc->functions[function].func.ngroups; 709 return 0; 710 } 711 712 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 713 unsigned int function, unsigned int group) 714 { 715 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 716 struct device *dev = pctrl->dev; 717 const struct intel_pingroup *grp; 718 unsigned long flags; 719 int i; 720 721 grp = &pctrl->soc->groups[group]; 722 723 raw_spin_lock_irqsave(&chv_lock, flags); 724 725 /* Check first that the pad is not locked */ 726 for (i = 0; i < grp->grp.npins; i++) { 727 if (chv_pad_locked(pctrl, grp->grp.pins[i])) { 728 raw_spin_unlock_irqrestore(&chv_lock, flags); 729 dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]); 730 return -EBUSY; 731 } 732 } 733 734 for (i = 0; i < grp->grp.npins; i++) { 735 int pin = grp->grp.pins[i]; 736 unsigned int mode; 737 bool invert_oe; 738 u32 value; 739 740 /* Check if there is pin-specific config */ 741 if (grp->modes) 742 mode = grp->modes[i]; 743 else 744 mode = grp->mode; 745 746 /* Extract OE inversion */ 747 invert_oe = mode & PINMODE_INVERT_OE; 748 mode &= ~PINMODE_INVERT_OE; 749 750 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 751 /* Disable GPIO mode */ 752 value &= ~CHV_PADCTRL0_GPIOEN; 753 /* Set to desired mode */ 754 value &= ~CHV_PADCTRL0_PMODE_MASK; 755 value |= mode << CHV_PADCTRL0_PMODE_SHIFT; 756 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 757 758 /* Update for invert_oe */ 759 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK; 760 if (invert_oe) 761 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 762 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 763 764 dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode, 765 invert_oe ? "" : "not "); 766 } 767 768 raw_spin_unlock_irqrestore(&chv_lock, flags); 769 770 return 0; 771 } 772 773 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, 774 unsigned int offset) 775 { 776 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; 777 u32 value; 778 779 /* 780 * One some devices the GPIO should output the inverted value from what 781 * device-drivers / ACPI code expects (inverted external buffer?). The 782 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, 783 * preserve this flag if the pin is already setup as GPIO. 784 */ 785 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 786 if (value & CHV_PADCTRL0_GPIOEN) 787 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; 788 789 value = chv_readl(pctrl, offset, CHV_PADCTRL1); 790 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 791 value &= ~invrxtx_mask; 792 chv_writel(pctrl, offset, CHV_PADCTRL1, value); 793 } 794 795 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 796 struct pinctrl_gpio_range *range, 797 unsigned int offset) 798 { 799 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 800 unsigned long flags; 801 u32 value; 802 803 raw_spin_lock_irqsave(&chv_lock, flags); 804 805 if (chv_pad_locked(pctrl, offset)) { 806 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 807 if (!(value & CHV_PADCTRL0_GPIOEN)) { 808 /* Locked so cannot enable */ 809 raw_spin_unlock_irqrestore(&chv_lock, flags); 810 return -EBUSY; 811 } 812 } else { 813 struct intel_community_context *cctx = &pctrl->context.communities[0]; 814 int i; 815 816 /* Reset the interrupt mapping */ 817 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { 818 if (cctx->intr_lines[i] == offset) { 819 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 820 break; 821 } 822 } 823 824 /* Disable interrupt generation */ 825 chv_gpio_clear_triggering(pctrl, offset); 826 827 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 828 829 /* 830 * If the pin is in HiZ mode (both TX and RX buffers are 831 * disabled) we turn it to be input now. 832 */ 833 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 834 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 835 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 836 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 837 } 838 839 /* Switch to a GPIO mode */ 840 value |= CHV_PADCTRL0_GPIOEN; 841 chv_writel(pctrl, offset, CHV_PADCTRL0, value); 842 } 843 844 raw_spin_unlock_irqrestore(&chv_lock, flags); 845 846 return 0; 847 } 848 849 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 850 struct pinctrl_gpio_range *range, 851 unsigned int offset) 852 { 853 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 854 unsigned long flags; 855 856 raw_spin_lock_irqsave(&chv_lock, flags); 857 858 if (!chv_pad_locked(pctrl, offset)) 859 chv_gpio_clear_triggering(pctrl, offset); 860 861 raw_spin_unlock_irqrestore(&chv_lock, flags); 862 } 863 864 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 865 struct pinctrl_gpio_range *range, 866 unsigned int offset, bool input) 867 { 868 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 869 unsigned long flags; 870 u32 ctrl0; 871 872 raw_spin_lock_irqsave(&chv_lock, flags); 873 874 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; 875 if (input) 876 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 877 else 878 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 879 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 880 881 raw_spin_unlock_irqrestore(&chv_lock, flags); 882 883 return 0; 884 } 885 886 static const struct pinmux_ops chv_pinmux_ops = { 887 .get_functions_count = chv_get_functions_count, 888 .get_function_name = chv_get_function_name, 889 .get_function_groups = chv_get_function_groups, 890 .set_mux = chv_pinmux_set_mux, 891 .gpio_request_enable = chv_gpio_request_enable, 892 .gpio_disable_free = chv_gpio_disable_free, 893 .gpio_set_direction = chv_gpio_set_direction, 894 }; 895 896 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 897 unsigned long *config) 898 { 899 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 900 enum pin_config_param param = pinconf_to_config_param(*config); 901 unsigned long flags; 902 u32 ctrl0, ctrl1; 903 u16 arg = 0; 904 u32 term; 905 906 raw_spin_lock_irqsave(&chv_lock, flags); 907 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 908 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 909 raw_spin_unlock_irqrestore(&chv_lock, flags); 910 911 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 912 913 switch (param) { 914 case PIN_CONFIG_BIAS_DISABLE: 915 if (term) 916 return -EINVAL; 917 break; 918 919 case PIN_CONFIG_BIAS_PULL_UP: 920 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 921 return -EINVAL; 922 923 switch (term) { 924 case CHV_PADCTRL0_TERM_20K: 925 arg = 20000; 926 break; 927 case CHV_PADCTRL0_TERM_5K: 928 arg = 5000; 929 break; 930 case CHV_PADCTRL0_TERM_1K: 931 arg = 1000; 932 break; 933 } 934 935 break; 936 937 case PIN_CONFIG_BIAS_PULL_DOWN: 938 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 939 return -EINVAL; 940 941 switch (term) { 942 case CHV_PADCTRL0_TERM_20K: 943 arg = 20000; 944 break; 945 case CHV_PADCTRL0_TERM_5K: 946 arg = 5000; 947 break; 948 } 949 950 break; 951 952 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 953 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 954 return -EINVAL; 955 break; 956 957 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 958 u32 cfg; 959 960 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 961 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 962 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 963 return -EINVAL; 964 965 break; 966 } 967 968 default: 969 return -ENOTSUPP; 970 } 971 972 *config = pinconf_to_config_packed(param, arg); 973 return 0; 974 } 975 976 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 977 enum pin_config_param param, u32 arg) 978 { 979 unsigned long flags; 980 u32 ctrl0, pull; 981 982 raw_spin_lock_irqsave(&chv_lock, flags); 983 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 984 985 switch (param) { 986 case PIN_CONFIG_BIAS_DISABLE: 987 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 988 break; 989 990 case PIN_CONFIG_BIAS_PULL_UP: 991 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 992 993 switch (arg) { 994 case 1000: 995 /* For 1k there is only pull up */ 996 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 997 break; 998 case 5000: 999 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1000 break; 1001 case 20000: 1002 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1003 break; 1004 default: 1005 raw_spin_unlock_irqrestore(&chv_lock, flags); 1006 return -EINVAL; 1007 } 1008 1009 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1010 break; 1011 1012 case PIN_CONFIG_BIAS_PULL_DOWN: 1013 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1014 1015 switch (arg) { 1016 case 5000: 1017 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1018 break; 1019 case 20000: 1020 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1021 break; 1022 default: 1023 raw_spin_unlock_irqrestore(&chv_lock, flags); 1024 return -EINVAL; 1025 } 1026 1027 ctrl0 |= pull; 1028 break; 1029 1030 default: 1031 raw_spin_unlock_irqrestore(&chv_lock, flags); 1032 return -EINVAL; 1033 } 1034 1035 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); 1036 raw_spin_unlock_irqrestore(&chv_lock, flags); 1037 1038 return 0; 1039 } 1040 1041 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, 1042 bool enable) 1043 { 1044 unsigned long flags; 1045 u32 ctrl1; 1046 1047 raw_spin_lock_irqsave(&chv_lock, flags); 1048 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 1049 1050 if (enable) 1051 ctrl1 |= CHV_PADCTRL1_ODEN; 1052 else 1053 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1054 1055 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); 1056 raw_spin_unlock_irqrestore(&chv_lock, flags); 1057 1058 return 0; 1059 } 1060 1061 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1062 unsigned long *configs, unsigned int nconfigs) 1063 { 1064 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1065 struct device *dev = pctrl->dev; 1066 enum pin_config_param param; 1067 int i, ret; 1068 u32 arg; 1069 1070 if (chv_pad_locked(pctrl, pin)) 1071 return -EBUSY; 1072 1073 for (i = 0; i < nconfigs; i++) { 1074 param = pinconf_to_config_param(configs[i]); 1075 arg = pinconf_to_config_argument(configs[i]); 1076 1077 switch (param) { 1078 case PIN_CONFIG_BIAS_DISABLE: 1079 case PIN_CONFIG_BIAS_PULL_UP: 1080 case PIN_CONFIG_BIAS_PULL_DOWN: 1081 ret = chv_config_set_pull(pctrl, pin, param, arg); 1082 if (ret) 1083 return ret; 1084 break; 1085 1086 case PIN_CONFIG_DRIVE_PUSH_PULL: 1087 ret = chv_config_set_oden(pctrl, pin, false); 1088 if (ret) 1089 return ret; 1090 break; 1091 1092 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1093 ret = chv_config_set_oden(pctrl, pin, true); 1094 if (ret) 1095 return ret; 1096 break; 1097 1098 default: 1099 return -ENOTSUPP; 1100 } 1101 1102 dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg); 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1109 unsigned int group, 1110 unsigned long *config) 1111 { 1112 const unsigned int *pins; 1113 unsigned int npins; 1114 int ret; 1115 1116 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1117 if (ret) 1118 return ret; 1119 1120 ret = chv_config_get(pctldev, pins[0], config); 1121 if (ret) 1122 return ret; 1123 1124 return 0; 1125 } 1126 1127 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1128 unsigned int group, unsigned long *configs, 1129 unsigned int num_configs) 1130 { 1131 const unsigned int *pins; 1132 unsigned int npins; 1133 int i, ret; 1134 1135 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1136 if (ret) 1137 return ret; 1138 1139 for (i = 0; i < npins; i++) { 1140 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1141 if (ret) 1142 return ret; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static const struct pinconf_ops chv_pinconf_ops = { 1149 .is_generic = true, 1150 .pin_config_set = chv_config_set, 1151 .pin_config_get = chv_config_get, 1152 .pin_config_group_get = chv_config_group_get, 1153 .pin_config_group_set = chv_config_group_set, 1154 }; 1155 1156 static struct pinctrl_desc chv_pinctrl_desc = { 1157 .pctlops = &chv_pinctrl_ops, 1158 .pmxops = &chv_pinmux_ops, 1159 .confops = &chv_pinconf_ops, 1160 .owner = THIS_MODULE, 1161 }; 1162 1163 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1164 { 1165 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1166 unsigned long flags; 1167 u32 ctrl0, cfg; 1168 1169 raw_spin_lock_irqsave(&chv_lock, flags); 1170 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1171 raw_spin_unlock_irqrestore(&chv_lock, flags); 1172 1173 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1174 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1175 1176 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1177 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1178 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1179 } 1180 1181 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1182 { 1183 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1184 unsigned long flags; 1185 u32 ctrl0; 1186 1187 raw_spin_lock_irqsave(&chv_lock, flags); 1188 1189 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1190 1191 if (value) 1192 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1193 else 1194 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1195 1196 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 1197 1198 raw_spin_unlock_irqrestore(&chv_lock, flags); 1199 } 1200 1201 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1202 { 1203 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1204 u32 ctrl0, direction; 1205 unsigned long flags; 1206 1207 raw_spin_lock_irqsave(&chv_lock, flags); 1208 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1209 raw_spin_unlock_irqrestore(&chv_lock, flags); 1210 1211 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1212 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1213 1214 if (direction == CHV_PADCTRL0_GPIOCFG_GPO) 1215 return GPIO_LINE_DIRECTION_OUT; 1216 1217 return GPIO_LINE_DIRECTION_IN; 1218 } 1219 1220 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1221 { 1222 return pinctrl_gpio_direction_input(chip->base + offset); 1223 } 1224 1225 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1226 int value) 1227 { 1228 chv_gpio_set(chip, offset, value); 1229 return pinctrl_gpio_direction_output(chip->base + offset); 1230 } 1231 1232 static const struct gpio_chip chv_gpio_chip = { 1233 .owner = THIS_MODULE, 1234 .request = gpiochip_generic_request, 1235 .free = gpiochip_generic_free, 1236 .get_direction = chv_gpio_get_direction, 1237 .direction_input = chv_gpio_direction_input, 1238 .direction_output = chv_gpio_direction_output, 1239 .get = chv_gpio_get, 1240 .set = chv_gpio_set, 1241 }; 1242 1243 static void chv_gpio_irq_ack(struct irq_data *d) 1244 { 1245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1246 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1247 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1248 u32 intr_line; 1249 1250 raw_spin_lock(&chv_lock); 1251 1252 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1253 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1254 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1255 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); 1256 1257 raw_spin_unlock(&chv_lock); 1258 } 1259 1260 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1261 { 1262 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1263 u32 value, intr_line; 1264 unsigned long flags; 1265 1266 raw_spin_lock_irqsave(&chv_lock, flags); 1267 1268 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1269 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1270 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1271 1272 value = chv_pctrl_readl(pctrl, CHV_INTMASK); 1273 if (mask) 1274 value &= ~BIT(intr_line); 1275 else 1276 value |= BIT(intr_line); 1277 chv_pctrl_writel(pctrl, CHV_INTMASK, value); 1278 1279 raw_spin_unlock_irqrestore(&chv_lock, flags); 1280 } 1281 1282 static void chv_gpio_irq_mask(struct irq_data *d) 1283 { 1284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1285 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1286 1287 chv_gpio_irq_mask_unmask(gc, hwirq, true); 1288 gpiochip_disable_irq(gc, hwirq); 1289 } 1290 1291 static void chv_gpio_irq_unmask(struct irq_data *d) 1292 { 1293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1294 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1295 1296 gpiochip_enable_irq(gc, hwirq); 1297 chv_gpio_irq_mask_unmask(gc, hwirq, false); 1298 } 1299 1300 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1301 { 1302 /* 1303 * Check if the interrupt has been requested with 0 as triggering 1304 * type. In that case it is assumed that the current values 1305 * programmed to the hardware are used (e.g BIOS configured 1306 * defaults). 1307 * 1308 * In that case ->irq_set_type() will never be called so we need to 1309 * read back the values from hardware now, set correct flow handler 1310 * and update mappings before the interrupt is being used. 1311 */ 1312 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1314 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1315 struct device *dev = pctrl->dev; 1316 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1317 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1318 irq_flow_handler_t handler; 1319 unsigned long flags; 1320 u32 intsel, value; 1321 1322 raw_spin_lock_irqsave(&chv_lock, flags); 1323 intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1324 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1325 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1326 1327 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1328 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1329 handler = handle_level_irq; 1330 else 1331 handler = handle_edge_irq; 1332 1333 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1334 irq_set_handler_locked(d, handler); 1335 dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n", 1336 intsel, hwirq); 1337 cctx->intr_lines[intsel] = hwirq; 1338 } 1339 raw_spin_unlock_irqrestore(&chv_lock, flags); 1340 } 1341 1342 chv_gpio_irq_unmask(d); 1343 return 0; 1344 } 1345 1346 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) 1347 { 1348 struct device *dev = pctrl->dev; 1349 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1350 const struct intel_community *community = &pctrl->communities[0]; 1351 u32 value, intsel; 1352 int i; 1353 1354 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 1355 intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT; 1356 1357 if (cctx->intr_lines[intsel] == pin) 1358 return 0; 1359 1360 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1361 dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin); 1362 cctx->intr_lines[intsel] = pin; 1363 return 0; 1364 } 1365 1366 /* 1367 * The interrupt line selected by the BIOS is already in use by 1368 * another pin, this is a known BIOS bug found on several models. 1369 * But this may also be caused by Linux deciding to use a pin as 1370 * IRQ which was not expected to be used as such by the BIOS authors, 1371 * so log this at info level only. 1372 */ 1373 dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel, 1374 cctx->intr_lines[intsel], pin); 1375 1376 if (chv_pad_locked(pctrl, pin)) 1377 return -EBUSY; 1378 1379 /* 1380 * The BIOS fills the interrupt lines from 0 counting up, start at 1381 * the other end to find a free interrupt line to workaround this. 1382 */ 1383 for (i = community->nirqs - 1; i >= 0; i--) { 1384 if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ) 1385 break; 1386 } 1387 if (i < 0) 1388 return -EBUSY; 1389 1390 dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i); 1391 1392 value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); 1393 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 1394 cctx->intr_lines[i] = pin; 1395 1396 return 0; 1397 } 1398 1399 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1400 { 1401 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1402 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1403 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1404 unsigned long flags; 1405 u32 value; 1406 int ret; 1407 1408 raw_spin_lock_irqsave(&chv_lock, flags); 1409 1410 ret = chv_gpio_set_intr_line(pctrl, hwirq); 1411 if (ret) 1412 goto out_unlock; 1413 1414 /* 1415 * Pins which can be used as shared interrupt are configured in 1416 * BIOS. Driver trusts BIOS configurations and assigns different 1417 * handler according to the irq type. 1418 * 1419 * Driver needs to save the mapping between each pin and 1420 * its interrupt line. 1421 * 1. If the pin cfg is locked in BIOS: 1422 * Trust BIOS has programmed IntWakeCfg bits correctly, 1423 * driver just needs to save the mapping. 1424 * 2. If the pin cfg is not locked in BIOS: 1425 * Driver programs the IntWakeCfg bits and save the mapping. 1426 */ 1427 if (!chv_pad_locked(pctrl, hwirq)) { 1428 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1429 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1430 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1431 1432 if (type & IRQ_TYPE_EDGE_BOTH) { 1433 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1434 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1435 else if (type & IRQ_TYPE_EDGE_RISING) 1436 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1437 else if (type & IRQ_TYPE_EDGE_FALLING) 1438 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1439 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1440 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1441 if (type & IRQ_TYPE_LEVEL_LOW) 1442 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1443 } 1444 1445 chv_writel(pctrl, hwirq, CHV_PADCTRL1, value); 1446 } 1447 1448 if (type & IRQ_TYPE_EDGE_BOTH) 1449 irq_set_handler_locked(d, handle_edge_irq); 1450 else if (type & IRQ_TYPE_LEVEL_MASK) 1451 irq_set_handler_locked(d, handle_level_irq); 1452 1453 out_unlock: 1454 raw_spin_unlock_irqrestore(&chv_lock, flags); 1455 1456 return ret; 1457 } 1458 1459 static const struct irq_chip chv_gpio_irq_chip = { 1460 .name = "chv-gpio", 1461 .irq_startup = chv_gpio_irq_startup, 1462 .irq_ack = chv_gpio_irq_ack, 1463 .irq_mask = chv_gpio_irq_mask, 1464 .irq_unmask = chv_gpio_irq_unmask, 1465 .irq_set_type = chv_gpio_irq_type, 1466 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1467 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1468 }; 1469 1470 static void chv_gpio_irq_handler(struct irq_desc *desc) 1471 { 1472 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1473 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1474 struct device *dev = pctrl->dev; 1475 const struct intel_community *community = &pctrl->communities[0]; 1476 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1477 struct irq_chip *chip = irq_desc_get_chip(desc); 1478 unsigned long pending; 1479 unsigned long flags; 1480 u32 intr_line; 1481 1482 chained_irq_enter(chip, desc); 1483 1484 raw_spin_lock_irqsave(&chv_lock, flags); 1485 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); 1486 raw_spin_unlock_irqrestore(&chv_lock, flags); 1487 1488 for_each_set_bit(intr_line, &pending, community->nirqs) { 1489 unsigned int offset; 1490 1491 offset = cctx->intr_lines[intr_line]; 1492 if (offset == CHV_INVALID_HWIRQ) { 1493 dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line); 1494 /* Some boards expect hwirq 0 to trigger in this case */ 1495 offset = 0; 1496 } 1497 1498 generic_handle_domain_irq(gc->irq.domain, offset); 1499 } 1500 1501 chained_irq_exit(chip, desc); 1502 } 1503 1504 /* 1505 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1506 * tables. Since we leave GPIOs that are not capable of generating 1507 * interrupts out of the irqdomain the numbering will be different and 1508 * cause devices using the hardcoded IRQ numbers fail. In order not to 1509 * break such machines we will only mask pins from irqdomain if the machine 1510 * is not listed below. 1511 */ 1512 static const struct dmi_system_id chv_no_valid_mask[] = { 1513 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1514 { 1515 .ident = "Intel_Strago based Chromebooks (All models)", 1516 .matches = { 1517 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1518 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1519 }, 1520 }, 1521 { 1522 .ident = "HP Chromebook 11 G5 (Setzer)", 1523 .matches = { 1524 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1525 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1526 }, 1527 }, 1528 { 1529 .ident = "Acer Chromebook R11 (Cyan)", 1530 .matches = { 1531 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1532 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1533 }, 1534 }, 1535 { 1536 .ident = "Samsung Chromebook 3 (Celes)", 1537 .matches = { 1538 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1539 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1540 }, 1541 }, 1542 {} 1543 }; 1544 1545 static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1546 unsigned long *valid_mask, 1547 unsigned int ngpios) 1548 { 1549 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1550 const struct intel_community *community = &pctrl->communities[0]; 1551 int i; 1552 1553 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1554 for (i = 0; i < pctrl->soc->npins; i++) { 1555 const struct pinctrl_pin_desc *desc; 1556 u32 intsel; 1557 1558 desc = &pctrl->soc->pins[i]; 1559 1560 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1561 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1562 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1563 1564 if (intsel >= community->nirqs) 1565 clear_bit(desc->number, valid_mask); 1566 } 1567 } 1568 1569 static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 1570 { 1571 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1572 const struct intel_community *community = &pctrl->communities[0]; 1573 1574 /* 1575 * The same set of machines in chv_no_valid_mask[] have incorrectly 1576 * configured GPIOs that generate spurious interrupts so we use 1577 * this same list to apply another quirk for them. 1578 * 1579 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1580 */ 1581 if (!pctrl->chip.irq.init_valid_mask) { 1582 /* 1583 * Mask all interrupts the community is able to generate 1584 * but leave the ones that can only generate GPEs unmasked. 1585 */ 1586 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs)); 1587 } 1588 1589 /* Clear all interrupts */ 1590 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1591 1592 return 0; 1593 } 1594 1595 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) 1596 { 1597 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1598 struct device *dev = pctrl->dev; 1599 const struct intel_community *community = &pctrl->communities[0]; 1600 const struct intel_padgroup *gpp; 1601 int ret, i; 1602 1603 for (i = 0; i < community->ngpps; i++) { 1604 gpp = &community->gpps[i]; 1605 ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); 1606 if (ret) { 1607 dev_err(dev, "failed to add GPIO pin range\n"); 1608 return ret; 1609 } 1610 } 1611 1612 return 0; 1613 } 1614 1615 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1616 { 1617 const struct intel_community *community = &pctrl->communities[0]; 1618 const struct intel_padgroup *gpp; 1619 struct gpio_chip *chip = &pctrl->chip; 1620 struct device *dev = pctrl->dev; 1621 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1622 int ret, i, irq_base; 1623 1624 *chip = chv_gpio_chip; 1625 1626 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1627 chip->label = dev_name(dev); 1628 chip->add_pin_ranges = chv_gpio_add_pin_ranges; 1629 chip->parent = dev; 1630 chip->base = -1; 1631 1632 pctrl->irq = irq; 1633 1634 gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip); 1635 chip->irq.init_hw = chv_gpio_irq_init_hw; 1636 chip->irq.parent_handler = chv_gpio_irq_handler; 1637 chip->irq.num_parents = 1; 1638 chip->irq.parents = &pctrl->irq; 1639 chip->irq.default_type = IRQ_TYPE_NONE; 1640 chip->irq.handler = handle_bad_irq; 1641 if (need_valid_mask) { 1642 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1643 } else { 1644 irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); 1645 if (irq_base < 0) { 1646 dev_err(dev, "Failed to allocate IRQ numbers\n"); 1647 return irq_base; 1648 } 1649 } 1650 1651 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1652 if (ret) { 1653 dev_err(dev, "Failed to register gpiochip\n"); 1654 return ret; 1655 } 1656 1657 if (!need_valid_mask) { 1658 for (i = 0; i < community->ngpps; i++) { 1659 gpp = &community->gpps[i]; 1660 1661 irq_domain_associate_many(chip->irq.domain, irq_base, 1662 gpp->base, gpp->size); 1663 irq_base += gpp->size; 1664 } 1665 } 1666 1667 return 0; 1668 } 1669 1670 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1671 acpi_physical_address address, u32 bits, u64 *value, 1672 void *handler_context, void *region_context) 1673 { 1674 struct intel_pinctrl *pctrl = region_context; 1675 unsigned long flags; 1676 acpi_status ret = AE_OK; 1677 1678 raw_spin_lock_irqsave(&chv_lock, flags); 1679 1680 if (function == ACPI_WRITE) 1681 chv_pctrl_writel(pctrl, address, *value); 1682 else if (function == ACPI_READ) 1683 *value = chv_pctrl_readl(pctrl, address); 1684 else 1685 ret = AE_BAD_PARAMETER; 1686 1687 raw_spin_unlock_irqrestore(&chv_lock, flags); 1688 1689 return ret; 1690 } 1691 1692 static int chv_pinctrl_probe(struct platform_device *pdev) 1693 { 1694 const struct intel_pinctrl_soc_data *soc_data; 1695 struct intel_community_context *cctx; 1696 struct intel_community *community; 1697 struct device *dev = &pdev->dev; 1698 struct acpi_device *adev = ACPI_COMPANION(dev); 1699 struct intel_pinctrl *pctrl; 1700 acpi_status status; 1701 unsigned int i; 1702 int ret, irq; 1703 1704 soc_data = intel_pinctrl_get_soc_data(pdev); 1705 if (IS_ERR(soc_data)) 1706 return PTR_ERR(soc_data); 1707 1708 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1709 if (!pctrl) 1710 return -ENOMEM; 1711 1712 pctrl->dev = dev; 1713 pctrl->soc = soc_data; 1714 1715 pctrl->ncommunities = pctrl->soc->ncommunities; 1716 pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities, 1717 pctrl->ncommunities * sizeof(*pctrl->communities), 1718 GFP_KERNEL); 1719 if (!pctrl->communities) 1720 return -ENOMEM; 1721 1722 community = &pctrl->communities[0]; 1723 community->regs = devm_platform_ioremap_resource(pdev, 0); 1724 if (IS_ERR(community->regs)) 1725 return PTR_ERR(community->regs); 1726 1727 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF; 1728 1729 #ifdef CONFIG_PM_SLEEP 1730 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins, 1731 sizeof(*pctrl->context.pads), 1732 GFP_KERNEL); 1733 if (!pctrl->context.pads) 1734 return -ENOMEM; 1735 #endif 1736 1737 pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities, 1738 sizeof(*pctrl->context.communities), 1739 GFP_KERNEL); 1740 if (!pctrl->context.communities) 1741 return -ENOMEM; 1742 1743 cctx = &pctrl->context.communities[0]; 1744 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) 1745 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 1746 1747 irq = platform_get_irq(pdev, 0); 1748 if (irq < 0) 1749 return irq; 1750 1751 pctrl->pctldesc = chv_pinctrl_desc; 1752 pctrl->pctldesc.name = dev_name(dev); 1753 pctrl->pctldesc.pins = pctrl->soc->pins; 1754 pctrl->pctldesc.npins = pctrl->soc->npins; 1755 1756 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1757 if (IS_ERR(pctrl->pctldev)) { 1758 dev_err(dev, "failed to register pinctrl driver\n"); 1759 return PTR_ERR(pctrl->pctldev); 1760 } 1761 1762 ret = chv_gpio_probe(pctrl, irq); 1763 if (ret) 1764 return ret; 1765 1766 status = acpi_install_address_space_handler(adev->handle, 1767 community->acpi_space_id, 1768 chv_pinctrl_mmio_access_handler, 1769 NULL, pctrl); 1770 if (ACPI_FAILURE(status)) 1771 dev_err(dev, "failed to install ACPI addr space handler\n"); 1772 1773 platform_set_drvdata(pdev, pctrl); 1774 1775 return 0; 1776 } 1777 1778 static int chv_pinctrl_remove(struct platform_device *pdev) 1779 { 1780 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1781 const struct intel_community *community = &pctrl->communities[0]; 1782 1783 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1784 community->acpi_space_id, 1785 chv_pinctrl_mmio_access_handler); 1786 1787 return 0; 1788 } 1789 1790 #ifdef CONFIG_PM_SLEEP 1791 static int chv_pinctrl_suspend_noirq(struct device *dev) 1792 { 1793 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1794 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1795 unsigned long flags; 1796 int i; 1797 1798 raw_spin_lock_irqsave(&chv_lock, flags); 1799 1800 cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); 1801 1802 for (i = 0; i < pctrl->soc->npins; i++) { 1803 const struct pinctrl_pin_desc *desc; 1804 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1805 1806 desc = &pctrl->soc->pins[i]; 1807 if (chv_pad_locked(pctrl, desc->number)) 1808 continue; 1809 1810 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1811 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE; 1812 1813 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1814 } 1815 1816 raw_spin_unlock_irqrestore(&chv_lock, flags); 1817 1818 return 0; 1819 } 1820 1821 static int chv_pinctrl_resume_noirq(struct device *dev) 1822 { 1823 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1824 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1825 unsigned long flags; 1826 int i; 1827 1828 raw_spin_lock_irqsave(&chv_lock, flags); 1829 1830 /* 1831 * Mask all interrupts before restoring per-pin configuration 1832 * registers because we don't know in which state BIOS left them 1833 * upon exiting suspend. 1834 */ 1835 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000); 1836 1837 for (i = 0; i < pctrl->soc->npins; i++) { 1838 const struct pinctrl_pin_desc *desc; 1839 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1840 u32 val; 1841 1842 desc = &pctrl->soc->pins[i]; 1843 if (chv_pad_locked(pctrl, desc->number)) 1844 continue; 1845 1846 /* Only restore if our saved state differs from the current */ 1847 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1848 val &= ~CHV_PADCTRL0_GPIORXSTATE; 1849 if (ctx->padctrl0 != val) { 1850 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); 1851 dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number, 1852 chv_readl(pctrl, desc->number, CHV_PADCTRL0)); 1853 } 1854 1855 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1856 if (ctx->padctrl1 != val) { 1857 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); 1858 dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number, 1859 chv_readl(pctrl, desc->number, CHV_PADCTRL1)); 1860 } 1861 } 1862 1863 /* 1864 * Now that all pins are restored to known state, we can restore 1865 * the interrupt mask register as well. 1866 */ 1867 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1868 chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); 1869 1870 raw_spin_unlock_irqrestore(&chv_lock, flags); 1871 1872 return 0; 1873 } 1874 #endif 1875 1876 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1877 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1878 chv_pinctrl_resume_noirq) 1879 }; 1880 1881 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1882 { "INT33FF", (kernel_ulong_t)chv_soc_data }, 1883 { } 1884 }; 1885 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1886 1887 static struct platform_driver chv_pinctrl_driver = { 1888 .probe = chv_pinctrl_probe, 1889 .remove = chv_pinctrl_remove, 1890 .driver = { 1891 .name = "cherryview-pinctrl", 1892 .pm = &chv_pinctrl_pm_ops, 1893 .acpi_match_table = chv_pinctrl_acpi_match, 1894 }, 1895 }; 1896 1897 static int __init chv_pinctrl_init(void) 1898 { 1899 return platform_driver_register(&chv_pinctrl_driver); 1900 } 1901 subsys_initcall(chv_pinctrl_init); 1902 1903 static void __exit chv_pinctrl_exit(void) 1904 { 1905 platform_driver_unregister(&chv_pinctrl_driver); 1906 } 1907 module_exit(chv_pinctrl_exit); 1908 1909 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1910 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1911 MODULE_LICENSE("GPL v2"); 1912