1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, 2020 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/dmi.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/types.h> 20 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 26 #include "pinctrl-intel.h" 27 28 #define CHV_INTSTAT 0x300 29 #define CHV_INTMASK 0x380 30 31 #define FAMILY_PAD_REGS_OFF 0x4400 32 #define FAMILY_PAD_REGS_SIZE 0x400 33 #define MAX_FAMILY_PAD_GPIO_NO 15 34 #define GPIO_REGS_SIZE 8 35 36 #define CHV_PADCTRL0 0x000 37 #define CHV_PADCTRL0_INTSEL_SHIFT 28 38 #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) 39 #define CHV_PADCTRL0_TERM_UP BIT(23) 40 #define CHV_PADCTRL0_TERM_SHIFT 20 41 #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) 42 #define CHV_PADCTRL0_TERM_20K 1 43 #define CHV_PADCTRL0_TERM_5K 2 44 #define CHV_PADCTRL0_TERM_1K 4 45 #define CHV_PADCTRL0_PMODE_SHIFT 16 46 #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) 47 #define CHV_PADCTRL0_GPIOEN BIT(15) 48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 49 #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) 50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 51 #define CHV_PADCTRL0_GPIOCFG_GPO 1 52 #define CHV_PADCTRL0_GPIOCFG_GPI 2 53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 56 57 #define CHV_PADCTRL1 0x004 58 #define CHV_PADCTRL1_CFGLOCK BIT(31) 59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 60 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) 61 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) 62 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) 63 #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) 64 #define CHV_PADCTRL1_ODEN BIT(3) 65 #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) 66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 70 71 struct intel_pad_context { 72 u32 padctrl0; 73 u32 padctrl1; 74 }; 75 76 /** 77 * struct chv_pinctrl - CHV pinctrl private structure 78 * @dev: Pointer to the parent device 79 * @pctldesc: Pin controller description 80 * @pctldev: Pointer to the pin controller device 81 * @chip: GPIO chip in this pin controller 82 * @irqchip: IRQ chip in this pin controller 83 * @soc: Community specific pin configuration data 84 * @communities: All communities in this pin controller 85 * @ncommunities: Number of communities in this pin controller 86 * @context: Configuration saved over system sleep 87 * @irq: Our parent irq 88 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) 89 * @saved_intmask: Interrupt mask saved for system sleep 90 * 91 * The first group in @groups is expected to contain all pins that can be 92 * used as GPIOs. 93 */ 94 struct chv_pinctrl { 95 struct device *dev; 96 struct pinctrl_desc pctldesc; 97 struct pinctrl_dev *pctldev; 98 struct gpio_chip chip; 99 struct irq_chip irqchip; 100 const struct intel_pinctrl_soc_data *soc; 101 struct intel_community *communities; 102 size_t ncommunities; 103 struct intel_pinctrl_context context; 104 int irq; 105 106 unsigned int intr_lines[16]; 107 u32 saved_intmask; 108 }; 109 110 #define PINMODE_INVERT_OE BIT(15) 111 112 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 113 114 #define CHV_GPP(start, end) \ 115 { \ 116 .base = (start), \ 117 .size = (end) - (start) + 1, \ 118 } 119 120 #define CHV_COMMUNITY(g, i, a) \ 121 { \ 122 .gpps = (g), \ 123 .ngpps = ARRAY_SIZE(g), \ 124 .nirqs = (i), \ 125 .acpi_space_id = (a), \ 126 } 127 128 static const struct pinctrl_pin_desc southwest_pins[] = { 129 PINCTRL_PIN(0, "FST_SPI_D2"), 130 PINCTRL_PIN(1, "FST_SPI_D0"), 131 PINCTRL_PIN(2, "FST_SPI_CLK"), 132 PINCTRL_PIN(3, "FST_SPI_D3"), 133 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 134 PINCTRL_PIN(5, "FST_SPI_D1"), 135 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 136 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 137 138 PINCTRL_PIN(15, "UART1_RTS_B"), 139 PINCTRL_PIN(16, "UART1_RXD"), 140 PINCTRL_PIN(17, "UART2_RXD"), 141 PINCTRL_PIN(18, "UART1_CTS_B"), 142 PINCTRL_PIN(19, "UART2_RTS_B"), 143 PINCTRL_PIN(20, "UART1_TXD"), 144 PINCTRL_PIN(21, "UART2_TXD"), 145 PINCTRL_PIN(22, "UART2_CTS_B"), 146 147 PINCTRL_PIN(30, "MF_HDA_CLK"), 148 PINCTRL_PIN(31, "MF_HDA_RSTB"), 149 PINCTRL_PIN(32, "MF_HDA_SDIO"), 150 PINCTRL_PIN(33, "MF_HDA_SDO"), 151 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 152 PINCTRL_PIN(35, "MF_HDA_SYNC"), 153 PINCTRL_PIN(36, "MF_HDA_SDI1"), 154 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 155 156 PINCTRL_PIN(45, "I2C5_SDA"), 157 PINCTRL_PIN(46, "I2C4_SDA"), 158 PINCTRL_PIN(47, "I2C6_SDA"), 159 PINCTRL_PIN(48, "I2C5_SCL"), 160 PINCTRL_PIN(49, "I2C_NFC_SDA"), 161 PINCTRL_PIN(50, "I2C4_SCL"), 162 PINCTRL_PIN(51, "I2C6_SCL"), 163 PINCTRL_PIN(52, "I2C_NFC_SCL"), 164 165 PINCTRL_PIN(60, "I2C1_SDA"), 166 PINCTRL_PIN(61, "I2C0_SDA"), 167 PINCTRL_PIN(62, "I2C2_SDA"), 168 PINCTRL_PIN(63, "I2C1_SCL"), 169 PINCTRL_PIN(64, "I2C3_SDA"), 170 PINCTRL_PIN(65, "I2C0_SCL"), 171 PINCTRL_PIN(66, "I2C2_SCL"), 172 PINCTRL_PIN(67, "I2C3_SCL"), 173 174 PINCTRL_PIN(75, "SATA_GP0"), 175 PINCTRL_PIN(76, "SATA_GP1"), 176 PINCTRL_PIN(77, "SATA_LEDN"), 177 PINCTRL_PIN(78, "SATA_GP2"), 178 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 179 PINCTRL_PIN(80, "SATA_GP3"), 180 PINCTRL_PIN(81, "MF_SMB_CLK"), 181 PINCTRL_PIN(82, "MF_SMB_DATA"), 182 183 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 184 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 185 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 186 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 187 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 188 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 189 PINCTRL_PIN(96, "GP_SSP_2_FS"), 190 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 191 }; 192 193 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 194 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 195 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 196 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 197 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 198 static const unsigned southwest_lpe_pins[] = { 199 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 200 }; 201 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 202 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 203 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 204 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 205 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 206 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 207 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 208 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 209 210 /* Some of LPE I2S TXD pins need to have OE inversion set */ 211 static const unsigned int southwest_lpe_altfuncs[] = { 212 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ 213 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ 214 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ 215 }; 216 217 /* 218 * Two spi3 chipselects are available in different mode than the main spi3 219 * functionality, which is using mode 2. 220 */ 221 static const unsigned int southwest_spi3_altfuncs[] = { 222 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ 223 PINMODE(2, 0), /* 82 */ 224 }; 225 226 static const struct intel_pingroup southwest_groups[] = { 227 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), 228 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), 229 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), 230 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), 231 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), 232 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), 233 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), 234 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), 235 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), 236 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), 237 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), 238 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), 239 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), 240 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), 241 }; 242 243 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 244 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 245 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 246 static const char * const southwest_hda_groups[] = { "hda_grp" }; 247 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 248 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 249 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 250 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 251 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 252 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 253 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 254 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 255 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 256 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 257 258 /* 259 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 260 * enabled only as GPIOs. 261 */ 262 static const struct intel_function southwest_functions[] = { 263 FUNCTION("uart0", southwest_uart0_groups), 264 FUNCTION("uart1", southwest_uart1_groups), 265 FUNCTION("uart2", southwest_uart2_groups), 266 FUNCTION("hda", southwest_hda_groups), 267 FUNCTION("lpe", southwest_lpe_groups), 268 FUNCTION("i2c0", southwest_i2c0_groups), 269 FUNCTION("i2c1", southwest_i2c1_groups), 270 FUNCTION("i2c2", southwest_i2c2_groups), 271 FUNCTION("i2c3", southwest_i2c3_groups), 272 FUNCTION("i2c4", southwest_i2c4_groups), 273 FUNCTION("i2c5", southwest_i2c5_groups), 274 FUNCTION("i2c6", southwest_i2c6_groups), 275 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 276 FUNCTION("spi3", southwest_spi3_groups), 277 }; 278 279 static const struct intel_padgroup southwest_gpps[] = { 280 CHV_GPP(0, 7), 281 CHV_GPP(15, 22), 282 CHV_GPP(30, 37), 283 CHV_GPP(45, 52), 284 CHV_GPP(60, 67), 285 CHV_GPP(75, 82), 286 CHV_GPP(90, 97), 287 }; 288 289 /* 290 * Southwest community can generate GPIO interrupts only for the first 8 291 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 292 */ 293 static const struct intel_community southwest_communities[] = { 294 CHV_COMMUNITY(southwest_gpps, 8, 0x91), 295 }; 296 297 static const struct intel_pinctrl_soc_data southwest_soc_data = { 298 .uid = "1", 299 .pins = southwest_pins, 300 .npins = ARRAY_SIZE(southwest_pins), 301 .groups = southwest_groups, 302 .ngroups = ARRAY_SIZE(southwest_groups), 303 .functions = southwest_functions, 304 .nfunctions = ARRAY_SIZE(southwest_functions), 305 .communities = southwest_communities, 306 .ncommunities = ARRAY_SIZE(southwest_communities), 307 }; 308 309 static const struct pinctrl_pin_desc north_pins[] = { 310 PINCTRL_PIN(0, "GPIO_DFX_0"), 311 PINCTRL_PIN(1, "GPIO_DFX_3"), 312 PINCTRL_PIN(2, "GPIO_DFX_7"), 313 PINCTRL_PIN(3, "GPIO_DFX_1"), 314 PINCTRL_PIN(4, "GPIO_DFX_5"), 315 PINCTRL_PIN(5, "GPIO_DFX_4"), 316 PINCTRL_PIN(6, "GPIO_DFX_8"), 317 PINCTRL_PIN(7, "GPIO_DFX_2"), 318 PINCTRL_PIN(8, "GPIO_DFX_6"), 319 320 PINCTRL_PIN(15, "GPIO_SUS0"), 321 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 322 PINCTRL_PIN(17, "GPIO_SUS3"), 323 PINCTRL_PIN(18, "GPIO_SUS7"), 324 PINCTRL_PIN(19, "GPIO_SUS1"), 325 PINCTRL_PIN(20, "GPIO_SUS5"), 326 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 327 PINCTRL_PIN(22, "GPIO_SUS4"), 328 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 329 PINCTRL_PIN(24, "GPIO_SUS2"), 330 PINCTRL_PIN(25, "GPIO_SUS6"), 331 PINCTRL_PIN(26, "CX_PREQ_B"), 332 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 333 334 PINCTRL_PIN(30, "TRST_B"), 335 PINCTRL_PIN(31, "TCK"), 336 PINCTRL_PIN(32, "PROCHOT_B"), 337 PINCTRL_PIN(33, "SVIDO_DATA"), 338 PINCTRL_PIN(34, "TMS"), 339 PINCTRL_PIN(35, "CX_PRDY_B_2"), 340 PINCTRL_PIN(36, "TDO_2"), 341 PINCTRL_PIN(37, "CX_PRDY_B"), 342 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 343 PINCTRL_PIN(39, "TDO"), 344 PINCTRL_PIN(40, "SVIDO_CLK"), 345 PINCTRL_PIN(41, "TDI"), 346 347 PINCTRL_PIN(45, "GP_CAMERASB_05"), 348 PINCTRL_PIN(46, "GP_CAMERASB_02"), 349 PINCTRL_PIN(47, "GP_CAMERASB_08"), 350 PINCTRL_PIN(48, "GP_CAMERASB_00"), 351 PINCTRL_PIN(49, "GP_CAMERASB_06"), 352 PINCTRL_PIN(50, "GP_CAMERASB_10"), 353 PINCTRL_PIN(51, "GP_CAMERASB_03"), 354 PINCTRL_PIN(52, "GP_CAMERASB_09"), 355 PINCTRL_PIN(53, "GP_CAMERASB_01"), 356 PINCTRL_PIN(54, "GP_CAMERASB_07"), 357 PINCTRL_PIN(55, "GP_CAMERASB_11"), 358 PINCTRL_PIN(56, "GP_CAMERASB_04"), 359 360 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 361 PINCTRL_PIN(61, "HV_DDI0_HPD"), 362 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 363 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 364 PINCTRL_PIN(64, "HV_DDI1_HPD"), 365 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 366 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 367 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 368 PINCTRL_PIN(68, "HV_DDI2_HPD"), 369 PINCTRL_PIN(69, "PANEL1_VDDEN"), 370 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 371 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 372 PINCTRL_PIN(72, "PANEL0_VDDEN"), 373 }; 374 375 static const struct intel_padgroup north_gpps[] = { 376 CHV_GPP(0, 8), 377 CHV_GPP(15, 27), 378 CHV_GPP(30, 41), 379 CHV_GPP(45, 56), 380 CHV_GPP(60, 72), 381 }; 382 383 /* 384 * North community can generate GPIO interrupts only for the first 8 385 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 386 */ 387 static const struct intel_community north_communities[] = { 388 CHV_COMMUNITY(north_gpps, 8, 0x92), 389 }; 390 391 static const struct intel_pinctrl_soc_data north_soc_data = { 392 .uid = "2", 393 .pins = north_pins, 394 .npins = ARRAY_SIZE(north_pins), 395 .communities = north_communities, 396 .ncommunities = ARRAY_SIZE(north_communities), 397 }; 398 399 static const struct pinctrl_pin_desc east_pins[] = { 400 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 401 PINCTRL_PIN(1, "PMU_BATLOW_B"), 402 PINCTRL_PIN(2, "SUS_STAT_B"), 403 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 404 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 405 PINCTRL_PIN(5, "PMU_PLTRST_B"), 406 PINCTRL_PIN(6, "PMU_SUSCLK"), 407 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 408 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 409 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 410 PINCTRL_PIN(10, "PMU_WAKE_B"), 411 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 412 413 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 414 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 415 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 416 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 417 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 418 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 419 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 420 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 421 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 422 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 423 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 424 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 425 }; 426 427 static const struct intel_padgroup east_gpps[] = { 428 CHV_GPP(0, 11), 429 CHV_GPP(15, 26), 430 }; 431 432 static const struct intel_community east_communities[] = { 433 CHV_COMMUNITY(east_gpps, 16, 0x93), 434 }; 435 436 static const struct intel_pinctrl_soc_data east_soc_data = { 437 .uid = "3", 438 .pins = east_pins, 439 .npins = ARRAY_SIZE(east_pins), 440 .communities = east_communities, 441 .ncommunities = ARRAY_SIZE(east_communities), 442 }; 443 444 static const struct pinctrl_pin_desc southeast_pins[] = { 445 PINCTRL_PIN(0, "MF_PLT_CLK0"), 446 PINCTRL_PIN(1, "PWM1"), 447 PINCTRL_PIN(2, "MF_PLT_CLK1"), 448 PINCTRL_PIN(3, "MF_PLT_CLK4"), 449 PINCTRL_PIN(4, "MF_PLT_CLK3"), 450 PINCTRL_PIN(5, "PWM0"), 451 PINCTRL_PIN(6, "MF_PLT_CLK5"), 452 PINCTRL_PIN(7, "MF_PLT_CLK2"), 453 454 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 455 PINCTRL_PIN(16, "SDMMC1_CLK"), 456 PINCTRL_PIN(17, "SDMMC1_D0"), 457 PINCTRL_PIN(18, "SDMMC2_D1"), 458 PINCTRL_PIN(19, "SDMMC2_CLK"), 459 PINCTRL_PIN(20, "SDMMC1_D2"), 460 PINCTRL_PIN(21, "SDMMC2_D2"), 461 PINCTRL_PIN(22, "SDMMC2_CMD"), 462 PINCTRL_PIN(23, "SDMMC1_CMD"), 463 PINCTRL_PIN(24, "SDMMC1_D1"), 464 PINCTRL_PIN(25, "SDMMC2_D0"), 465 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 466 467 PINCTRL_PIN(30, "SDMMC3_D1"), 468 PINCTRL_PIN(31, "SDMMC3_CLK"), 469 PINCTRL_PIN(32, "SDMMC3_D3"), 470 PINCTRL_PIN(33, "SDMMC3_D2"), 471 PINCTRL_PIN(34, "SDMMC3_CMD"), 472 PINCTRL_PIN(35, "SDMMC3_D0"), 473 474 PINCTRL_PIN(45, "MF_LPC_AD2"), 475 PINCTRL_PIN(46, "LPC_CLKRUNB"), 476 PINCTRL_PIN(47, "MF_LPC_AD0"), 477 PINCTRL_PIN(48, "LPC_FRAMEB"), 478 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 479 PINCTRL_PIN(50, "MF_LPC_AD3"), 480 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 481 PINCTRL_PIN(52, "MF_LPC_AD1"), 482 483 PINCTRL_PIN(60, "SPI1_MISO"), 484 PINCTRL_PIN(61, "SPI1_CSO_B"), 485 PINCTRL_PIN(62, "SPI1_CLK"), 486 PINCTRL_PIN(63, "MMC1_D6"), 487 PINCTRL_PIN(64, "SPI1_MOSI"), 488 PINCTRL_PIN(65, "MMC1_D5"), 489 PINCTRL_PIN(66, "SPI1_CS1_B"), 490 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 491 PINCTRL_PIN(68, "MMC1_D7"), 492 PINCTRL_PIN(69, "MMC1_RCLK"), 493 494 PINCTRL_PIN(75, "USB_OC1_B"), 495 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 496 PINCTRL_PIN(77, "GPIO_ALERT"), 497 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 498 PINCTRL_PIN(79, "ILB_SERIRQ"), 499 PINCTRL_PIN(80, "USB_OC0_B"), 500 PINCTRL_PIN(81, "SDMMC3_CD_B"), 501 PINCTRL_PIN(82, "SPKR"), 502 PINCTRL_PIN(83, "SUSPWRDNACK"), 503 PINCTRL_PIN(84, "SPARE_PIN"), 504 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 505 }; 506 507 static const unsigned southeast_pwm0_pins[] = { 5 }; 508 static const unsigned southeast_pwm1_pins[] = { 1 }; 509 static const unsigned southeast_sdmmc1_pins[] = { 510 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 511 }; 512 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 513 static const unsigned southeast_sdmmc3_pins[] = { 514 30, 31, 32, 33, 34, 35, 78, 81, 85, 515 }; 516 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 517 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 518 519 static const struct intel_pingroup southeast_groups[] = { 520 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), 521 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), 522 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), 523 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), 524 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), 525 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), 526 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), 527 }; 528 529 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 530 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 531 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 532 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 533 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 534 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 535 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 536 537 static const struct intel_function southeast_functions[] = { 538 FUNCTION("pwm0", southeast_pwm0_groups), 539 FUNCTION("pwm1", southeast_pwm1_groups), 540 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 541 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 542 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 543 FUNCTION("spi1", southeast_spi1_groups), 544 FUNCTION("spi2", southeast_spi2_groups), 545 }; 546 547 static const struct intel_padgroup southeast_gpps[] = { 548 CHV_GPP(0, 7), 549 CHV_GPP(15, 26), 550 CHV_GPP(30, 35), 551 CHV_GPP(45, 52), 552 CHV_GPP(60, 69), 553 CHV_GPP(75, 85), 554 }; 555 556 static const struct intel_community southeast_communities[] = { 557 CHV_COMMUNITY(southeast_gpps, 16, 0x94), 558 }; 559 560 static const struct intel_pinctrl_soc_data southeast_soc_data = { 561 .uid = "4", 562 .pins = southeast_pins, 563 .npins = ARRAY_SIZE(southeast_pins), 564 .groups = southeast_groups, 565 .ngroups = ARRAY_SIZE(southeast_groups), 566 .functions = southeast_functions, 567 .nfunctions = ARRAY_SIZE(southeast_functions), 568 .communities = southeast_communities, 569 .ncommunities = ARRAY_SIZE(southeast_communities), 570 }; 571 572 static const struct intel_pinctrl_soc_data *chv_soc_data[] = { 573 &southwest_soc_data, 574 &north_soc_data, 575 &east_soc_data, 576 &southeast_soc_data, 577 NULL 578 }; 579 580 /* 581 * Lock to serialize register accesses 582 * 583 * Due to a silicon issue, a shared lock must be used to prevent 584 * concurrent accesses across the 4 GPIO controllers. 585 * 586 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 587 * errata #CHT34, for further information. 588 */ 589 static DEFINE_RAW_SPINLOCK(chv_lock); 590 591 static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset) 592 { 593 const struct intel_community *community = &pctrl->communities[0]; 594 595 return readl(community->regs + offset); 596 } 597 598 static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value) 599 { 600 const struct intel_community *community = &pctrl->communities[0]; 601 void __iomem *reg = community->regs + offset; 602 603 /* Write and simple read back to confirm the bus transferring done */ 604 writel(value, reg); 605 readl(reg); 606 } 607 608 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset, 609 unsigned int reg) 610 { 611 const struct intel_community *community = &pctrl->communities[0]; 612 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 613 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 614 615 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; 616 617 return community->pad_regs + offset + reg; 618 } 619 620 static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset) 621 { 622 return readl(chv_padreg(pctrl, pin, offset)); 623 } 624 625 static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) 626 { 627 void __iomem *reg = chv_padreg(pctrl, pin, offset); 628 629 /* Write and simple read back to confirm the bus transferring done */ 630 writel(value, reg); 631 readl(reg); 632 } 633 634 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 635 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset) 636 { 637 return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; 638 } 639 640 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 641 { 642 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 643 644 return pctrl->soc->ngroups; 645 } 646 647 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 648 unsigned int group) 649 { 650 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 651 652 return pctrl->soc->groups[group].name; 653 } 654 655 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 656 const unsigned int **pins, unsigned int *npins) 657 { 658 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 659 660 *pins = pctrl->soc->groups[group].pins; 661 *npins = pctrl->soc->groups[group].npins; 662 return 0; 663 } 664 665 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 666 unsigned int offset) 667 { 668 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 669 unsigned long flags; 670 u32 ctrl0, ctrl1; 671 bool locked; 672 673 raw_spin_lock_irqsave(&chv_lock, flags); 674 675 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 676 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); 677 locked = chv_pad_locked(pctrl, offset); 678 679 raw_spin_unlock_irqrestore(&chv_lock, flags); 680 681 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 682 seq_puts(s, "GPIO "); 683 } else { 684 u32 mode; 685 686 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 687 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 688 689 seq_printf(s, "mode %d ", mode); 690 } 691 692 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 693 694 if (locked) 695 seq_puts(s, " [LOCKED]"); 696 } 697 698 static const struct pinctrl_ops chv_pinctrl_ops = { 699 .get_groups_count = chv_get_groups_count, 700 .get_group_name = chv_get_group_name, 701 .get_group_pins = chv_get_group_pins, 702 .pin_dbg_show = chv_pin_dbg_show, 703 }; 704 705 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 706 { 707 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 708 709 return pctrl->soc->nfunctions; 710 } 711 712 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 713 unsigned int function) 714 { 715 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 716 717 return pctrl->soc->functions[function].name; 718 } 719 720 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 721 unsigned int function, 722 const char * const **groups, 723 unsigned int * const ngroups) 724 { 725 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 726 727 *groups = pctrl->soc->functions[function].groups; 728 *ngroups = pctrl->soc->functions[function].ngroups; 729 return 0; 730 } 731 732 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 733 unsigned int function, unsigned int group) 734 { 735 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 736 const struct intel_pingroup *grp; 737 unsigned long flags; 738 int i; 739 740 grp = &pctrl->soc->groups[group]; 741 742 raw_spin_lock_irqsave(&chv_lock, flags); 743 744 /* Check first that the pad is not locked */ 745 for (i = 0; i < grp->npins; i++) { 746 if (chv_pad_locked(pctrl, grp->pins[i])) { 747 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 748 grp->pins[i]); 749 raw_spin_unlock_irqrestore(&chv_lock, flags); 750 return -EBUSY; 751 } 752 } 753 754 for (i = 0; i < grp->npins; i++) { 755 int pin = grp->pins[i]; 756 unsigned int mode; 757 bool invert_oe; 758 u32 value; 759 760 /* Check if there is pin-specific config */ 761 if (grp->modes) 762 mode = grp->modes[i]; 763 else 764 mode = grp->mode; 765 766 /* Extract OE inversion */ 767 invert_oe = mode & PINMODE_INVERT_OE; 768 mode &= ~PINMODE_INVERT_OE; 769 770 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 771 /* Disable GPIO mode */ 772 value &= ~CHV_PADCTRL0_GPIOEN; 773 /* Set to desired mode */ 774 value &= ~CHV_PADCTRL0_PMODE_MASK; 775 value |= mode << CHV_PADCTRL0_PMODE_SHIFT; 776 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 777 778 /* Update for invert_oe */ 779 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK; 780 if (invert_oe) 781 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 782 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 783 784 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 785 pin, mode, invert_oe ? "" : "not "); 786 } 787 788 raw_spin_unlock_irqrestore(&chv_lock, flags); 789 790 return 0; 791 } 792 793 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl, 794 unsigned int offset) 795 { 796 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; 797 u32 value; 798 799 /* 800 * One some devices the GPIO should output the inverted value from what 801 * device-drivers / ACPI code expects (inverted external buffer?). The 802 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, 803 * preserve this flag if the pin is already setup as GPIO. 804 */ 805 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 806 if (value & CHV_PADCTRL0_GPIOEN) 807 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; 808 809 value = chv_readl(pctrl, offset, CHV_PADCTRL1); 810 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 811 value &= ~invrxtx_mask; 812 chv_writel(pctrl, offset, CHV_PADCTRL1, value); 813 } 814 815 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 816 struct pinctrl_gpio_range *range, 817 unsigned int offset) 818 { 819 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 820 unsigned long flags; 821 u32 value; 822 823 raw_spin_lock_irqsave(&chv_lock, flags); 824 825 if (chv_pad_locked(pctrl, offset)) { 826 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 827 if (!(value & CHV_PADCTRL0_GPIOEN)) { 828 /* Locked so cannot enable */ 829 raw_spin_unlock_irqrestore(&chv_lock, flags); 830 return -EBUSY; 831 } 832 } else { 833 int i; 834 835 /* Reset the interrupt mapping */ 836 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 837 if (pctrl->intr_lines[i] == offset) { 838 pctrl->intr_lines[i] = 0; 839 break; 840 } 841 } 842 843 /* Disable interrupt generation */ 844 chv_gpio_clear_triggering(pctrl, offset); 845 846 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 847 848 /* 849 * If the pin is in HiZ mode (both TX and RX buffers are 850 * disabled) we turn it to be input now. 851 */ 852 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 853 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 854 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 855 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 856 } 857 858 /* Switch to a GPIO mode */ 859 value |= CHV_PADCTRL0_GPIOEN; 860 chv_writel(pctrl, offset, CHV_PADCTRL0, value); 861 } 862 863 raw_spin_unlock_irqrestore(&chv_lock, flags); 864 865 return 0; 866 } 867 868 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 869 struct pinctrl_gpio_range *range, 870 unsigned int offset) 871 { 872 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 873 unsigned long flags; 874 875 raw_spin_lock_irqsave(&chv_lock, flags); 876 877 if (!chv_pad_locked(pctrl, offset)) 878 chv_gpio_clear_triggering(pctrl, offset); 879 880 raw_spin_unlock_irqrestore(&chv_lock, flags); 881 } 882 883 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 884 struct pinctrl_gpio_range *range, 885 unsigned int offset, bool input) 886 { 887 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 888 unsigned long flags; 889 u32 ctrl0; 890 891 raw_spin_lock_irqsave(&chv_lock, flags); 892 893 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; 894 if (input) 895 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 896 else 897 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 898 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 899 900 raw_spin_unlock_irqrestore(&chv_lock, flags); 901 902 return 0; 903 } 904 905 static const struct pinmux_ops chv_pinmux_ops = { 906 .get_functions_count = chv_get_functions_count, 907 .get_function_name = chv_get_function_name, 908 .get_function_groups = chv_get_function_groups, 909 .set_mux = chv_pinmux_set_mux, 910 .gpio_request_enable = chv_gpio_request_enable, 911 .gpio_disable_free = chv_gpio_disable_free, 912 .gpio_set_direction = chv_gpio_set_direction, 913 }; 914 915 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 916 unsigned long *config) 917 { 918 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 919 enum pin_config_param param = pinconf_to_config_param(*config); 920 unsigned long flags; 921 u32 ctrl0, ctrl1; 922 u16 arg = 0; 923 u32 term; 924 925 raw_spin_lock_irqsave(&chv_lock, flags); 926 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 927 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 928 raw_spin_unlock_irqrestore(&chv_lock, flags); 929 930 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 931 932 switch (param) { 933 case PIN_CONFIG_BIAS_DISABLE: 934 if (term) 935 return -EINVAL; 936 break; 937 938 case PIN_CONFIG_BIAS_PULL_UP: 939 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 940 return -EINVAL; 941 942 switch (term) { 943 case CHV_PADCTRL0_TERM_20K: 944 arg = 20000; 945 break; 946 case CHV_PADCTRL0_TERM_5K: 947 arg = 5000; 948 break; 949 case CHV_PADCTRL0_TERM_1K: 950 arg = 1000; 951 break; 952 } 953 954 break; 955 956 case PIN_CONFIG_BIAS_PULL_DOWN: 957 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 958 return -EINVAL; 959 960 switch (term) { 961 case CHV_PADCTRL0_TERM_20K: 962 arg = 20000; 963 break; 964 case CHV_PADCTRL0_TERM_5K: 965 arg = 5000; 966 break; 967 } 968 969 break; 970 971 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 972 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 973 return -EINVAL; 974 break; 975 976 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 977 u32 cfg; 978 979 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 980 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 981 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 982 return -EINVAL; 983 984 break; 985 } 986 987 default: 988 return -ENOTSUPP; 989 } 990 991 *config = pinconf_to_config_packed(param, arg); 992 return 0; 993 } 994 995 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin, 996 enum pin_config_param param, u32 arg) 997 { 998 unsigned long flags; 999 u32 ctrl0, pull; 1000 1001 raw_spin_lock_irqsave(&chv_lock, flags); 1002 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 1003 1004 switch (param) { 1005 case PIN_CONFIG_BIAS_DISABLE: 1006 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1007 break; 1008 1009 case PIN_CONFIG_BIAS_PULL_UP: 1010 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1011 1012 switch (arg) { 1013 case 1000: 1014 /* For 1k there is only pull up */ 1015 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1016 break; 1017 case 5000: 1018 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1019 break; 1020 case 20000: 1021 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1022 break; 1023 default: 1024 raw_spin_unlock_irqrestore(&chv_lock, flags); 1025 return -EINVAL; 1026 } 1027 1028 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1029 break; 1030 1031 case PIN_CONFIG_BIAS_PULL_DOWN: 1032 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1033 1034 switch (arg) { 1035 case 5000: 1036 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1037 break; 1038 case 20000: 1039 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1040 break; 1041 default: 1042 raw_spin_unlock_irqrestore(&chv_lock, flags); 1043 return -EINVAL; 1044 } 1045 1046 ctrl0 |= pull; 1047 break; 1048 1049 default: 1050 raw_spin_unlock_irqrestore(&chv_lock, flags); 1051 return -EINVAL; 1052 } 1053 1054 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); 1055 raw_spin_unlock_irqrestore(&chv_lock, flags); 1056 1057 return 0; 1058 } 1059 1060 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1061 bool enable) 1062 { 1063 unsigned long flags; 1064 u32 ctrl1; 1065 1066 raw_spin_lock_irqsave(&chv_lock, flags); 1067 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 1068 1069 if (enable) 1070 ctrl1 |= CHV_PADCTRL1_ODEN; 1071 else 1072 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1073 1074 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); 1075 raw_spin_unlock_irqrestore(&chv_lock, flags); 1076 1077 return 0; 1078 } 1079 1080 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1081 unsigned long *configs, unsigned int nconfigs) 1082 { 1083 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1084 enum pin_config_param param; 1085 int i, ret; 1086 u32 arg; 1087 1088 if (chv_pad_locked(pctrl, pin)) 1089 return -EBUSY; 1090 1091 for (i = 0; i < nconfigs; i++) { 1092 param = pinconf_to_config_param(configs[i]); 1093 arg = pinconf_to_config_argument(configs[i]); 1094 1095 switch (param) { 1096 case PIN_CONFIG_BIAS_DISABLE: 1097 case PIN_CONFIG_BIAS_PULL_UP: 1098 case PIN_CONFIG_BIAS_PULL_DOWN: 1099 ret = chv_config_set_pull(pctrl, pin, param, arg); 1100 if (ret) 1101 return ret; 1102 break; 1103 1104 case PIN_CONFIG_DRIVE_PUSH_PULL: 1105 ret = chv_config_set_oden(pctrl, pin, false); 1106 if (ret) 1107 return ret; 1108 break; 1109 1110 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1111 ret = chv_config_set_oden(pctrl, pin, true); 1112 if (ret) 1113 return ret; 1114 break; 1115 1116 default: 1117 return -ENOTSUPP; 1118 } 1119 1120 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1121 param, arg); 1122 } 1123 1124 return 0; 1125 } 1126 1127 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1128 unsigned int group, 1129 unsigned long *config) 1130 { 1131 const unsigned int *pins; 1132 unsigned int npins; 1133 int ret; 1134 1135 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1136 if (ret) 1137 return ret; 1138 1139 ret = chv_config_get(pctldev, pins[0], config); 1140 if (ret) 1141 return ret; 1142 1143 return 0; 1144 } 1145 1146 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1147 unsigned int group, unsigned long *configs, 1148 unsigned int num_configs) 1149 { 1150 const unsigned int *pins; 1151 unsigned int npins; 1152 int i, ret; 1153 1154 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1155 if (ret) 1156 return ret; 1157 1158 for (i = 0; i < npins; i++) { 1159 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1160 if (ret) 1161 return ret; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static const struct pinconf_ops chv_pinconf_ops = { 1168 .is_generic = true, 1169 .pin_config_set = chv_config_set, 1170 .pin_config_get = chv_config_get, 1171 .pin_config_group_get = chv_config_group_get, 1172 .pin_config_group_set = chv_config_group_set, 1173 }; 1174 1175 static struct pinctrl_desc chv_pinctrl_desc = { 1176 .pctlops = &chv_pinctrl_ops, 1177 .pmxops = &chv_pinmux_ops, 1178 .confops = &chv_pinconf_ops, 1179 .owner = THIS_MODULE, 1180 }; 1181 1182 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1183 { 1184 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1185 unsigned long flags; 1186 u32 ctrl0, cfg; 1187 1188 raw_spin_lock_irqsave(&chv_lock, flags); 1189 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1190 raw_spin_unlock_irqrestore(&chv_lock, flags); 1191 1192 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1193 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1194 1195 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1196 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1197 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1198 } 1199 1200 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1201 { 1202 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1203 unsigned long flags; 1204 u32 ctrl0; 1205 1206 raw_spin_lock_irqsave(&chv_lock, flags); 1207 1208 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1209 1210 if (value) 1211 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1212 else 1213 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1214 1215 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 1216 1217 raw_spin_unlock_irqrestore(&chv_lock, flags); 1218 } 1219 1220 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1221 { 1222 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1223 u32 ctrl0, direction; 1224 unsigned long flags; 1225 1226 raw_spin_lock_irqsave(&chv_lock, flags); 1227 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1228 raw_spin_unlock_irqrestore(&chv_lock, flags); 1229 1230 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1231 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1232 1233 if (direction == CHV_PADCTRL0_GPIOCFG_GPO) 1234 return GPIO_LINE_DIRECTION_OUT; 1235 1236 return GPIO_LINE_DIRECTION_IN; 1237 } 1238 1239 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1240 { 1241 return pinctrl_gpio_direction_input(chip->base + offset); 1242 } 1243 1244 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1245 int value) 1246 { 1247 chv_gpio_set(chip, offset, value); 1248 return pinctrl_gpio_direction_output(chip->base + offset); 1249 } 1250 1251 static const struct gpio_chip chv_gpio_chip = { 1252 .owner = THIS_MODULE, 1253 .request = gpiochip_generic_request, 1254 .free = gpiochip_generic_free, 1255 .get_direction = chv_gpio_get_direction, 1256 .direction_input = chv_gpio_direction_input, 1257 .direction_output = chv_gpio_direction_output, 1258 .get = chv_gpio_get, 1259 .set = chv_gpio_set, 1260 }; 1261 1262 static void chv_gpio_irq_ack(struct irq_data *d) 1263 { 1264 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1265 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1266 int pin = irqd_to_hwirq(d); 1267 u32 intr_line; 1268 1269 raw_spin_lock(&chv_lock); 1270 1271 intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0); 1272 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1273 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1274 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); 1275 1276 raw_spin_unlock(&chv_lock); 1277 } 1278 1279 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1280 { 1281 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1282 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1283 int pin = irqd_to_hwirq(d); 1284 u32 value, intr_line; 1285 unsigned long flags; 1286 1287 raw_spin_lock_irqsave(&chv_lock, flags); 1288 1289 intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0); 1290 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1291 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1292 1293 value = chv_pctrl_readl(pctrl, CHV_INTMASK); 1294 if (mask) 1295 value &= ~BIT(intr_line); 1296 else 1297 value |= BIT(intr_line); 1298 chv_pctrl_writel(pctrl, CHV_INTMASK, value); 1299 1300 raw_spin_unlock_irqrestore(&chv_lock, flags); 1301 } 1302 1303 static void chv_gpio_irq_mask(struct irq_data *d) 1304 { 1305 chv_gpio_irq_mask_unmask(d, true); 1306 } 1307 1308 static void chv_gpio_irq_unmask(struct irq_data *d) 1309 { 1310 chv_gpio_irq_mask_unmask(d, false); 1311 } 1312 1313 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1314 { 1315 /* 1316 * Check if the interrupt has been requested with 0 as triggering 1317 * type. In that case it is assumed that the current values 1318 * programmed to the hardware are used (e.g BIOS configured 1319 * defaults). 1320 * 1321 * In that case ->irq_set_type() will never be called so we need to 1322 * read back the values from hardware now, set correct flow handler 1323 * and update mappings before the interrupt is being used. 1324 */ 1325 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1326 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1327 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1328 unsigned int pin = irqd_to_hwirq(d); 1329 irq_flow_handler_t handler; 1330 unsigned long flags; 1331 u32 intsel, value; 1332 1333 raw_spin_lock_irqsave(&chv_lock, flags); 1334 intsel = chv_readl(pctrl, pin, CHV_PADCTRL0); 1335 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1336 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1337 1338 value = chv_readl(pctrl, pin, CHV_PADCTRL1); 1339 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1340 handler = handle_level_irq; 1341 else 1342 handler = handle_edge_irq; 1343 1344 if (!pctrl->intr_lines[intsel]) { 1345 irq_set_handler_locked(d, handler); 1346 pctrl->intr_lines[intsel] = pin; 1347 } 1348 raw_spin_unlock_irqrestore(&chv_lock, flags); 1349 } 1350 1351 chv_gpio_irq_unmask(d); 1352 return 0; 1353 } 1354 1355 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1356 { 1357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1358 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1359 unsigned int pin = irqd_to_hwirq(d); 1360 unsigned long flags; 1361 u32 value; 1362 1363 raw_spin_lock_irqsave(&chv_lock, flags); 1364 1365 /* 1366 * Pins which can be used as shared interrupt are configured in 1367 * BIOS. Driver trusts BIOS configurations and assigns different 1368 * handler according to the irq type. 1369 * 1370 * Driver needs to save the mapping between each pin and 1371 * its interrupt line. 1372 * 1. If the pin cfg is locked in BIOS: 1373 * Trust BIOS has programmed IntWakeCfg bits correctly, 1374 * driver just needs to save the mapping. 1375 * 2. If the pin cfg is not locked in BIOS: 1376 * Driver programs the IntWakeCfg bits and save the mapping. 1377 */ 1378 if (!chv_pad_locked(pctrl, pin)) { 1379 value = chv_readl(pctrl, pin, CHV_PADCTRL1); 1380 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1381 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1382 1383 if (type & IRQ_TYPE_EDGE_BOTH) { 1384 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1385 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1386 else if (type & IRQ_TYPE_EDGE_RISING) 1387 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1388 else if (type & IRQ_TYPE_EDGE_FALLING) 1389 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1390 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1391 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1392 if (type & IRQ_TYPE_LEVEL_LOW) 1393 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1394 } 1395 1396 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 1397 } 1398 1399 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 1400 value &= CHV_PADCTRL0_INTSEL_MASK; 1401 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1402 1403 pctrl->intr_lines[value] = pin; 1404 1405 if (type & IRQ_TYPE_EDGE_BOTH) 1406 irq_set_handler_locked(d, handle_edge_irq); 1407 else if (type & IRQ_TYPE_LEVEL_MASK) 1408 irq_set_handler_locked(d, handle_level_irq); 1409 1410 raw_spin_unlock_irqrestore(&chv_lock, flags); 1411 1412 return 0; 1413 } 1414 1415 static void chv_gpio_irq_handler(struct irq_desc *desc) 1416 { 1417 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1418 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1419 const struct intel_community *community = &pctrl->communities[0]; 1420 struct irq_chip *chip = irq_desc_get_chip(desc); 1421 unsigned long pending; 1422 unsigned long flags; 1423 u32 intr_line; 1424 1425 chained_irq_enter(chip, desc); 1426 1427 raw_spin_lock_irqsave(&chv_lock, flags); 1428 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); 1429 raw_spin_unlock_irqrestore(&chv_lock, flags); 1430 1431 for_each_set_bit(intr_line, &pending, community->nirqs) { 1432 unsigned int irq, offset; 1433 1434 offset = pctrl->intr_lines[intr_line]; 1435 irq = irq_find_mapping(gc->irq.domain, offset); 1436 generic_handle_irq(irq); 1437 } 1438 1439 chained_irq_exit(chip, desc); 1440 } 1441 1442 /* 1443 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1444 * tables. Since we leave GPIOs that are not capable of generating 1445 * interrupts out of the irqdomain the numbering will be different and 1446 * cause devices using the hardcoded IRQ numbers fail. In order not to 1447 * break such machines we will only mask pins from irqdomain if the machine 1448 * is not listed below. 1449 */ 1450 static const struct dmi_system_id chv_no_valid_mask[] = { 1451 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1452 { 1453 .ident = "Intel_Strago based Chromebooks (All models)", 1454 .matches = { 1455 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1456 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1457 }, 1458 }, 1459 { 1460 .ident = "HP Chromebook 11 G5 (Setzer)", 1461 .matches = { 1462 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1463 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1464 }, 1465 }, 1466 { 1467 .ident = "Acer Chromebook R11 (Cyan)", 1468 .matches = { 1469 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1470 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1471 }, 1472 }, 1473 { 1474 .ident = "Samsung Chromebook 3 (Celes)", 1475 .matches = { 1476 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1477 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1478 }, 1479 }, 1480 {} 1481 }; 1482 1483 static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1484 unsigned long *valid_mask, 1485 unsigned int ngpios) 1486 { 1487 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1488 const struct intel_community *community = &pctrl->communities[0]; 1489 int i; 1490 1491 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1492 for (i = 0; i < pctrl->soc->npins; i++) { 1493 const struct pinctrl_pin_desc *desc; 1494 u32 intsel; 1495 1496 desc = &pctrl->soc->pins[i]; 1497 1498 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1499 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1500 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1501 1502 if (intsel >= community->nirqs) 1503 clear_bit(desc->number, valid_mask); 1504 } 1505 } 1506 1507 static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 1508 { 1509 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1510 const struct intel_community *community = &pctrl->communities[0]; 1511 1512 /* 1513 * The same set of machines in chv_no_valid_mask[] have incorrectly 1514 * configured GPIOs that generate spurious interrupts so we use 1515 * this same list to apply another quirk for them. 1516 * 1517 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1518 */ 1519 if (!pctrl->chip.irq.init_valid_mask) { 1520 /* 1521 * Mask all interrupts the community is able to generate 1522 * but leave the ones that can only generate GPEs unmasked. 1523 */ 1524 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs)); 1525 } 1526 1527 /* Clear all interrupts */ 1528 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1529 1530 return 0; 1531 } 1532 1533 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) 1534 { 1535 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1536 const struct intel_community *community = &pctrl->communities[0]; 1537 const struct intel_padgroup *gpp; 1538 int ret, i; 1539 1540 for (i = 0; i < community->ngpps; i++) { 1541 gpp = &community->gpps[i]; 1542 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), 1543 gpp->base, gpp->base, 1544 gpp->size); 1545 if (ret) { 1546 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1547 return ret; 1548 } 1549 } 1550 1551 return 0; 1552 } 1553 1554 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1555 { 1556 const struct intel_community *community = &pctrl->communities[0]; 1557 const struct intel_padgroup *gpp; 1558 struct gpio_chip *chip = &pctrl->chip; 1559 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1560 int ret, i, irq_base; 1561 1562 *chip = chv_gpio_chip; 1563 1564 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1565 chip->label = dev_name(pctrl->dev); 1566 chip->add_pin_ranges = chv_gpio_add_pin_ranges; 1567 chip->parent = pctrl->dev; 1568 chip->base = -1; 1569 1570 pctrl->irq = irq; 1571 pctrl->irqchip.name = "chv-gpio"; 1572 pctrl->irqchip.irq_startup = chv_gpio_irq_startup; 1573 pctrl->irqchip.irq_ack = chv_gpio_irq_ack; 1574 pctrl->irqchip.irq_mask = chv_gpio_irq_mask; 1575 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; 1576 pctrl->irqchip.irq_set_type = chv_gpio_irq_type; 1577 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; 1578 1579 chip->irq.chip = &pctrl->irqchip; 1580 chip->irq.init_hw = chv_gpio_irq_init_hw; 1581 chip->irq.parent_handler = chv_gpio_irq_handler; 1582 chip->irq.num_parents = 1; 1583 chip->irq.parents = &pctrl->irq; 1584 chip->irq.default_type = IRQ_TYPE_NONE; 1585 chip->irq.handler = handle_bad_irq; 1586 if (need_valid_mask) { 1587 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1588 } else { 1589 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 1590 pctrl->soc->npins, NUMA_NO_NODE); 1591 if (irq_base < 0) { 1592 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1593 return irq_base; 1594 } 1595 } 1596 1597 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1598 if (ret) { 1599 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1600 return ret; 1601 } 1602 1603 if (!need_valid_mask) { 1604 for (i = 0; i < community->ngpps; i++) { 1605 gpp = &community->gpps[i]; 1606 1607 irq_domain_associate_many(chip->irq.domain, irq_base, 1608 gpp->base, gpp->size); 1609 irq_base += gpp->size; 1610 } 1611 } 1612 1613 return 0; 1614 } 1615 1616 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1617 acpi_physical_address address, u32 bits, u64 *value, 1618 void *handler_context, void *region_context) 1619 { 1620 struct chv_pinctrl *pctrl = region_context; 1621 unsigned long flags; 1622 acpi_status ret = AE_OK; 1623 1624 raw_spin_lock_irqsave(&chv_lock, flags); 1625 1626 if (function == ACPI_WRITE) 1627 chv_pctrl_writel(pctrl, address, *value); 1628 else if (function == ACPI_READ) 1629 *value = chv_pctrl_readl(pctrl, address); 1630 else 1631 ret = AE_BAD_PARAMETER; 1632 1633 raw_spin_unlock_irqrestore(&chv_lock, flags); 1634 1635 return ret; 1636 } 1637 1638 static int chv_pinctrl_probe(struct platform_device *pdev) 1639 { 1640 const struct intel_pinctrl_soc_data *soc_data = NULL; 1641 const struct intel_pinctrl_soc_data **soc_table; 1642 struct intel_community *community; 1643 struct device *dev = &pdev->dev; 1644 struct chv_pinctrl *pctrl; 1645 struct acpi_device *adev; 1646 acpi_status status; 1647 int ret, irq, i; 1648 1649 adev = ACPI_COMPANION(&pdev->dev); 1650 if (!adev) 1651 return -ENODEV; 1652 1653 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev); 1654 for (i = 0; soc_table[i]; i++) { 1655 if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) { 1656 soc_data = soc_table[i]; 1657 break; 1658 } 1659 } 1660 if (!soc_data) 1661 return -ENODEV; 1662 1663 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1664 if (!pctrl) 1665 return -ENOMEM; 1666 1667 pctrl->dev = &pdev->dev; 1668 pctrl->soc = soc_data; 1669 1670 pctrl->ncommunities = pctrl->soc->ncommunities; 1671 pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities, 1672 pctrl->ncommunities * sizeof(*pctrl->communities), 1673 GFP_KERNEL); 1674 if (!pctrl->communities) 1675 return -ENOMEM; 1676 1677 community = &pctrl->communities[0]; 1678 community->regs = devm_platform_ioremap_resource(pdev, 0); 1679 if (IS_ERR(community->regs)) 1680 return PTR_ERR(community->regs); 1681 1682 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF; 1683 1684 #ifdef CONFIG_PM_SLEEP 1685 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins, 1686 sizeof(*pctrl->context.pads), 1687 GFP_KERNEL); 1688 if (!pctrl->context.pads) 1689 return -ENOMEM; 1690 #endif 1691 1692 irq = platform_get_irq(pdev, 0); 1693 if (irq < 0) 1694 return irq; 1695 1696 pctrl->pctldesc = chv_pinctrl_desc; 1697 pctrl->pctldesc.name = dev_name(&pdev->dev); 1698 pctrl->pctldesc.pins = pctrl->soc->pins; 1699 pctrl->pctldesc.npins = pctrl->soc->npins; 1700 1701 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1702 pctrl); 1703 if (IS_ERR(pctrl->pctldev)) { 1704 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1705 return PTR_ERR(pctrl->pctldev); 1706 } 1707 1708 ret = chv_gpio_probe(pctrl, irq); 1709 if (ret) 1710 return ret; 1711 1712 status = acpi_install_address_space_handler(adev->handle, 1713 community->acpi_space_id, 1714 chv_pinctrl_mmio_access_handler, 1715 NULL, pctrl); 1716 if (ACPI_FAILURE(status)) 1717 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1718 1719 platform_set_drvdata(pdev, pctrl); 1720 1721 return 0; 1722 } 1723 1724 static int chv_pinctrl_remove(struct platform_device *pdev) 1725 { 1726 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1727 const struct intel_community *community = &pctrl->communities[0]; 1728 1729 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1730 community->acpi_space_id, 1731 chv_pinctrl_mmio_access_handler); 1732 1733 return 0; 1734 } 1735 1736 #ifdef CONFIG_PM_SLEEP 1737 static int chv_pinctrl_suspend_noirq(struct device *dev) 1738 { 1739 struct chv_pinctrl *pctrl = dev_get_drvdata(dev); 1740 unsigned long flags; 1741 int i; 1742 1743 raw_spin_lock_irqsave(&chv_lock, flags); 1744 1745 pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); 1746 1747 for (i = 0; i < pctrl->soc->npins; i++) { 1748 const struct pinctrl_pin_desc *desc; 1749 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1750 1751 desc = &pctrl->soc->pins[i]; 1752 if (chv_pad_locked(pctrl, desc->number)) 1753 continue; 1754 1755 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1756 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE; 1757 1758 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1759 } 1760 1761 raw_spin_unlock_irqrestore(&chv_lock, flags); 1762 1763 return 0; 1764 } 1765 1766 static int chv_pinctrl_resume_noirq(struct device *dev) 1767 { 1768 struct chv_pinctrl *pctrl = dev_get_drvdata(dev); 1769 unsigned long flags; 1770 int i; 1771 1772 raw_spin_lock_irqsave(&chv_lock, flags); 1773 1774 /* 1775 * Mask all interrupts before restoring per-pin configuration 1776 * registers because we don't know in which state BIOS left them 1777 * upon exiting suspend. 1778 */ 1779 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000); 1780 1781 for (i = 0; i < pctrl->soc->npins; i++) { 1782 const struct pinctrl_pin_desc *desc; 1783 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1784 u32 val; 1785 1786 desc = &pctrl->soc->pins[i]; 1787 if (chv_pad_locked(pctrl, desc->number)) 1788 continue; 1789 1790 /* Only restore if our saved state differs from the current */ 1791 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1792 val &= ~CHV_PADCTRL0_GPIORXSTATE; 1793 if (ctx->padctrl0 != val) { 1794 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); 1795 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1796 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0)); 1797 } 1798 1799 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1800 if (ctx->padctrl1 != val) { 1801 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); 1802 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1803 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1)); 1804 } 1805 } 1806 1807 /* 1808 * Now that all pins are restored to known state, we can restore 1809 * the interrupt mask register as well. 1810 */ 1811 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1812 chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask); 1813 1814 raw_spin_unlock_irqrestore(&chv_lock, flags); 1815 1816 return 0; 1817 } 1818 #endif 1819 1820 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1821 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1822 chv_pinctrl_resume_noirq) 1823 }; 1824 1825 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1826 { "INT33FF", (kernel_ulong_t)chv_soc_data }, 1827 { } 1828 }; 1829 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1830 1831 static struct platform_driver chv_pinctrl_driver = { 1832 .probe = chv_pinctrl_probe, 1833 .remove = chv_pinctrl_remove, 1834 .driver = { 1835 .name = "cherryview-pinctrl", 1836 .pm = &chv_pinctrl_pm_ops, 1837 .acpi_match_table = chv_pinctrl_acpi_match, 1838 }, 1839 }; 1840 1841 static int __init chv_pinctrl_init(void) 1842 { 1843 return platform_driver_register(&chv_pinctrl_driver); 1844 } 1845 subsys_initcall(chv_pinctrl_init); 1846 1847 static void __exit chv_pinctrl_exit(void) 1848 { 1849 platform_driver_unregister(&chv_pinctrl_driver); 1850 } 1851 module_exit(chv_pinctrl_exit); 1852 1853 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1854 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1855 MODULE_LICENSE("GPL v2"); 1856