1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/dmi.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/types.h> 20 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 26 #include "pinctrl-intel.h" 27 28 #define CHV_INTSTAT 0x300 29 #define CHV_INTMASK 0x380 30 31 #define FAMILY_PAD_REGS_OFF 0x4400 32 #define FAMILY_PAD_REGS_SIZE 0x400 33 #define MAX_FAMILY_PAD_GPIO_NO 15 34 #define GPIO_REGS_SIZE 8 35 36 #define CHV_PADCTRL0 0x000 37 #define CHV_PADCTRL0_INTSEL_SHIFT 28 38 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 39 #define CHV_PADCTRL0_TERM_UP BIT(23) 40 #define CHV_PADCTRL0_TERM_SHIFT 20 41 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 42 #define CHV_PADCTRL0_TERM_20K 1 43 #define CHV_PADCTRL0_TERM_5K 2 44 #define CHV_PADCTRL0_TERM_1K 4 45 #define CHV_PADCTRL0_PMODE_SHIFT 16 46 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 47 #define CHV_PADCTRL0_GPIOEN BIT(15) 48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 49 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 51 #define CHV_PADCTRL0_GPIOCFG_GPO 1 52 #define CHV_PADCTRL0_GPIOCFG_GPI 2 53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 56 57 #define CHV_PADCTRL1 0x004 58 #define CHV_PADCTRL1_CFGLOCK BIT(31) 59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 60 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 61 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 62 #define CHV_PADCTRL1_ODEN BIT(3) 63 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 64 #define CHV_PADCTRL1_INTWAKECFG_MASK 7 65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 66 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 67 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 69 70 /** 71 * struct chv_alternate_function - A per group or per pin alternate function 72 * @pin: Pin number (only used in per pin configs) 73 * @mode: Mode the pin should be set in 74 * @invert_oe: Invert OE for this pin 75 */ 76 struct chv_alternate_function { 77 unsigned int pin; 78 u8 mode; 79 bool invert_oe; 80 }; 81 82 /** 83 * struct chv_pincgroup - describes a CHV pin group 84 * @name: Name of the group 85 * @pins: An array of pins in this group 86 * @npins: Number of pins in this group 87 * @altfunc: Alternate function applied to all pins in this group 88 * @overrides: Alternate function override per pin or %NULL if not used 89 * @noverrides: Number of per pin alternate function overrides if 90 * @overrides != NULL. 91 */ 92 struct chv_pingroup { 93 const char *name; 94 const unsigned int *pins; 95 size_t npins; 96 struct chv_alternate_function altfunc; 97 const struct chv_alternate_function *overrides; 98 size_t noverrides; 99 }; 100 101 /** 102 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 103 * @base: Start pin number 104 * @npins: Number of pins in this range 105 */ 106 struct chv_gpio_pinrange { 107 unsigned int base; 108 unsigned int npins; 109 }; 110 111 /** 112 * struct chv_community - A community specific configuration 113 * @uid: ACPI _UID used to match the community 114 * @pins: All pins in this community 115 * @npins: Number of pins 116 * @groups: All groups in this community 117 * @ngroups: Number of groups 118 * @functions: All functions in this community 119 * @nfunctions: Number of functions 120 * @gpio_ranges: An array of GPIO ranges in this community 121 * @ngpio_ranges: Number of GPIO ranges 122 * @nirqs: Total number of IRQs this community can generate 123 * @acpi_space_id: An address space ID for ACPI OpRegion handler 124 */ 125 struct chv_community { 126 const char *uid; 127 const struct pinctrl_pin_desc *pins; 128 size_t npins; 129 const struct chv_pingroup *groups; 130 size_t ngroups; 131 const struct intel_function *functions; 132 size_t nfunctions; 133 const struct chv_gpio_pinrange *gpio_ranges; 134 size_t ngpio_ranges; 135 size_t nirqs; 136 acpi_adr_space_type acpi_space_id; 137 }; 138 139 struct chv_pin_context { 140 u32 padctrl0; 141 u32 padctrl1; 142 }; 143 144 /** 145 * struct chv_pinctrl - CHV pinctrl private structure 146 * @dev: Pointer to the parent device 147 * @pctldesc: Pin controller description 148 * @pctldev: Pointer to the pin controller device 149 * @chip: GPIO chip in this pin controller 150 * @irqchip: IRQ chip in this pin controller 151 * @regs: MMIO registers 152 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 153 * offset (in GPIO number space) 154 * @community: Community this pinctrl instance represents 155 * @saved_intmask: Interrupt mask saved for system sleep 156 * @saved_pin_context: Pointer to a context of the pins saved for system sleep 157 * 158 * The first group in @groups is expected to contain all pins that can be 159 * used as GPIOs. 160 */ 161 struct chv_pinctrl { 162 struct device *dev; 163 struct pinctrl_desc pctldesc; 164 struct pinctrl_dev *pctldev; 165 struct gpio_chip chip; 166 struct irq_chip irqchip; 167 void __iomem *regs; 168 unsigned int intr_lines[16]; 169 const struct chv_community *community; 170 u32 saved_intmask; 171 struct chv_pin_context *saved_pin_context; 172 }; 173 174 #define ALTERNATE_FUNCTION(p, m, i) \ 175 { \ 176 .pin = (p), \ 177 .mode = (m), \ 178 .invert_oe = (i), \ 179 } 180 181 #define PIN_GROUP_WITH_ALT(n, p, m, i) \ 182 { \ 183 .name = (n), \ 184 .pins = (p), \ 185 .npins = ARRAY_SIZE((p)), \ 186 .altfunc.mode = (m), \ 187 .altfunc.invert_oe = (i), \ 188 } 189 190 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 191 { \ 192 .name = (n), \ 193 .pins = (p), \ 194 .npins = ARRAY_SIZE((p)), \ 195 .altfunc.mode = (m), \ 196 .altfunc.invert_oe = (i), \ 197 .overrides = (o), \ 198 .noverrides = ARRAY_SIZE((o)), \ 199 } 200 201 #define GPIO_PINRANGE(start, end) \ 202 { \ 203 .base = (start), \ 204 .npins = (end) - (start) + 1, \ 205 } 206 207 static const struct pinctrl_pin_desc southwest_pins[] = { 208 PINCTRL_PIN(0, "FST_SPI_D2"), 209 PINCTRL_PIN(1, "FST_SPI_D0"), 210 PINCTRL_PIN(2, "FST_SPI_CLK"), 211 PINCTRL_PIN(3, "FST_SPI_D3"), 212 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 213 PINCTRL_PIN(5, "FST_SPI_D1"), 214 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 215 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 216 217 PINCTRL_PIN(15, "UART1_RTS_B"), 218 PINCTRL_PIN(16, "UART1_RXD"), 219 PINCTRL_PIN(17, "UART2_RXD"), 220 PINCTRL_PIN(18, "UART1_CTS_B"), 221 PINCTRL_PIN(19, "UART2_RTS_B"), 222 PINCTRL_PIN(20, "UART1_TXD"), 223 PINCTRL_PIN(21, "UART2_TXD"), 224 PINCTRL_PIN(22, "UART2_CTS_B"), 225 226 PINCTRL_PIN(30, "MF_HDA_CLK"), 227 PINCTRL_PIN(31, "MF_HDA_RSTB"), 228 PINCTRL_PIN(32, "MF_HDA_SDIO"), 229 PINCTRL_PIN(33, "MF_HDA_SDO"), 230 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 231 PINCTRL_PIN(35, "MF_HDA_SYNC"), 232 PINCTRL_PIN(36, "MF_HDA_SDI1"), 233 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 234 235 PINCTRL_PIN(45, "I2C5_SDA"), 236 PINCTRL_PIN(46, "I2C4_SDA"), 237 PINCTRL_PIN(47, "I2C6_SDA"), 238 PINCTRL_PIN(48, "I2C5_SCL"), 239 PINCTRL_PIN(49, "I2C_NFC_SDA"), 240 PINCTRL_PIN(50, "I2C4_SCL"), 241 PINCTRL_PIN(51, "I2C6_SCL"), 242 PINCTRL_PIN(52, "I2C_NFC_SCL"), 243 244 PINCTRL_PIN(60, "I2C1_SDA"), 245 PINCTRL_PIN(61, "I2C0_SDA"), 246 PINCTRL_PIN(62, "I2C2_SDA"), 247 PINCTRL_PIN(63, "I2C1_SCL"), 248 PINCTRL_PIN(64, "I2C3_SDA"), 249 PINCTRL_PIN(65, "I2C0_SCL"), 250 PINCTRL_PIN(66, "I2C2_SCL"), 251 PINCTRL_PIN(67, "I2C3_SCL"), 252 253 PINCTRL_PIN(75, "SATA_GP0"), 254 PINCTRL_PIN(76, "SATA_GP1"), 255 PINCTRL_PIN(77, "SATA_LEDN"), 256 PINCTRL_PIN(78, "SATA_GP2"), 257 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 258 PINCTRL_PIN(80, "SATA_GP3"), 259 PINCTRL_PIN(81, "MF_SMB_CLK"), 260 PINCTRL_PIN(82, "MF_SMB_DATA"), 261 262 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 263 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 264 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 265 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 266 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 267 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 268 PINCTRL_PIN(96, "GP_SSP_2_FS"), 269 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 270 }; 271 272 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 273 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 274 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 275 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 276 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 277 static const unsigned southwest_lpe_pins[] = { 278 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 279 }; 280 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 281 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 282 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 283 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 284 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 285 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 286 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 287 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 288 289 /* LPE I2S TXD pins need to have invert_oe set */ 290 static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 291 ALTERNATE_FUNCTION(30, 1, true), 292 ALTERNATE_FUNCTION(34, 1, true), 293 ALTERNATE_FUNCTION(97, 1, true), 294 }; 295 296 /* 297 * Two spi3 chipselects are available in different mode than the main spi3 298 * functionality, which is using mode 1. 299 */ 300 static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 301 ALTERNATE_FUNCTION(76, 3, false), 302 ALTERNATE_FUNCTION(80, 3, false), 303 }; 304 305 static const struct chv_pingroup southwest_groups[] = { 306 PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), 307 PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), 308 PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), 309 PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), 310 PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), 311 PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), 312 PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), 313 PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), 314 PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), 315 PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), 316 PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), 317 PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 318 319 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 320 southwest_lpe_altfuncs), 321 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 322 southwest_spi3_altfuncs), 323 }; 324 325 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 326 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 327 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 328 static const char * const southwest_hda_groups[] = { "hda_grp" }; 329 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 330 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 331 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 332 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 333 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 334 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 335 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 336 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 337 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 338 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 339 340 /* 341 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 342 * enabled only as GPIOs. 343 */ 344 static const struct intel_function southwest_functions[] = { 345 FUNCTION("uart0", southwest_uart0_groups), 346 FUNCTION("uart1", southwest_uart1_groups), 347 FUNCTION("uart2", southwest_uart2_groups), 348 FUNCTION("hda", southwest_hda_groups), 349 FUNCTION("lpe", southwest_lpe_groups), 350 FUNCTION("i2c0", southwest_i2c0_groups), 351 FUNCTION("i2c1", southwest_i2c1_groups), 352 FUNCTION("i2c2", southwest_i2c2_groups), 353 FUNCTION("i2c3", southwest_i2c3_groups), 354 FUNCTION("i2c4", southwest_i2c4_groups), 355 FUNCTION("i2c5", southwest_i2c5_groups), 356 FUNCTION("i2c6", southwest_i2c6_groups), 357 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 358 FUNCTION("spi3", southwest_spi3_groups), 359 }; 360 361 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 362 GPIO_PINRANGE(0, 7), 363 GPIO_PINRANGE(15, 22), 364 GPIO_PINRANGE(30, 37), 365 GPIO_PINRANGE(45, 52), 366 GPIO_PINRANGE(60, 67), 367 GPIO_PINRANGE(75, 82), 368 GPIO_PINRANGE(90, 97), 369 }; 370 371 static const struct chv_community southwest_community = { 372 .uid = "1", 373 .pins = southwest_pins, 374 .npins = ARRAY_SIZE(southwest_pins), 375 .groups = southwest_groups, 376 .ngroups = ARRAY_SIZE(southwest_groups), 377 .functions = southwest_functions, 378 .nfunctions = ARRAY_SIZE(southwest_functions), 379 .gpio_ranges = southwest_gpio_ranges, 380 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 381 /* 382 * Southwest community can generate GPIO interrupts only for the 383 * first 8 interrupts. The upper half (8-15) can only be used to 384 * trigger GPEs. 385 */ 386 .nirqs = 8, 387 .acpi_space_id = 0x91, 388 }; 389 390 static const struct pinctrl_pin_desc north_pins[] = { 391 PINCTRL_PIN(0, "GPIO_DFX_0"), 392 PINCTRL_PIN(1, "GPIO_DFX_3"), 393 PINCTRL_PIN(2, "GPIO_DFX_7"), 394 PINCTRL_PIN(3, "GPIO_DFX_1"), 395 PINCTRL_PIN(4, "GPIO_DFX_5"), 396 PINCTRL_PIN(5, "GPIO_DFX_4"), 397 PINCTRL_PIN(6, "GPIO_DFX_8"), 398 PINCTRL_PIN(7, "GPIO_DFX_2"), 399 PINCTRL_PIN(8, "GPIO_DFX_6"), 400 401 PINCTRL_PIN(15, "GPIO_SUS0"), 402 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 403 PINCTRL_PIN(17, "GPIO_SUS3"), 404 PINCTRL_PIN(18, "GPIO_SUS7"), 405 PINCTRL_PIN(19, "GPIO_SUS1"), 406 PINCTRL_PIN(20, "GPIO_SUS5"), 407 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 408 PINCTRL_PIN(22, "GPIO_SUS4"), 409 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 410 PINCTRL_PIN(24, "GPIO_SUS2"), 411 PINCTRL_PIN(25, "GPIO_SUS6"), 412 PINCTRL_PIN(26, "CX_PREQ_B"), 413 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 414 415 PINCTRL_PIN(30, "TRST_B"), 416 PINCTRL_PIN(31, "TCK"), 417 PINCTRL_PIN(32, "PROCHOT_B"), 418 PINCTRL_PIN(33, "SVIDO_DATA"), 419 PINCTRL_PIN(34, "TMS"), 420 PINCTRL_PIN(35, "CX_PRDY_B_2"), 421 PINCTRL_PIN(36, "TDO_2"), 422 PINCTRL_PIN(37, "CX_PRDY_B"), 423 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 424 PINCTRL_PIN(39, "TDO"), 425 PINCTRL_PIN(40, "SVIDO_CLK"), 426 PINCTRL_PIN(41, "TDI"), 427 428 PINCTRL_PIN(45, "GP_CAMERASB_05"), 429 PINCTRL_PIN(46, "GP_CAMERASB_02"), 430 PINCTRL_PIN(47, "GP_CAMERASB_08"), 431 PINCTRL_PIN(48, "GP_CAMERASB_00"), 432 PINCTRL_PIN(49, "GP_CAMERASB_06"), 433 PINCTRL_PIN(50, "GP_CAMERASB_10"), 434 PINCTRL_PIN(51, "GP_CAMERASB_03"), 435 PINCTRL_PIN(52, "GP_CAMERASB_09"), 436 PINCTRL_PIN(53, "GP_CAMERASB_01"), 437 PINCTRL_PIN(54, "GP_CAMERASB_07"), 438 PINCTRL_PIN(55, "GP_CAMERASB_11"), 439 PINCTRL_PIN(56, "GP_CAMERASB_04"), 440 441 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 442 PINCTRL_PIN(61, "HV_DDI0_HPD"), 443 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 444 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 445 PINCTRL_PIN(64, "HV_DDI1_HPD"), 446 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 447 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 448 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 449 PINCTRL_PIN(68, "HV_DDI2_HPD"), 450 PINCTRL_PIN(69, "PANEL1_VDDEN"), 451 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 452 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 453 PINCTRL_PIN(72, "PANEL0_VDDEN"), 454 }; 455 456 static const struct chv_gpio_pinrange north_gpio_ranges[] = { 457 GPIO_PINRANGE(0, 8), 458 GPIO_PINRANGE(15, 27), 459 GPIO_PINRANGE(30, 41), 460 GPIO_PINRANGE(45, 56), 461 GPIO_PINRANGE(60, 72), 462 }; 463 464 static const struct chv_community north_community = { 465 .uid = "2", 466 .pins = north_pins, 467 .npins = ARRAY_SIZE(north_pins), 468 .gpio_ranges = north_gpio_ranges, 469 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 470 /* 471 * North community can generate GPIO interrupts only for the first 472 * 8 interrupts. The upper half (8-15) can only be used to trigger 473 * GPEs. 474 */ 475 .nirqs = 8, 476 .acpi_space_id = 0x92, 477 }; 478 479 static const struct pinctrl_pin_desc east_pins[] = { 480 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 481 PINCTRL_PIN(1, "PMU_BATLOW_B"), 482 PINCTRL_PIN(2, "SUS_STAT_B"), 483 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 484 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 485 PINCTRL_PIN(5, "PMU_PLTRST_B"), 486 PINCTRL_PIN(6, "PMU_SUSCLK"), 487 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 488 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 489 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 490 PINCTRL_PIN(10, "PMU_WAKE_B"), 491 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 492 493 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 494 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 495 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 496 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 497 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 498 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 499 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 500 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 501 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 502 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 503 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 504 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 505 }; 506 507 static const struct chv_gpio_pinrange east_gpio_ranges[] = { 508 GPIO_PINRANGE(0, 11), 509 GPIO_PINRANGE(15, 26), 510 }; 511 512 static const struct chv_community east_community = { 513 .uid = "3", 514 .pins = east_pins, 515 .npins = ARRAY_SIZE(east_pins), 516 .gpio_ranges = east_gpio_ranges, 517 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 518 .nirqs = 16, 519 .acpi_space_id = 0x93, 520 }; 521 522 static const struct pinctrl_pin_desc southeast_pins[] = { 523 PINCTRL_PIN(0, "MF_PLT_CLK0"), 524 PINCTRL_PIN(1, "PWM1"), 525 PINCTRL_PIN(2, "MF_PLT_CLK1"), 526 PINCTRL_PIN(3, "MF_PLT_CLK4"), 527 PINCTRL_PIN(4, "MF_PLT_CLK3"), 528 PINCTRL_PIN(5, "PWM0"), 529 PINCTRL_PIN(6, "MF_PLT_CLK5"), 530 PINCTRL_PIN(7, "MF_PLT_CLK2"), 531 532 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 533 PINCTRL_PIN(16, "SDMMC1_CLK"), 534 PINCTRL_PIN(17, "SDMMC1_D0"), 535 PINCTRL_PIN(18, "SDMMC2_D1"), 536 PINCTRL_PIN(19, "SDMMC2_CLK"), 537 PINCTRL_PIN(20, "SDMMC1_D2"), 538 PINCTRL_PIN(21, "SDMMC2_D2"), 539 PINCTRL_PIN(22, "SDMMC2_CMD"), 540 PINCTRL_PIN(23, "SDMMC1_CMD"), 541 PINCTRL_PIN(24, "SDMMC1_D1"), 542 PINCTRL_PIN(25, "SDMMC2_D0"), 543 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 544 545 PINCTRL_PIN(30, "SDMMC3_D1"), 546 PINCTRL_PIN(31, "SDMMC3_CLK"), 547 PINCTRL_PIN(32, "SDMMC3_D3"), 548 PINCTRL_PIN(33, "SDMMC3_D2"), 549 PINCTRL_PIN(34, "SDMMC3_CMD"), 550 PINCTRL_PIN(35, "SDMMC3_D0"), 551 552 PINCTRL_PIN(45, "MF_LPC_AD2"), 553 PINCTRL_PIN(46, "LPC_CLKRUNB"), 554 PINCTRL_PIN(47, "MF_LPC_AD0"), 555 PINCTRL_PIN(48, "LPC_FRAMEB"), 556 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 557 PINCTRL_PIN(50, "MF_LPC_AD3"), 558 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 559 PINCTRL_PIN(52, "MF_LPC_AD1"), 560 561 PINCTRL_PIN(60, "SPI1_MISO"), 562 PINCTRL_PIN(61, "SPI1_CSO_B"), 563 PINCTRL_PIN(62, "SPI1_CLK"), 564 PINCTRL_PIN(63, "MMC1_D6"), 565 PINCTRL_PIN(64, "SPI1_MOSI"), 566 PINCTRL_PIN(65, "MMC1_D5"), 567 PINCTRL_PIN(66, "SPI1_CS1_B"), 568 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 569 PINCTRL_PIN(68, "MMC1_D7"), 570 PINCTRL_PIN(69, "MMC1_RCLK"), 571 572 PINCTRL_PIN(75, "USB_OC1_B"), 573 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 574 PINCTRL_PIN(77, "GPIO_ALERT"), 575 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 576 PINCTRL_PIN(79, "ILB_SERIRQ"), 577 PINCTRL_PIN(80, "USB_OC0_B"), 578 PINCTRL_PIN(81, "SDMMC3_CD_B"), 579 PINCTRL_PIN(82, "SPKR"), 580 PINCTRL_PIN(83, "SUSPWRDNACK"), 581 PINCTRL_PIN(84, "SPARE_PIN"), 582 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 583 }; 584 585 static const unsigned southeast_pwm0_pins[] = { 5 }; 586 static const unsigned southeast_pwm1_pins[] = { 1 }; 587 static const unsigned southeast_sdmmc1_pins[] = { 588 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 589 }; 590 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 591 static const unsigned southeast_sdmmc3_pins[] = { 592 30, 31, 32, 33, 34, 35, 78, 81, 85, 593 }; 594 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 595 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 596 597 static const struct chv_pingroup southeast_groups[] = { 598 PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), 599 PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), 600 PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 601 PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 602 PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 603 PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), 604 PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), 605 }; 606 607 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 608 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 609 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 610 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 611 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 612 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 613 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 614 615 static const struct intel_function southeast_functions[] = { 616 FUNCTION("pwm0", southeast_pwm0_groups), 617 FUNCTION("pwm1", southeast_pwm1_groups), 618 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 619 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 620 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 621 FUNCTION("spi1", southeast_spi1_groups), 622 FUNCTION("spi2", southeast_spi2_groups), 623 }; 624 625 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 626 GPIO_PINRANGE(0, 7), 627 GPIO_PINRANGE(15, 26), 628 GPIO_PINRANGE(30, 35), 629 GPIO_PINRANGE(45, 52), 630 GPIO_PINRANGE(60, 69), 631 GPIO_PINRANGE(75, 85), 632 }; 633 634 static const struct chv_community southeast_community = { 635 .uid = "4", 636 .pins = southeast_pins, 637 .npins = ARRAY_SIZE(southeast_pins), 638 .groups = southeast_groups, 639 .ngroups = ARRAY_SIZE(southeast_groups), 640 .functions = southeast_functions, 641 .nfunctions = ARRAY_SIZE(southeast_functions), 642 .gpio_ranges = southeast_gpio_ranges, 643 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 644 .nirqs = 16, 645 .acpi_space_id = 0x94, 646 }; 647 648 static const struct chv_community *chv_communities[] = { 649 &southwest_community, 650 &north_community, 651 &east_community, 652 &southeast_community, 653 }; 654 655 /* 656 * Lock to serialize register accesses 657 * 658 * Due to a silicon issue, a shared lock must be used to prevent 659 * concurrent accesses across the 4 GPIO controllers. 660 * 661 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 662 * errata #CHT34, for further information. 663 */ 664 static DEFINE_RAW_SPINLOCK(chv_lock); 665 666 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset, 667 unsigned int reg) 668 { 669 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 670 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 671 672 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 673 GPIO_REGS_SIZE * pad_no; 674 675 return pctrl->regs + offset + reg; 676 } 677 678 static void chv_writel(u32 value, void __iomem *reg) 679 { 680 writel(value, reg); 681 /* simple readback to confirm the bus transferring done */ 682 readl(reg); 683 } 684 685 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 686 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset) 687 { 688 void __iomem *reg; 689 690 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 691 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 692 } 693 694 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 695 { 696 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 697 698 return pctrl->community->ngroups; 699 } 700 701 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 702 unsigned int group) 703 { 704 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 705 706 return pctrl->community->groups[group].name; 707 } 708 709 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, 710 const unsigned int **pins, unsigned int *npins) 711 { 712 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 713 714 *pins = pctrl->community->groups[group].pins; 715 *npins = pctrl->community->groups[group].npins; 716 return 0; 717 } 718 719 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 720 unsigned int offset) 721 { 722 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 723 unsigned long flags; 724 u32 ctrl0, ctrl1; 725 bool locked; 726 727 raw_spin_lock_irqsave(&chv_lock, flags); 728 729 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 730 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 731 locked = chv_pad_locked(pctrl, offset); 732 733 raw_spin_unlock_irqrestore(&chv_lock, flags); 734 735 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 736 seq_puts(s, "GPIO "); 737 } else { 738 u32 mode; 739 740 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 741 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 742 743 seq_printf(s, "mode %d ", mode); 744 } 745 746 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 747 748 if (locked) 749 seq_puts(s, " [LOCKED]"); 750 } 751 752 static const struct pinctrl_ops chv_pinctrl_ops = { 753 .get_groups_count = chv_get_groups_count, 754 .get_group_name = chv_get_group_name, 755 .get_group_pins = chv_get_group_pins, 756 .pin_dbg_show = chv_pin_dbg_show, 757 }; 758 759 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 760 { 761 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 762 763 return pctrl->community->nfunctions; 764 } 765 766 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 767 unsigned int function) 768 { 769 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 770 771 return pctrl->community->functions[function].name; 772 } 773 774 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 775 unsigned int function, 776 const char * const **groups, 777 unsigned int * const ngroups) 778 { 779 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 780 781 *groups = pctrl->community->functions[function].groups; 782 *ngroups = pctrl->community->functions[function].ngroups; 783 return 0; 784 } 785 786 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 787 unsigned int function, unsigned int group) 788 { 789 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 790 const struct chv_pingroup *grp; 791 unsigned long flags; 792 int i; 793 794 grp = &pctrl->community->groups[group]; 795 796 raw_spin_lock_irqsave(&chv_lock, flags); 797 798 /* Check first that the pad is not locked */ 799 for (i = 0; i < grp->npins; i++) { 800 if (chv_pad_locked(pctrl, grp->pins[i])) { 801 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 802 grp->pins[i]); 803 raw_spin_unlock_irqrestore(&chv_lock, flags); 804 return -EBUSY; 805 } 806 } 807 808 for (i = 0; i < grp->npins; i++) { 809 const struct chv_alternate_function *altfunc = &grp->altfunc; 810 int pin = grp->pins[i]; 811 void __iomem *reg; 812 u32 value; 813 814 /* Check if there is pin-specific config */ 815 if (grp->overrides) { 816 int j; 817 818 for (j = 0; j < grp->noverrides; j++) { 819 if (grp->overrides[j].pin == pin) { 820 altfunc = &grp->overrides[j]; 821 break; 822 } 823 } 824 } 825 826 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 827 value = readl(reg); 828 /* Disable GPIO mode */ 829 value &= ~CHV_PADCTRL0_GPIOEN; 830 /* Set to desired mode */ 831 value &= ~CHV_PADCTRL0_PMODE_MASK; 832 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 833 chv_writel(value, reg); 834 835 /* Update for invert_oe */ 836 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 837 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 838 if (altfunc->invert_oe) 839 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 840 chv_writel(value, reg); 841 842 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 843 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 844 } 845 846 raw_spin_unlock_irqrestore(&chv_lock, flags); 847 848 return 0; 849 } 850 851 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl, 852 unsigned int offset) 853 { 854 void __iomem *reg; 855 u32 value; 856 857 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 858 value = readl(reg); 859 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 860 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 861 chv_writel(value, reg); 862 } 863 864 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 865 struct pinctrl_gpio_range *range, 866 unsigned int offset) 867 { 868 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 869 unsigned long flags; 870 void __iomem *reg; 871 u32 value; 872 873 raw_spin_lock_irqsave(&chv_lock, flags); 874 875 if (chv_pad_locked(pctrl, offset)) { 876 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 877 if (!(value & CHV_PADCTRL0_GPIOEN)) { 878 /* Locked so cannot enable */ 879 raw_spin_unlock_irqrestore(&chv_lock, flags); 880 return -EBUSY; 881 } 882 } else { 883 int i; 884 885 /* Reset the interrupt mapping */ 886 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 887 if (pctrl->intr_lines[i] == offset) { 888 pctrl->intr_lines[i] = 0; 889 break; 890 } 891 } 892 893 /* Disable interrupt generation */ 894 chv_gpio_clear_triggering(pctrl, offset); 895 896 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 897 value = readl(reg); 898 899 /* 900 * If the pin is in HiZ mode (both TX and RX buffers are 901 * disabled) we turn it to be input now. 902 */ 903 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 904 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 905 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 906 value |= CHV_PADCTRL0_GPIOCFG_GPI << 907 CHV_PADCTRL0_GPIOCFG_SHIFT; 908 } 909 910 /* Switch to a GPIO mode */ 911 value |= CHV_PADCTRL0_GPIOEN; 912 chv_writel(value, reg); 913 } 914 915 raw_spin_unlock_irqrestore(&chv_lock, flags); 916 917 return 0; 918 } 919 920 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 921 struct pinctrl_gpio_range *range, 922 unsigned int offset) 923 { 924 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 925 unsigned long flags; 926 927 raw_spin_lock_irqsave(&chv_lock, flags); 928 929 if (!chv_pad_locked(pctrl, offset)) 930 chv_gpio_clear_triggering(pctrl, offset); 931 932 raw_spin_unlock_irqrestore(&chv_lock, flags); 933 } 934 935 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 936 struct pinctrl_gpio_range *range, 937 unsigned int offset, bool input) 938 { 939 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 940 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 941 unsigned long flags; 942 u32 ctrl0; 943 944 raw_spin_lock_irqsave(&chv_lock, flags); 945 946 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 947 if (input) 948 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 949 else 950 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 951 chv_writel(ctrl0, reg); 952 953 raw_spin_unlock_irqrestore(&chv_lock, flags); 954 955 return 0; 956 } 957 958 static const struct pinmux_ops chv_pinmux_ops = { 959 .get_functions_count = chv_get_functions_count, 960 .get_function_name = chv_get_function_name, 961 .get_function_groups = chv_get_function_groups, 962 .set_mux = chv_pinmux_set_mux, 963 .gpio_request_enable = chv_gpio_request_enable, 964 .gpio_disable_free = chv_gpio_disable_free, 965 .gpio_set_direction = chv_gpio_set_direction, 966 }; 967 968 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 969 unsigned long *config) 970 { 971 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 972 enum pin_config_param param = pinconf_to_config_param(*config); 973 unsigned long flags; 974 u32 ctrl0, ctrl1; 975 u16 arg = 0; 976 u32 term; 977 978 raw_spin_lock_irqsave(&chv_lock, flags); 979 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 980 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 981 raw_spin_unlock_irqrestore(&chv_lock, flags); 982 983 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 984 985 switch (param) { 986 case PIN_CONFIG_BIAS_DISABLE: 987 if (term) 988 return -EINVAL; 989 break; 990 991 case PIN_CONFIG_BIAS_PULL_UP: 992 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 993 return -EINVAL; 994 995 switch (term) { 996 case CHV_PADCTRL0_TERM_20K: 997 arg = 20000; 998 break; 999 case CHV_PADCTRL0_TERM_5K: 1000 arg = 5000; 1001 break; 1002 case CHV_PADCTRL0_TERM_1K: 1003 arg = 1000; 1004 break; 1005 } 1006 1007 break; 1008 1009 case PIN_CONFIG_BIAS_PULL_DOWN: 1010 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 1011 return -EINVAL; 1012 1013 switch (term) { 1014 case CHV_PADCTRL0_TERM_20K: 1015 arg = 20000; 1016 break; 1017 case CHV_PADCTRL0_TERM_5K: 1018 arg = 5000; 1019 break; 1020 } 1021 1022 break; 1023 1024 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1025 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 1026 return -EINVAL; 1027 break; 1028 1029 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1030 u32 cfg; 1031 1032 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1033 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1034 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1035 return -EINVAL; 1036 1037 break; 1038 } 1039 1040 default: 1041 return -ENOTSUPP; 1042 } 1043 1044 *config = pinconf_to_config_packed(param, arg); 1045 return 0; 1046 } 1047 1048 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin, 1049 enum pin_config_param param, u32 arg) 1050 { 1051 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1052 unsigned long flags; 1053 u32 ctrl0, pull; 1054 1055 raw_spin_lock_irqsave(&chv_lock, flags); 1056 ctrl0 = readl(reg); 1057 1058 switch (param) { 1059 case PIN_CONFIG_BIAS_DISABLE: 1060 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1061 break; 1062 1063 case PIN_CONFIG_BIAS_PULL_UP: 1064 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1065 1066 switch (arg) { 1067 case 1000: 1068 /* For 1k there is only pull up */ 1069 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1070 break; 1071 case 5000: 1072 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1073 break; 1074 case 20000: 1075 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1076 break; 1077 default: 1078 raw_spin_unlock_irqrestore(&chv_lock, flags); 1079 return -EINVAL; 1080 } 1081 1082 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1083 break; 1084 1085 case PIN_CONFIG_BIAS_PULL_DOWN: 1086 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1087 1088 switch (arg) { 1089 case 5000: 1090 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1091 break; 1092 case 20000: 1093 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1094 break; 1095 default: 1096 raw_spin_unlock_irqrestore(&chv_lock, flags); 1097 return -EINVAL; 1098 } 1099 1100 ctrl0 |= pull; 1101 break; 1102 1103 default: 1104 raw_spin_unlock_irqrestore(&chv_lock, flags); 1105 return -EINVAL; 1106 } 1107 1108 chv_writel(ctrl0, reg); 1109 raw_spin_unlock_irqrestore(&chv_lock, flags); 1110 1111 return 0; 1112 } 1113 1114 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1115 bool enable) 1116 { 1117 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1118 unsigned long flags; 1119 u32 ctrl1; 1120 1121 raw_spin_lock_irqsave(&chv_lock, flags); 1122 ctrl1 = readl(reg); 1123 1124 if (enable) 1125 ctrl1 |= CHV_PADCTRL1_ODEN; 1126 else 1127 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1128 1129 chv_writel(ctrl1, reg); 1130 raw_spin_unlock_irqrestore(&chv_lock, flags); 1131 1132 return 0; 1133 } 1134 1135 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1136 unsigned long *configs, unsigned int nconfigs) 1137 { 1138 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1139 enum pin_config_param param; 1140 int i, ret; 1141 u32 arg; 1142 1143 if (chv_pad_locked(pctrl, pin)) 1144 return -EBUSY; 1145 1146 for (i = 0; i < nconfigs; i++) { 1147 param = pinconf_to_config_param(configs[i]); 1148 arg = pinconf_to_config_argument(configs[i]); 1149 1150 switch (param) { 1151 case PIN_CONFIG_BIAS_DISABLE: 1152 case PIN_CONFIG_BIAS_PULL_UP: 1153 case PIN_CONFIG_BIAS_PULL_DOWN: 1154 ret = chv_config_set_pull(pctrl, pin, param, arg); 1155 if (ret) 1156 return ret; 1157 break; 1158 1159 case PIN_CONFIG_DRIVE_PUSH_PULL: 1160 ret = chv_config_set_oden(pctrl, pin, false); 1161 if (ret) 1162 return ret; 1163 break; 1164 1165 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1166 ret = chv_config_set_oden(pctrl, pin, true); 1167 if (ret) 1168 return ret; 1169 break; 1170 1171 default: 1172 return -ENOTSUPP; 1173 } 1174 1175 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1176 param, arg); 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1183 unsigned int group, 1184 unsigned long *config) 1185 { 1186 const unsigned int *pins; 1187 unsigned int npins; 1188 int ret; 1189 1190 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1191 if (ret) 1192 return ret; 1193 1194 ret = chv_config_get(pctldev, pins[0], config); 1195 if (ret) 1196 return ret; 1197 1198 return 0; 1199 } 1200 1201 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1202 unsigned int group, unsigned long *configs, 1203 unsigned int num_configs) 1204 { 1205 const unsigned int *pins; 1206 unsigned int npins; 1207 int i, ret; 1208 1209 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1210 if (ret) 1211 return ret; 1212 1213 for (i = 0; i < npins; i++) { 1214 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1215 if (ret) 1216 return ret; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static const struct pinconf_ops chv_pinconf_ops = { 1223 .is_generic = true, 1224 .pin_config_set = chv_config_set, 1225 .pin_config_get = chv_config_get, 1226 .pin_config_group_get = chv_config_group_get, 1227 .pin_config_group_set = chv_config_group_set, 1228 }; 1229 1230 static struct pinctrl_desc chv_pinctrl_desc = { 1231 .pctlops = &chv_pinctrl_ops, 1232 .pmxops = &chv_pinmux_ops, 1233 .confops = &chv_pinconf_ops, 1234 .owner = THIS_MODULE, 1235 }; 1236 1237 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1238 { 1239 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1240 unsigned long flags; 1241 u32 ctrl0, cfg; 1242 1243 raw_spin_lock_irqsave(&chv_lock, flags); 1244 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1245 raw_spin_unlock_irqrestore(&chv_lock, flags); 1246 1247 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1248 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1249 1250 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1251 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1252 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1253 } 1254 1255 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1256 { 1257 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1258 unsigned long flags; 1259 void __iomem *reg; 1260 u32 ctrl0; 1261 1262 raw_spin_lock_irqsave(&chv_lock, flags); 1263 1264 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 1265 ctrl0 = readl(reg); 1266 1267 if (value) 1268 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1269 else 1270 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1271 1272 chv_writel(ctrl0, reg); 1273 1274 raw_spin_unlock_irqrestore(&chv_lock, flags); 1275 } 1276 1277 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1278 { 1279 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1280 u32 ctrl0, direction; 1281 unsigned long flags; 1282 1283 raw_spin_lock_irqsave(&chv_lock, flags); 1284 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1285 raw_spin_unlock_irqrestore(&chv_lock, flags); 1286 1287 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1288 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1289 1290 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1291 } 1292 1293 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1294 { 1295 return pinctrl_gpio_direction_input(chip->base + offset); 1296 } 1297 1298 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1299 int value) 1300 { 1301 chv_gpio_set(chip, offset, value); 1302 return pinctrl_gpio_direction_output(chip->base + offset); 1303 } 1304 1305 static const struct gpio_chip chv_gpio_chip = { 1306 .owner = THIS_MODULE, 1307 .request = gpiochip_generic_request, 1308 .free = gpiochip_generic_free, 1309 .get_direction = chv_gpio_get_direction, 1310 .direction_input = chv_gpio_direction_input, 1311 .direction_output = chv_gpio_direction_output, 1312 .get = chv_gpio_get, 1313 .set = chv_gpio_set, 1314 }; 1315 1316 static void chv_gpio_irq_ack(struct irq_data *d) 1317 { 1318 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1319 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1320 int pin = irqd_to_hwirq(d); 1321 u32 intr_line; 1322 1323 raw_spin_lock(&chv_lock); 1324 1325 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1326 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1327 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1328 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1329 1330 raw_spin_unlock(&chv_lock); 1331 } 1332 1333 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1334 { 1335 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1336 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1337 int pin = irqd_to_hwirq(d); 1338 u32 value, intr_line; 1339 unsigned long flags; 1340 1341 raw_spin_lock_irqsave(&chv_lock, flags); 1342 1343 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1344 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1345 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1346 1347 value = readl(pctrl->regs + CHV_INTMASK); 1348 if (mask) 1349 value &= ~BIT(intr_line); 1350 else 1351 value |= BIT(intr_line); 1352 chv_writel(value, pctrl->regs + CHV_INTMASK); 1353 1354 raw_spin_unlock_irqrestore(&chv_lock, flags); 1355 } 1356 1357 static void chv_gpio_irq_mask(struct irq_data *d) 1358 { 1359 chv_gpio_irq_mask_unmask(d, true); 1360 } 1361 1362 static void chv_gpio_irq_unmask(struct irq_data *d) 1363 { 1364 chv_gpio_irq_mask_unmask(d, false); 1365 } 1366 1367 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1368 { 1369 /* 1370 * Check if the interrupt has been requested with 0 as triggering 1371 * type. In that case it is assumed that the current values 1372 * programmed to the hardware are used (e.g BIOS configured 1373 * defaults). 1374 * 1375 * In that case ->irq_set_type() will never be called so we need to 1376 * read back the values from hardware now, set correct flow handler 1377 * and update mappings before the interrupt is being used. 1378 */ 1379 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1380 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1381 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1382 unsigned int pin = irqd_to_hwirq(d); 1383 irq_flow_handler_t handler; 1384 unsigned long flags; 1385 u32 intsel, value; 1386 1387 raw_spin_lock_irqsave(&chv_lock, flags); 1388 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1389 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1390 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1391 1392 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1393 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1394 handler = handle_level_irq; 1395 else 1396 handler = handle_edge_irq; 1397 1398 if (!pctrl->intr_lines[intsel]) { 1399 irq_set_handler_locked(d, handler); 1400 pctrl->intr_lines[intsel] = pin; 1401 } 1402 raw_spin_unlock_irqrestore(&chv_lock, flags); 1403 } 1404 1405 chv_gpio_irq_unmask(d); 1406 return 0; 1407 } 1408 1409 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1410 { 1411 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1412 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1413 unsigned int pin = irqd_to_hwirq(d); 1414 unsigned long flags; 1415 u32 value; 1416 1417 raw_spin_lock_irqsave(&chv_lock, flags); 1418 1419 /* 1420 * Pins which can be used as shared interrupt are configured in 1421 * BIOS. Driver trusts BIOS configurations and assigns different 1422 * handler according to the irq type. 1423 * 1424 * Driver needs to save the mapping between each pin and 1425 * its interrupt line. 1426 * 1. If the pin cfg is locked in BIOS: 1427 * Trust BIOS has programmed IntWakeCfg bits correctly, 1428 * driver just needs to save the mapping. 1429 * 2. If the pin cfg is not locked in BIOS: 1430 * Driver programs the IntWakeCfg bits and save the mapping. 1431 */ 1432 if (!chv_pad_locked(pctrl, pin)) { 1433 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1434 1435 value = readl(reg); 1436 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1437 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1438 1439 if (type & IRQ_TYPE_EDGE_BOTH) { 1440 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1441 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1442 else if (type & IRQ_TYPE_EDGE_RISING) 1443 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1444 else if (type & IRQ_TYPE_EDGE_FALLING) 1445 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1446 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1447 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1448 if (type & IRQ_TYPE_LEVEL_LOW) 1449 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1450 } 1451 1452 chv_writel(value, reg); 1453 } 1454 1455 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1456 value &= CHV_PADCTRL0_INTSEL_MASK; 1457 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1458 1459 pctrl->intr_lines[value] = pin; 1460 1461 if (type & IRQ_TYPE_EDGE_BOTH) 1462 irq_set_handler_locked(d, handle_edge_irq); 1463 else if (type & IRQ_TYPE_LEVEL_MASK) 1464 irq_set_handler_locked(d, handle_level_irq); 1465 1466 raw_spin_unlock_irqrestore(&chv_lock, flags); 1467 1468 return 0; 1469 } 1470 1471 static void chv_gpio_irq_handler(struct irq_desc *desc) 1472 { 1473 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1474 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1475 struct irq_chip *chip = irq_desc_get_chip(desc); 1476 unsigned long pending; 1477 u32 intr_line; 1478 1479 chained_irq_enter(chip, desc); 1480 1481 pending = readl(pctrl->regs + CHV_INTSTAT); 1482 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 1483 unsigned int irq, offset; 1484 1485 offset = pctrl->intr_lines[intr_line]; 1486 irq = irq_find_mapping(gc->irq.domain, offset); 1487 generic_handle_irq(irq); 1488 } 1489 1490 chained_irq_exit(chip, desc); 1491 } 1492 1493 /* 1494 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1495 * tables. Since we leave GPIOs that are not capable of generating 1496 * interrupts out of the irqdomain the numbering will be different and 1497 * cause devices using the hardcoded IRQ numbers fail. In order not to 1498 * break such machines we will only mask pins from irqdomain if the machine 1499 * is not listed below. 1500 */ 1501 static const struct dmi_system_id chv_no_valid_mask[] = { 1502 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1503 { 1504 .ident = "Intel_Strago based Chromebooks (All models)", 1505 .matches = { 1506 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1507 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1508 }, 1509 }, 1510 { 1511 .ident = "HP Chromebook 11 G5 (Setzer)", 1512 .matches = { 1513 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1514 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1515 }, 1516 }, 1517 { 1518 .ident = "Acer Chromebook R11 (Cyan)", 1519 .matches = { 1520 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1521 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1522 }, 1523 }, 1524 { 1525 .ident = "Samsung Chromebook 3 (Celes)", 1526 .matches = { 1527 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1528 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1529 }, 1530 }, 1531 {} 1532 }; 1533 1534 static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1535 unsigned long *valid_mask, 1536 unsigned int ngpios) 1537 { 1538 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1539 const struct chv_community *community = pctrl->community; 1540 int i; 1541 1542 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1543 for (i = 0; i < community->npins; i++) { 1544 const struct pinctrl_pin_desc *desc; 1545 u32 intsel; 1546 1547 desc = &community->pins[i]; 1548 1549 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 1550 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1551 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1552 1553 if (intsel >= community->nirqs) 1554 clear_bit(desc->number, valid_mask); 1555 } 1556 } 1557 1558 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1559 { 1560 const struct chv_gpio_pinrange *range; 1561 struct gpio_chip *chip = &pctrl->chip; 1562 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1563 const struct chv_community *community = pctrl->community; 1564 int ret, i, irq_base; 1565 1566 *chip = chv_gpio_chip; 1567 1568 chip->ngpio = community->pins[community->npins - 1].number + 1; 1569 chip->label = dev_name(pctrl->dev); 1570 chip->parent = pctrl->dev; 1571 chip->base = -1; 1572 if (need_valid_mask) 1573 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1574 1575 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1576 if (ret) { 1577 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1578 return ret; 1579 } 1580 1581 for (i = 0; i < community->ngpio_ranges; i++) { 1582 range = &community->gpio_ranges[i]; 1583 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), 1584 range->base, range->base, 1585 range->npins); 1586 if (ret) { 1587 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1588 return ret; 1589 } 1590 } 1591 1592 /* 1593 * The same set of machines in chv_no_valid_mask[] have incorrectly 1594 * configured GPIOs that generate spurious interrupts so we use 1595 * this same list to apply another quirk for them. 1596 * 1597 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1598 */ 1599 if (!need_valid_mask) { 1600 /* 1601 * Mask all interrupts the community is able to generate 1602 * but leave the ones that can only generate GPEs unmasked. 1603 */ 1604 chv_writel(GENMASK(31, pctrl->community->nirqs), 1605 pctrl->regs + CHV_INTMASK); 1606 } 1607 1608 /* Clear all interrupts */ 1609 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1610 1611 if (!need_valid_mask) { 1612 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 1613 community->npins, NUMA_NO_NODE); 1614 if (irq_base < 0) { 1615 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1616 return irq_base; 1617 } 1618 } 1619 1620 pctrl->irqchip.name = "chv-gpio"; 1621 pctrl->irqchip.irq_startup = chv_gpio_irq_startup; 1622 pctrl->irqchip.irq_ack = chv_gpio_irq_ack; 1623 pctrl->irqchip.irq_mask = chv_gpio_irq_mask; 1624 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; 1625 pctrl->irqchip.irq_set_type = chv_gpio_irq_type; 1626 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; 1627 1628 ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0, 1629 handle_bad_irq, IRQ_TYPE_NONE); 1630 if (ret) { 1631 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1632 return ret; 1633 } 1634 1635 if (!need_valid_mask) { 1636 for (i = 0; i < community->ngpio_ranges; i++) { 1637 range = &community->gpio_ranges[i]; 1638 1639 irq_domain_associate_many(chip->irq.domain, irq_base, 1640 range->base, range->npins); 1641 irq_base += range->npins; 1642 } 1643 } 1644 1645 gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq, 1646 chv_gpio_irq_handler); 1647 return 0; 1648 } 1649 1650 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1651 acpi_physical_address address, u32 bits, u64 *value, 1652 void *handler_context, void *region_context) 1653 { 1654 struct chv_pinctrl *pctrl = region_context; 1655 unsigned long flags; 1656 acpi_status ret = AE_OK; 1657 1658 raw_spin_lock_irqsave(&chv_lock, flags); 1659 1660 if (function == ACPI_WRITE) 1661 chv_writel((u32)(*value), pctrl->regs + (u32)address); 1662 else if (function == ACPI_READ) 1663 *value = readl(pctrl->regs + (u32)address); 1664 else 1665 ret = AE_BAD_PARAMETER; 1666 1667 raw_spin_unlock_irqrestore(&chv_lock, flags); 1668 1669 return ret; 1670 } 1671 1672 static int chv_pinctrl_probe(struct platform_device *pdev) 1673 { 1674 struct chv_pinctrl *pctrl; 1675 struct acpi_device *adev; 1676 acpi_status status; 1677 int ret, irq, i; 1678 1679 adev = ACPI_COMPANION(&pdev->dev); 1680 if (!adev) 1681 return -ENODEV; 1682 1683 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1684 if (!pctrl) 1685 return -ENOMEM; 1686 1687 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1688 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1689 pctrl->community = chv_communities[i]; 1690 break; 1691 } 1692 if (i == ARRAY_SIZE(chv_communities)) 1693 return -ENODEV; 1694 1695 pctrl->dev = &pdev->dev; 1696 1697 #ifdef CONFIG_PM_SLEEP 1698 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 1699 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 1700 GFP_KERNEL); 1701 if (!pctrl->saved_pin_context) 1702 return -ENOMEM; 1703 #endif 1704 1705 pctrl->regs = devm_platform_ioremap_resource(pdev, 0); 1706 if (IS_ERR(pctrl->regs)) 1707 return PTR_ERR(pctrl->regs); 1708 1709 irq = platform_get_irq(pdev, 0); 1710 if (irq < 0) 1711 return irq; 1712 1713 pctrl->pctldesc = chv_pinctrl_desc; 1714 pctrl->pctldesc.name = dev_name(&pdev->dev); 1715 pctrl->pctldesc.pins = pctrl->community->pins; 1716 pctrl->pctldesc.npins = pctrl->community->npins; 1717 1718 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1719 pctrl); 1720 if (IS_ERR(pctrl->pctldev)) { 1721 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1722 return PTR_ERR(pctrl->pctldev); 1723 } 1724 1725 ret = chv_gpio_probe(pctrl, irq); 1726 if (ret) 1727 return ret; 1728 1729 status = acpi_install_address_space_handler(adev->handle, 1730 pctrl->community->acpi_space_id, 1731 chv_pinctrl_mmio_access_handler, 1732 NULL, pctrl); 1733 if (ACPI_FAILURE(status)) 1734 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1735 1736 platform_set_drvdata(pdev, pctrl); 1737 1738 return 0; 1739 } 1740 1741 static int chv_pinctrl_remove(struct platform_device *pdev) 1742 { 1743 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1744 1745 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1746 pctrl->community->acpi_space_id, 1747 chv_pinctrl_mmio_access_handler); 1748 1749 return 0; 1750 } 1751 1752 #ifdef CONFIG_PM_SLEEP 1753 static int chv_pinctrl_suspend_noirq(struct device *dev) 1754 { 1755 struct chv_pinctrl *pctrl = dev_get_drvdata(dev); 1756 unsigned long flags; 1757 int i; 1758 1759 raw_spin_lock_irqsave(&chv_lock, flags); 1760 1761 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1762 1763 for (i = 0; i < pctrl->community->npins; i++) { 1764 const struct pinctrl_pin_desc *desc; 1765 struct chv_pin_context *ctx; 1766 void __iomem *reg; 1767 1768 desc = &pctrl->community->pins[i]; 1769 if (chv_pad_locked(pctrl, desc->number)) 1770 continue; 1771 1772 ctx = &pctrl->saved_pin_context[i]; 1773 1774 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1775 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1776 1777 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1778 ctx->padctrl1 = readl(reg); 1779 } 1780 1781 raw_spin_unlock_irqrestore(&chv_lock, flags); 1782 1783 return 0; 1784 } 1785 1786 static int chv_pinctrl_resume_noirq(struct device *dev) 1787 { 1788 struct chv_pinctrl *pctrl = dev_get_drvdata(dev); 1789 unsigned long flags; 1790 int i; 1791 1792 raw_spin_lock_irqsave(&chv_lock, flags); 1793 1794 /* 1795 * Mask all interrupts before restoring per-pin configuration 1796 * registers because we don't know in which state BIOS left them 1797 * upon exiting suspend. 1798 */ 1799 chv_writel(0, pctrl->regs + CHV_INTMASK); 1800 1801 for (i = 0; i < pctrl->community->npins; i++) { 1802 const struct pinctrl_pin_desc *desc; 1803 const struct chv_pin_context *ctx; 1804 void __iomem *reg; 1805 u32 val; 1806 1807 desc = &pctrl->community->pins[i]; 1808 if (chv_pad_locked(pctrl, desc->number)) 1809 continue; 1810 1811 ctx = &pctrl->saved_pin_context[i]; 1812 1813 /* Only restore if our saved state differs from the current */ 1814 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1815 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1816 if (ctx->padctrl0 != val) { 1817 chv_writel(ctx->padctrl0, reg); 1818 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1819 desc->number, readl(reg)); 1820 } 1821 1822 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1823 val = readl(reg); 1824 if (ctx->padctrl1 != val) { 1825 chv_writel(ctx->padctrl1, reg); 1826 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1827 desc->number, readl(reg)); 1828 } 1829 } 1830 1831 /* 1832 * Now that all pins are restored to known state, we can restore 1833 * the interrupt mask register as well. 1834 */ 1835 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1836 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1837 1838 raw_spin_unlock_irqrestore(&chv_lock, flags); 1839 1840 return 0; 1841 } 1842 #endif 1843 1844 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1845 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1846 chv_pinctrl_resume_noirq) 1847 }; 1848 1849 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1850 { "INT33FF" }, 1851 { } 1852 }; 1853 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1854 1855 static struct platform_driver chv_pinctrl_driver = { 1856 .probe = chv_pinctrl_probe, 1857 .remove = chv_pinctrl_remove, 1858 .driver = { 1859 .name = "cherryview-pinctrl", 1860 .pm = &chv_pinctrl_pm_ops, 1861 .acpi_match_table = chv_pinctrl_acpi_match, 1862 }, 1863 }; 1864 1865 static int __init chv_pinctrl_init(void) 1866 { 1867 return platform_driver_register(&chv_pinctrl_driver); 1868 } 1869 subsys_initcall(chv_pinctrl_init); 1870 1871 static void __exit chv_pinctrl_exit(void) 1872 { 1873 platform_driver_unregister(&chv_pinctrl_driver); 1874 } 1875 module_exit(chv_pinctrl_exit); 1876 1877 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1878 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1879 MODULE_LICENSE("GPL v2"); 1880