1 /* 2 * Cherryview/Braswell pinctrl driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This driver is based on the original Cherryview GPIO driver by 8 * Ning Li <ning.li@intel.com> 9 * Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/acpi.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/platform_device.h> 28 29 #define CHV_INTSTAT 0x300 30 #define CHV_INTMASK 0x380 31 32 #define FAMILY_PAD_REGS_OFF 0x4400 33 #define FAMILY_PAD_REGS_SIZE 0x400 34 #define MAX_FAMILY_PAD_GPIO_NO 15 35 #define GPIO_REGS_SIZE 8 36 37 #define CHV_PADCTRL0 0x000 38 #define CHV_PADCTRL0_INTSEL_SHIFT 28 39 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 40 #define CHV_PADCTRL0_TERM_UP BIT(23) 41 #define CHV_PADCTRL0_TERM_SHIFT 20 42 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 43 #define CHV_PADCTRL0_TERM_20K 1 44 #define CHV_PADCTRL0_TERM_5K 2 45 #define CHV_PADCTRL0_TERM_1K 4 46 #define CHV_PADCTRL0_PMODE_SHIFT 16 47 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 48 #define CHV_PADCTRL0_GPIOEN BIT(15) 49 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 50 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 51 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 52 #define CHV_PADCTRL0_GPIOCFG_GPO 1 53 #define CHV_PADCTRL0_GPIOCFG_GPI 2 54 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 55 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 56 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 57 58 #define CHV_PADCTRL1 0x004 59 #define CHV_PADCTRL1_CFGLOCK BIT(31) 60 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 61 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 62 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 63 #define CHV_PADCTRL1_ODEN BIT(3) 64 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 65 #define CHV_PADCTRL1_INTWAKECFG_MASK 7 66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 70 71 /** 72 * struct chv_alternate_function - A per group or per pin alternate function 73 * @pin: Pin number (only used in per pin configs) 74 * @mode: Mode the pin should be set in 75 * @invert_oe: Invert OE for this pin 76 */ 77 struct chv_alternate_function { 78 unsigned pin; 79 u8 mode; 80 bool invert_oe; 81 }; 82 83 /** 84 * struct chv_pincgroup - describes a CHV pin group 85 * @name: Name of the group 86 * @pins: An array of pins in this group 87 * @npins: Number of pins in this group 88 * @altfunc: Alternate function applied to all pins in this group 89 * @overrides: Alternate function override per pin or %NULL if not used 90 * @noverrides: Number of per pin alternate function overrides if 91 * @overrides != NULL. 92 */ 93 struct chv_pingroup { 94 const char *name; 95 const unsigned *pins; 96 size_t npins; 97 struct chv_alternate_function altfunc; 98 const struct chv_alternate_function *overrides; 99 size_t noverrides; 100 }; 101 102 /** 103 * struct chv_function - A CHV pinmux function 104 * @name: Name of the function 105 * @groups: An array of groups for this function 106 * @ngroups: Number of groups in @groups 107 */ 108 struct chv_function { 109 const char *name; 110 const char * const *groups; 111 size_t ngroups; 112 }; 113 114 /** 115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 116 * @base: Start pin number 117 * @npins: Number of pins in this range 118 */ 119 struct chv_gpio_pinrange { 120 unsigned base; 121 unsigned npins; 122 }; 123 124 /** 125 * struct chv_community - A community specific configuration 126 * @uid: ACPI _UID used to match the community 127 * @pins: All pins in this community 128 * @npins: Number of pins 129 * @groups: All groups in this community 130 * @ngroups: Number of groups 131 * @functions: All functions in this community 132 * @nfunctions: Number of functions 133 * @ngpios: Number of GPIOs in this community 134 * @gpio_ranges: An array of GPIO ranges in this community 135 * @ngpio_ranges: Number of GPIO ranges 136 * @ngpios: Total number of GPIOs in this community 137 */ 138 struct chv_community { 139 const char *uid; 140 const struct pinctrl_pin_desc *pins; 141 size_t npins; 142 const struct chv_pingroup *groups; 143 size_t ngroups; 144 const struct chv_function *functions; 145 size_t nfunctions; 146 const struct chv_gpio_pinrange *gpio_ranges; 147 size_t ngpio_ranges; 148 size_t ngpios; 149 }; 150 151 /** 152 * struct chv_pinctrl - CHV pinctrl private structure 153 * @dev: Pointer to the parent device 154 * @pctldesc: Pin controller description 155 * @pctldev: Pointer to the pin controller device 156 * @chip: GPIO chip in this pin controller 157 * @regs: MMIO registers 158 * @lock: Lock to serialize register accesses 159 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 160 * offset (in GPIO number space) 161 * @community: Community this pinctrl instance represents 162 * 163 * The first group in @groups is expected to contain all pins that can be 164 * used as GPIOs. 165 */ 166 struct chv_pinctrl { 167 struct device *dev; 168 struct pinctrl_desc pctldesc; 169 struct pinctrl_dev *pctldev; 170 struct gpio_chip chip; 171 void __iomem *regs; 172 spinlock_t lock; 173 unsigned intr_lines[16]; 174 const struct chv_community *community; 175 }; 176 177 #define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip) 178 179 #define ALTERNATE_FUNCTION(p, m, i) \ 180 { \ 181 .pin = (p), \ 182 .mode = (m), \ 183 .invert_oe = (i), \ 184 } 185 186 #define PIN_GROUP(n, p, m, i) \ 187 { \ 188 .name = (n), \ 189 .pins = (p), \ 190 .npins = ARRAY_SIZE((p)), \ 191 .altfunc.mode = (m), \ 192 .altfunc.invert_oe = (i), \ 193 } 194 195 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 196 { \ 197 .name = (n), \ 198 .pins = (p), \ 199 .npins = ARRAY_SIZE((p)), \ 200 .altfunc.mode = (m), \ 201 .altfunc.invert_oe = (i), \ 202 .overrides = (o), \ 203 .noverrides = ARRAY_SIZE((o)), \ 204 } 205 206 #define FUNCTION(n, g) \ 207 { \ 208 .name = (n), \ 209 .groups = (g), \ 210 .ngroups = ARRAY_SIZE((g)), \ 211 } 212 213 #define GPIO_PINRANGE(start, end) \ 214 { \ 215 .base = (start), \ 216 .npins = (end) - (start) + 1, \ 217 } 218 219 static const struct pinctrl_pin_desc southwest_pins[] = { 220 PINCTRL_PIN(0, "FST_SPI_D2"), 221 PINCTRL_PIN(1, "FST_SPI_D0"), 222 PINCTRL_PIN(2, "FST_SPI_CLK"), 223 PINCTRL_PIN(3, "FST_SPI_D3"), 224 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 225 PINCTRL_PIN(5, "FST_SPI_D1"), 226 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 227 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 228 229 PINCTRL_PIN(15, "UART1_RTS_B"), 230 PINCTRL_PIN(16, "UART1_RXD"), 231 PINCTRL_PIN(17, "UART2_RXD"), 232 PINCTRL_PIN(18, "UART1_CTS_B"), 233 PINCTRL_PIN(19, "UART2_RTS_B"), 234 PINCTRL_PIN(20, "UART1_TXD"), 235 PINCTRL_PIN(21, "UART2_TXD"), 236 PINCTRL_PIN(22, "UART2_CTS_B"), 237 238 PINCTRL_PIN(30, "MF_HDA_CLK"), 239 PINCTRL_PIN(31, "MF_HDA_RSTB"), 240 PINCTRL_PIN(32, "MF_HDA_SDIO"), 241 PINCTRL_PIN(33, "MF_HDA_SDO"), 242 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 243 PINCTRL_PIN(35, "MF_HDA_SYNC"), 244 PINCTRL_PIN(36, "MF_HDA_SDI1"), 245 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 246 247 PINCTRL_PIN(45, "I2C5_SDA"), 248 PINCTRL_PIN(46, "I2C4_SDA"), 249 PINCTRL_PIN(47, "I2C6_SDA"), 250 PINCTRL_PIN(48, "I2C5_SCL"), 251 PINCTRL_PIN(49, "I2C_NFC_SDA"), 252 PINCTRL_PIN(50, "I2C4_SCL"), 253 PINCTRL_PIN(51, "I2C6_SCL"), 254 PINCTRL_PIN(52, "I2C_NFC_SCL"), 255 256 PINCTRL_PIN(60, "I2C1_SDA"), 257 PINCTRL_PIN(61, "I2C0_SDA"), 258 PINCTRL_PIN(62, "I2C2_SDA"), 259 PINCTRL_PIN(63, "I2C1_SCL"), 260 PINCTRL_PIN(64, "I2C3_SDA"), 261 PINCTRL_PIN(65, "I2C0_SCL"), 262 PINCTRL_PIN(66, "I2C2_SCL"), 263 PINCTRL_PIN(67, "I2C3_SCL"), 264 265 PINCTRL_PIN(75, "SATA_GP0"), 266 PINCTRL_PIN(76, "SATA_GP1"), 267 PINCTRL_PIN(77, "SATA_LEDN"), 268 PINCTRL_PIN(78, "SATA_GP2"), 269 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 270 PINCTRL_PIN(80, "SATA_GP3"), 271 PINCTRL_PIN(81, "MF_SMB_CLK"), 272 PINCTRL_PIN(82, "MF_SMB_DATA"), 273 274 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 275 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 276 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 277 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 278 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 279 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 280 PINCTRL_PIN(96, "GP_SSP_2_FS"), 281 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 282 }; 283 284 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 285 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 286 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 287 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 288 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 289 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 290 static const unsigned southwest_lpe_pins[] = { 291 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 292 }; 293 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 294 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 295 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 296 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 297 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 298 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 299 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 300 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 301 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 302 303 /* LPE I2S TXD pins need to have invert_oe set */ 304 static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 305 ALTERNATE_FUNCTION(30, 1, true), 306 ALTERNATE_FUNCTION(34, 1, true), 307 ALTERNATE_FUNCTION(97, 1, true), 308 }; 309 310 /* 311 * Two spi3 chipselects are available in different mode than the main spi3 312 * functionality, which is using mode 1. 313 */ 314 static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 315 ALTERNATE_FUNCTION(76, 3, false), 316 ALTERNATE_FUNCTION(80, 3, false), 317 }; 318 319 static const struct chv_pingroup southwest_groups[] = { 320 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 321 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 322 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 323 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 324 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 325 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 326 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 327 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 328 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 329 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 330 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 331 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 332 333 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 334 southwest_lpe_altfuncs), 335 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 336 southwest_spi3_altfuncs), 337 }; 338 339 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 340 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 341 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 342 static const char * const southwest_hda_groups[] = { "hda_grp" }; 343 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 344 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 345 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 346 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 347 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 348 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 349 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 350 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 351 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 352 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 353 354 /* 355 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 356 * enabled only as GPIOs. 357 */ 358 static const struct chv_function southwest_functions[] = { 359 FUNCTION("uart0", southwest_uart0_groups), 360 FUNCTION("uart1", southwest_uart1_groups), 361 FUNCTION("uart2", southwest_uart2_groups), 362 FUNCTION("hda", southwest_hda_groups), 363 FUNCTION("lpe", southwest_lpe_groups), 364 FUNCTION("i2c0", southwest_i2c0_groups), 365 FUNCTION("i2c1", southwest_i2c1_groups), 366 FUNCTION("i2c2", southwest_i2c2_groups), 367 FUNCTION("i2c3", southwest_i2c3_groups), 368 FUNCTION("i2c4", southwest_i2c4_groups), 369 FUNCTION("i2c5", southwest_i2c5_groups), 370 FUNCTION("i2c6", southwest_i2c6_groups), 371 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 372 FUNCTION("spi3", southwest_spi3_groups), 373 }; 374 375 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 376 GPIO_PINRANGE(0, 7), 377 GPIO_PINRANGE(15, 22), 378 GPIO_PINRANGE(30, 37), 379 GPIO_PINRANGE(45, 52), 380 GPIO_PINRANGE(60, 67), 381 GPIO_PINRANGE(75, 82), 382 GPIO_PINRANGE(90, 97), 383 }; 384 385 static const struct chv_community southwest_community = { 386 .uid = "1", 387 .pins = southwest_pins, 388 .npins = ARRAY_SIZE(southwest_pins), 389 .groups = southwest_groups, 390 .ngroups = ARRAY_SIZE(southwest_groups), 391 .functions = southwest_functions, 392 .nfunctions = ARRAY_SIZE(southwest_functions), 393 .gpio_ranges = southwest_gpio_ranges, 394 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 395 .ngpios = ARRAY_SIZE(southwest_pins), 396 }; 397 398 static const struct pinctrl_pin_desc north_pins[] = { 399 PINCTRL_PIN(0, "GPIO_DFX_0"), 400 PINCTRL_PIN(1, "GPIO_DFX_3"), 401 PINCTRL_PIN(2, "GPIO_DFX_7"), 402 PINCTRL_PIN(3, "GPIO_DFX_1"), 403 PINCTRL_PIN(4, "GPIO_DFX_5"), 404 PINCTRL_PIN(5, "GPIO_DFX_4"), 405 PINCTRL_PIN(6, "GPIO_DFX_8"), 406 PINCTRL_PIN(7, "GPIO_DFX_2"), 407 PINCTRL_PIN(8, "GPIO_DFX_6"), 408 409 PINCTRL_PIN(15, "GPIO_SUS0"), 410 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 411 PINCTRL_PIN(17, "GPIO_SUS3"), 412 PINCTRL_PIN(18, "GPIO_SUS7"), 413 PINCTRL_PIN(19, "GPIO_SUS1"), 414 PINCTRL_PIN(20, "GPIO_SUS5"), 415 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 416 PINCTRL_PIN(22, "GPIO_SUS4"), 417 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 418 PINCTRL_PIN(24, "GPIO_SUS2"), 419 PINCTRL_PIN(25, "GPIO_SUS6"), 420 PINCTRL_PIN(26, "CX_PREQ_B"), 421 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 422 423 PINCTRL_PIN(30, "TRST_B"), 424 PINCTRL_PIN(31, "TCK"), 425 PINCTRL_PIN(32, "PROCHOT_B"), 426 PINCTRL_PIN(33, "SVIDO_DATA"), 427 PINCTRL_PIN(34, "TMS"), 428 PINCTRL_PIN(35, "CX_PRDY_B_2"), 429 PINCTRL_PIN(36, "TDO_2"), 430 PINCTRL_PIN(37, "CX_PRDY_B"), 431 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 432 PINCTRL_PIN(39, "TDO"), 433 PINCTRL_PIN(40, "SVIDO_CLK"), 434 PINCTRL_PIN(41, "TDI"), 435 436 PINCTRL_PIN(45, "GP_CAMERASB_05"), 437 PINCTRL_PIN(46, "GP_CAMERASB_02"), 438 PINCTRL_PIN(47, "GP_CAMERASB_08"), 439 PINCTRL_PIN(48, "GP_CAMERASB_00"), 440 PINCTRL_PIN(49, "GP_CAMERASB_06"), 441 PINCTRL_PIN(50, "GP_CAMERASB_10"), 442 PINCTRL_PIN(51, "GP_CAMERASB_03"), 443 PINCTRL_PIN(52, "GP_CAMERASB_09"), 444 PINCTRL_PIN(53, "GP_CAMERASB_01"), 445 PINCTRL_PIN(54, "GP_CAMERASB_07"), 446 PINCTRL_PIN(55, "GP_CAMERASB_11"), 447 PINCTRL_PIN(56, "GP_CAMERASB_04"), 448 449 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 450 PINCTRL_PIN(61, "HV_DDI0_HPD"), 451 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 452 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 453 PINCTRL_PIN(64, "HV_DDI1_HPD"), 454 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 455 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 456 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 457 PINCTRL_PIN(68, "HV_DDI2_HPD"), 458 PINCTRL_PIN(69, "PANEL1_VDDEN"), 459 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 460 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 461 PINCTRL_PIN(72, "PANEL0_VDDEN"), 462 }; 463 464 static const struct chv_gpio_pinrange north_gpio_ranges[] = { 465 GPIO_PINRANGE(0, 8), 466 GPIO_PINRANGE(15, 27), 467 GPIO_PINRANGE(30, 41), 468 GPIO_PINRANGE(45, 56), 469 GPIO_PINRANGE(60, 72), 470 }; 471 472 static const struct chv_community north_community = { 473 .uid = "2", 474 .pins = north_pins, 475 .npins = ARRAY_SIZE(north_pins), 476 .gpio_ranges = north_gpio_ranges, 477 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 478 .ngpios = ARRAY_SIZE(north_pins), 479 }; 480 481 static const struct pinctrl_pin_desc east_pins[] = { 482 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 483 PINCTRL_PIN(1, "PMU_BATLOW_B"), 484 PINCTRL_PIN(2, "SUS_STAT_B"), 485 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 486 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 487 PINCTRL_PIN(5, "PMU_PLTRST_B"), 488 PINCTRL_PIN(6, "PMU_SUSCLK"), 489 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 490 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 491 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 492 PINCTRL_PIN(10, "PMU_WAKE_B"), 493 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 494 495 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 496 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 497 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 498 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 499 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 500 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 501 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 502 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 503 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 504 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 505 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 506 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 507 }; 508 509 static const struct chv_gpio_pinrange east_gpio_ranges[] = { 510 GPIO_PINRANGE(0, 11), 511 GPIO_PINRANGE(15, 26), 512 }; 513 514 static const struct chv_community east_community = { 515 .uid = "3", 516 .pins = east_pins, 517 .npins = ARRAY_SIZE(east_pins), 518 .gpio_ranges = east_gpio_ranges, 519 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 520 .ngpios = ARRAY_SIZE(east_pins), 521 }; 522 523 static const struct pinctrl_pin_desc southeast_pins[] = { 524 PINCTRL_PIN(0, "MF_PLT_CLK0"), 525 PINCTRL_PIN(1, "PWM1"), 526 PINCTRL_PIN(2, "MF_PLT_CLK1"), 527 PINCTRL_PIN(3, "MF_PLT_CLK4"), 528 PINCTRL_PIN(4, "MF_PLT_CLK3"), 529 PINCTRL_PIN(5, "PWM0"), 530 PINCTRL_PIN(6, "MF_PLT_CLK5"), 531 PINCTRL_PIN(7, "MF_PLT_CLK2"), 532 533 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 534 PINCTRL_PIN(16, "SDMMC1_CLK"), 535 PINCTRL_PIN(17, "SDMMC1_D0"), 536 PINCTRL_PIN(18, "SDMMC2_D1"), 537 PINCTRL_PIN(19, "SDMMC2_CLK"), 538 PINCTRL_PIN(20, "SDMMC1_D2"), 539 PINCTRL_PIN(21, "SDMMC2_D2"), 540 PINCTRL_PIN(22, "SDMMC2_CMD"), 541 PINCTRL_PIN(23, "SDMMC1_CMD"), 542 PINCTRL_PIN(24, "SDMMC1_D1"), 543 PINCTRL_PIN(25, "SDMMC2_D0"), 544 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 545 546 PINCTRL_PIN(30, "SDMMC3_D1"), 547 PINCTRL_PIN(31, "SDMMC3_CLK"), 548 PINCTRL_PIN(32, "SDMMC3_D3"), 549 PINCTRL_PIN(33, "SDMMC3_D2"), 550 PINCTRL_PIN(34, "SDMMC3_CMD"), 551 PINCTRL_PIN(35, "SDMMC3_D0"), 552 553 PINCTRL_PIN(45, "MF_LPC_AD2"), 554 PINCTRL_PIN(46, "LPC_CLKRUNB"), 555 PINCTRL_PIN(47, "MF_LPC_AD0"), 556 PINCTRL_PIN(48, "LPC_FRAMEB"), 557 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 558 PINCTRL_PIN(50, "MF_LPC_AD3"), 559 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 560 PINCTRL_PIN(52, "MF_LPC_AD1"), 561 562 PINCTRL_PIN(60, "SPI1_MISO"), 563 PINCTRL_PIN(61, "SPI1_CSO_B"), 564 PINCTRL_PIN(62, "SPI1_CLK"), 565 PINCTRL_PIN(63, "MMC1_D6"), 566 PINCTRL_PIN(64, "SPI1_MOSI"), 567 PINCTRL_PIN(65, "MMC1_D5"), 568 PINCTRL_PIN(66, "SPI1_CS1_B"), 569 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 570 PINCTRL_PIN(68, "MMC1_D7"), 571 PINCTRL_PIN(69, "MMC1_RCLK"), 572 573 PINCTRL_PIN(75, "USB_OC1_B"), 574 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 575 PINCTRL_PIN(77, "GPIO_ALERT"), 576 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 577 PINCTRL_PIN(79, "ILB_SERIRQ"), 578 PINCTRL_PIN(80, "USB_OC0_B"), 579 PINCTRL_PIN(81, "SDMMC3_CD_B"), 580 PINCTRL_PIN(82, "SPKR"), 581 PINCTRL_PIN(83, "SUSPWRDNACK"), 582 PINCTRL_PIN(84, "SPARE_PIN"), 583 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 584 }; 585 586 static const unsigned southeast_pwm0_pins[] = { 5 }; 587 static const unsigned southeast_pwm1_pins[] = { 1 }; 588 static const unsigned southeast_sdmmc1_pins[] = { 589 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 590 }; 591 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 592 static const unsigned southeast_sdmmc3_pins[] = { 593 30, 31, 32, 33, 34, 35, 78, 81, 85, 594 }; 595 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 596 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 597 598 static const struct chv_pingroup southeast_groups[] = { 599 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 600 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 601 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 602 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 603 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 604 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 605 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 606 }; 607 608 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 609 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 610 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 611 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 612 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 613 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 614 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 615 616 static const struct chv_function southeast_functions[] = { 617 FUNCTION("pwm0", southeast_pwm0_groups), 618 FUNCTION("pwm1", southeast_pwm1_groups), 619 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 620 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 621 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 622 FUNCTION("spi1", southeast_spi1_groups), 623 FUNCTION("spi2", southeast_spi2_groups), 624 }; 625 626 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 627 GPIO_PINRANGE(0, 7), 628 GPIO_PINRANGE(15, 26), 629 GPIO_PINRANGE(30, 35), 630 GPIO_PINRANGE(45, 52), 631 GPIO_PINRANGE(60, 69), 632 GPIO_PINRANGE(75, 85), 633 }; 634 635 static const struct chv_community southeast_community = { 636 .uid = "4", 637 .pins = southeast_pins, 638 .npins = ARRAY_SIZE(southeast_pins), 639 .groups = southeast_groups, 640 .ngroups = ARRAY_SIZE(southeast_groups), 641 .functions = southeast_functions, 642 .nfunctions = ARRAY_SIZE(southeast_functions), 643 .gpio_ranges = southeast_gpio_ranges, 644 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 645 .ngpios = ARRAY_SIZE(southeast_pins), 646 }; 647 648 static const struct chv_community *chv_communities[] = { 649 &southwest_community, 650 &north_community, 651 &east_community, 652 &southeast_community, 653 }; 654 655 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 656 unsigned reg) 657 { 658 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 659 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 660 661 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 662 GPIO_REGS_SIZE * pad_no; 663 664 return pctrl->regs + offset + reg; 665 } 666 667 static void chv_writel(u32 value, void __iomem *reg) 668 { 669 writel(value, reg); 670 /* simple readback to confirm the bus transferring done */ 671 readl(reg); 672 } 673 674 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 675 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 676 { 677 void __iomem *reg; 678 679 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 680 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 681 } 682 683 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 684 { 685 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 686 687 return pctrl->community->ngroups; 688 } 689 690 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 691 unsigned group) 692 { 693 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 694 695 return pctrl->community->groups[group].name; 696 } 697 698 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 699 const unsigned **pins, unsigned *npins) 700 { 701 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 702 703 *pins = pctrl->community->groups[group].pins; 704 *npins = pctrl->community->groups[group].npins; 705 return 0; 706 } 707 708 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 709 unsigned offset) 710 { 711 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 712 unsigned long flags; 713 u32 ctrl0, ctrl1; 714 bool locked; 715 716 spin_lock_irqsave(&pctrl->lock, flags); 717 718 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 719 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 720 locked = chv_pad_locked(pctrl, offset); 721 722 spin_unlock_irqrestore(&pctrl->lock, flags); 723 724 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 725 seq_puts(s, "GPIO "); 726 } else { 727 u32 mode; 728 729 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 730 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 731 732 seq_printf(s, "mode %d ", mode); 733 } 734 735 seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); 736 737 if (locked) 738 seq_puts(s, " [LOCKED]"); 739 } 740 741 static const struct pinctrl_ops chv_pinctrl_ops = { 742 .get_groups_count = chv_get_groups_count, 743 .get_group_name = chv_get_group_name, 744 .get_group_pins = chv_get_group_pins, 745 .pin_dbg_show = chv_pin_dbg_show, 746 }; 747 748 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 749 { 750 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 751 752 return pctrl->community->nfunctions; 753 } 754 755 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 756 unsigned function) 757 { 758 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 759 760 return pctrl->community->functions[function].name; 761 } 762 763 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 764 unsigned function, 765 const char * const **groups, 766 unsigned * const ngroups) 767 { 768 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 769 770 *groups = pctrl->community->functions[function].groups; 771 *ngroups = pctrl->community->functions[function].ngroups; 772 return 0; 773 } 774 775 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 776 unsigned group) 777 { 778 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 779 const struct chv_pingroup *grp; 780 unsigned long flags; 781 int i; 782 783 grp = &pctrl->community->groups[group]; 784 785 spin_lock_irqsave(&pctrl->lock, flags); 786 787 /* Check first that the pad is not locked */ 788 for (i = 0; i < grp->npins; i++) { 789 if (chv_pad_locked(pctrl, grp->pins[i])) { 790 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 791 grp->pins[i]); 792 spin_unlock_irqrestore(&pctrl->lock, flags); 793 return -EBUSY; 794 } 795 } 796 797 for (i = 0; i < grp->npins; i++) { 798 const struct chv_alternate_function *altfunc = &grp->altfunc; 799 int pin = grp->pins[i]; 800 void __iomem *reg; 801 u32 value; 802 803 /* Check if there is pin-specific config */ 804 if (grp->overrides) { 805 int j; 806 807 for (j = 0; j < grp->noverrides; j++) { 808 if (grp->overrides[j].pin == pin) { 809 altfunc = &grp->overrides[j]; 810 break; 811 } 812 } 813 } 814 815 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 816 value = readl(reg); 817 /* Disable GPIO mode */ 818 value &= ~CHV_PADCTRL0_GPIOEN; 819 /* Set to desired mode */ 820 value &= ~CHV_PADCTRL0_PMODE_MASK; 821 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 822 chv_writel(value, reg); 823 824 /* Update for invert_oe */ 825 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 826 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 827 if (altfunc->invert_oe) 828 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 829 chv_writel(value, reg); 830 831 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 832 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 833 } 834 835 spin_unlock_irqrestore(&pctrl->lock, flags); 836 837 return 0; 838 } 839 840 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 841 struct pinctrl_gpio_range *range, 842 unsigned offset) 843 { 844 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 845 unsigned long flags; 846 void __iomem *reg; 847 u32 value; 848 849 spin_lock_irqsave(&pctrl->lock, flags); 850 851 if (chv_pad_locked(pctrl, offset)) { 852 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 853 if (!(value & CHV_PADCTRL0_GPIOEN)) { 854 /* Locked so cannot enable */ 855 spin_unlock_irqrestore(&pctrl->lock, flags); 856 return -EBUSY; 857 } 858 } else { 859 int i; 860 861 /* Reset the interrupt mapping */ 862 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 863 if (pctrl->intr_lines[i] == offset) { 864 pctrl->intr_lines[i] = 0; 865 break; 866 } 867 } 868 869 /* Disable interrupt generation */ 870 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 871 value = readl(reg); 872 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 873 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 874 chv_writel(value, reg); 875 876 /* Switch to a GPIO mode */ 877 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 878 value = readl(reg) | CHV_PADCTRL0_GPIOEN; 879 chv_writel(value, reg); 880 } 881 882 spin_unlock_irqrestore(&pctrl->lock, flags); 883 884 return 0; 885 } 886 887 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 888 struct pinctrl_gpio_range *range, 889 unsigned offset) 890 { 891 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 892 unsigned long flags; 893 void __iomem *reg; 894 u32 value; 895 896 spin_lock_irqsave(&pctrl->lock, flags); 897 898 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 899 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 900 chv_writel(value, reg); 901 902 spin_unlock_irqrestore(&pctrl->lock, flags); 903 } 904 905 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 906 struct pinctrl_gpio_range *range, 907 unsigned offset, bool input) 908 { 909 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 910 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 911 unsigned long flags; 912 u32 ctrl0; 913 914 spin_lock_irqsave(&pctrl->lock, flags); 915 916 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 917 if (input) 918 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 919 else 920 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 921 chv_writel(ctrl0, reg); 922 923 spin_unlock_irqrestore(&pctrl->lock, flags); 924 925 return 0; 926 } 927 928 static const struct pinmux_ops chv_pinmux_ops = { 929 .get_functions_count = chv_get_functions_count, 930 .get_function_name = chv_get_function_name, 931 .get_function_groups = chv_get_function_groups, 932 .set_mux = chv_pinmux_set_mux, 933 .gpio_request_enable = chv_gpio_request_enable, 934 .gpio_disable_free = chv_gpio_disable_free, 935 .gpio_set_direction = chv_gpio_set_direction, 936 }; 937 938 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 939 unsigned long *config) 940 { 941 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 942 enum pin_config_param param = pinconf_to_config_param(*config); 943 unsigned long flags; 944 u32 ctrl0, ctrl1; 945 u16 arg = 0; 946 u32 term; 947 948 spin_lock_irqsave(&pctrl->lock, flags); 949 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 950 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 951 spin_unlock_irqrestore(&pctrl->lock, flags); 952 953 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 954 955 switch (param) { 956 case PIN_CONFIG_BIAS_DISABLE: 957 if (term) 958 return -EINVAL; 959 break; 960 961 case PIN_CONFIG_BIAS_PULL_UP: 962 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 963 return -EINVAL; 964 965 switch (term) { 966 case CHV_PADCTRL0_TERM_20K: 967 arg = 20000; 968 break; 969 case CHV_PADCTRL0_TERM_5K: 970 arg = 5000; 971 break; 972 case CHV_PADCTRL0_TERM_1K: 973 arg = 1000; 974 break; 975 } 976 977 break; 978 979 case PIN_CONFIG_BIAS_PULL_DOWN: 980 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 981 return -EINVAL; 982 983 switch (term) { 984 case CHV_PADCTRL0_TERM_20K: 985 arg = 20000; 986 break; 987 case CHV_PADCTRL0_TERM_5K: 988 arg = 5000; 989 break; 990 } 991 992 break; 993 994 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 995 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 996 return -EINVAL; 997 break; 998 999 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1000 u32 cfg; 1001 1002 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1003 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1004 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1005 return -EINVAL; 1006 1007 break; 1008 } 1009 1010 default: 1011 return -ENOTSUPP; 1012 } 1013 1014 *config = pinconf_to_config_packed(param, arg); 1015 return 0; 1016 } 1017 1018 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 1019 enum pin_config_param param, u16 arg) 1020 { 1021 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1022 unsigned long flags; 1023 u32 ctrl0, pull; 1024 1025 spin_lock_irqsave(&pctrl->lock, flags); 1026 ctrl0 = readl(reg); 1027 1028 switch (param) { 1029 case PIN_CONFIG_BIAS_DISABLE: 1030 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1031 break; 1032 1033 case PIN_CONFIG_BIAS_PULL_UP: 1034 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1035 1036 switch (arg) { 1037 case 1000: 1038 /* For 1k there is only pull up */ 1039 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1040 break; 1041 case 5000: 1042 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1043 break; 1044 case 20000: 1045 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1046 break; 1047 default: 1048 spin_unlock_irqrestore(&pctrl->lock, flags); 1049 return -EINVAL; 1050 } 1051 1052 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1053 break; 1054 1055 case PIN_CONFIG_BIAS_PULL_DOWN: 1056 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1057 1058 switch (arg) { 1059 case 5000: 1060 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1061 break; 1062 case 20000: 1063 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1064 break; 1065 default: 1066 spin_unlock_irqrestore(&pctrl->lock, flags); 1067 return -EINVAL; 1068 } 1069 1070 ctrl0 |= pull; 1071 break; 1072 1073 default: 1074 spin_unlock_irqrestore(&pctrl->lock, flags); 1075 return -EINVAL; 1076 } 1077 1078 chv_writel(ctrl0, reg); 1079 spin_unlock_irqrestore(&pctrl->lock, flags); 1080 1081 return 0; 1082 } 1083 1084 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1085 unsigned long *configs, unsigned nconfigs) 1086 { 1087 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1088 enum pin_config_param param; 1089 int i, ret; 1090 u16 arg; 1091 1092 if (chv_pad_locked(pctrl, pin)) 1093 return -EBUSY; 1094 1095 for (i = 0; i < nconfigs; i++) { 1096 param = pinconf_to_config_param(configs[i]); 1097 arg = pinconf_to_config_argument(configs[i]); 1098 1099 switch (param) { 1100 case PIN_CONFIG_BIAS_DISABLE: 1101 case PIN_CONFIG_BIAS_PULL_UP: 1102 case PIN_CONFIG_BIAS_PULL_DOWN: 1103 ret = chv_config_set_pull(pctrl, pin, param, arg); 1104 if (ret) 1105 return ret; 1106 break; 1107 1108 default: 1109 return -ENOTSUPP; 1110 } 1111 1112 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1113 param, arg); 1114 } 1115 1116 return 0; 1117 } 1118 1119 static const struct pinconf_ops chv_pinconf_ops = { 1120 .is_generic = true, 1121 .pin_config_set = chv_config_set, 1122 .pin_config_get = chv_config_get, 1123 }; 1124 1125 static struct pinctrl_desc chv_pinctrl_desc = { 1126 .pctlops = &chv_pinctrl_ops, 1127 .pmxops = &chv_pinmux_ops, 1128 .confops = &chv_pinconf_ops, 1129 .owner = THIS_MODULE, 1130 }; 1131 1132 static int chv_gpio_request(struct gpio_chip *chip, unsigned offset) 1133 { 1134 return pinctrl_request_gpio(chip->base + offset); 1135 } 1136 1137 static void chv_gpio_free(struct gpio_chip *chip, unsigned offset) 1138 { 1139 pinctrl_free_gpio(chip->base + offset); 1140 } 1141 1142 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 1143 unsigned offset) 1144 { 1145 return pctrl->community->pins[offset].number; 1146 } 1147 1148 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1149 { 1150 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1151 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1152 u32 ctrl0, cfg; 1153 1154 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1155 1156 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1157 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1158 1159 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1160 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1161 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1162 } 1163 1164 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1165 { 1166 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1167 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1168 unsigned long flags; 1169 void __iomem *reg; 1170 u32 ctrl0; 1171 1172 spin_lock_irqsave(&pctrl->lock, flags); 1173 1174 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1175 ctrl0 = readl(reg); 1176 1177 if (value) 1178 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1179 else 1180 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1181 1182 chv_writel(ctrl0, reg); 1183 1184 spin_unlock_irqrestore(&pctrl->lock, flags); 1185 } 1186 1187 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1188 { 1189 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1190 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1191 u32 ctrl0, direction; 1192 1193 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1194 1195 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1196 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1197 1198 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1199 } 1200 1201 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1202 { 1203 return pinctrl_gpio_direction_input(chip->base + offset); 1204 } 1205 1206 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1207 int value) 1208 { 1209 return pinctrl_gpio_direction_output(chip->base + offset); 1210 } 1211 1212 static const struct gpio_chip chv_gpio_chip = { 1213 .owner = THIS_MODULE, 1214 .request = chv_gpio_request, 1215 .free = chv_gpio_free, 1216 .get_direction = chv_gpio_get_direction, 1217 .direction_input = chv_gpio_direction_input, 1218 .direction_output = chv_gpio_direction_output, 1219 .get = chv_gpio_get, 1220 .set = chv_gpio_set, 1221 }; 1222 1223 static void chv_gpio_irq_ack(struct irq_data *d) 1224 { 1225 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1226 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1227 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1228 u32 intr_line; 1229 1230 spin_lock(&pctrl->lock); 1231 1232 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1233 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1234 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1235 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1236 1237 spin_unlock(&pctrl->lock); 1238 } 1239 1240 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1241 { 1242 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1243 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1244 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1245 u32 value, intr_line; 1246 unsigned long flags; 1247 1248 spin_lock_irqsave(&pctrl->lock, flags); 1249 1250 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1251 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1252 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1253 1254 value = readl(pctrl->regs + CHV_INTMASK); 1255 if (mask) 1256 value &= ~BIT(intr_line); 1257 else 1258 value |= BIT(intr_line); 1259 chv_writel(value, pctrl->regs + CHV_INTMASK); 1260 1261 spin_unlock_irqrestore(&pctrl->lock, flags); 1262 } 1263 1264 static void chv_gpio_irq_mask(struct irq_data *d) 1265 { 1266 chv_gpio_irq_mask_unmask(d, true); 1267 } 1268 1269 static void chv_gpio_irq_unmask(struct irq_data *d) 1270 { 1271 chv_gpio_irq_mask_unmask(d, false); 1272 } 1273 1274 static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 1275 { 1276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1277 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1278 unsigned offset = irqd_to_hwirq(d); 1279 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1280 unsigned long flags; 1281 u32 value; 1282 1283 spin_lock_irqsave(&pctrl->lock, flags); 1284 1285 /* 1286 * Pins which can be used as shared interrupt are configured in 1287 * BIOS. Driver trusts BIOS configurations and assigns different 1288 * handler according to the irq type. 1289 * 1290 * Driver needs to save the mapping between each pin and 1291 * its interrupt line. 1292 * 1. If the pin cfg is locked in BIOS: 1293 * Trust BIOS has programmed IntWakeCfg bits correctly, 1294 * driver just needs to save the mapping. 1295 * 2. If the pin cfg is not locked in BIOS: 1296 * Driver programs the IntWakeCfg bits and save the mapping. 1297 */ 1298 if (!chv_pad_locked(pctrl, pin)) { 1299 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1300 1301 value = readl(reg); 1302 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1303 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1304 1305 if (type & IRQ_TYPE_EDGE_BOTH) { 1306 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1307 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1308 else if (type & IRQ_TYPE_EDGE_RISING) 1309 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1310 else if (type & IRQ_TYPE_EDGE_FALLING) 1311 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1312 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1313 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1314 if (type & IRQ_TYPE_LEVEL_LOW) 1315 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1316 } 1317 1318 chv_writel(value, reg); 1319 } 1320 1321 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1322 value &= CHV_PADCTRL0_INTSEL_MASK; 1323 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1324 1325 pctrl->intr_lines[value] = offset; 1326 1327 if (type & IRQ_TYPE_EDGE_BOTH) 1328 __irq_set_handler_locked(d->irq, handle_edge_irq); 1329 else if (type & IRQ_TYPE_LEVEL_MASK) 1330 __irq_set_handler_locked(d->irq, handle_level_irq); 1331 1332 spin_unlock_irqrestore(&pctrl->lock, flags); 1333 1334 return 0; 1335 } 1336 1337 static struct irq_chip chv_gpio_irqchip = { 1338 .name = "chv-gpio", 1339 .irq_ack = chv_gpio_irq_ack, 1340 .irq_mask = chv_gpio_irq_mask, 1341 .irq_unmask = chv_gpio_irq_unmask, 1342 .irq_set_type = chv_gpio_irq_type, 1343 .flags = IRQCHIP_SKIP_SET_WAKE, 1344 }; 1345 1346 static void chv_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1347 { 1348 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1349 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1350 struct irq_chip *chip = irq_get_chip(irq); 1351 unsigned long pending; 1352 u32 intr_line; 1353 1354 chained_irq_enter(chip, desc); 1355 1356 pending = readl(pctrl->regs + CHV_INTSTAT); 1357 for_each_set_bit(intr_line, &pending, 16) { 1358 unsigned irq, offset; 1359 1360 offset = pctrl->intr_lines[intr_line]; 1361 irq = irq_find_mapping(gc->irqdomain, offset); 1362 generic_handle_irq(irq); 1363 } 1364 1365 chained_irq_exit(chip, desc); 1366 } 1367 1368 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1369 { 1370 const struct chv_gpio_pinrange *range; 1371 struct gpio_chip *chip = &pctrl->chip; 1372 int ret, i, offset; 1373 1374 *chip = chv_gpio_chip; 1375 1376 chip->ngpio = pctrl->community->ngpios; 1377 chip->label = dev_name(pctrl->dev); 1378 chip->dev = pctrl->dev; 1379 chip->base = -1; 1380 1381 ret = gpiochip_add(chip); 1382 if (ret) { 1383 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1384 return ret; 1385 } 1386 1387 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 1388 range = &pctrl->community->gpio_ranges[i]; 1389 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 1390 range->base, range->npins); 1391 if (ret) { 1392 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1393 goto fail; 1394 } 1395 1396 offset += range->npins; 1397 } 1398 1399 /* Mask and clear all interrupts */ 1400 chv_writel(0, pctrl->regs + CHV_INTMASK); 1401 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1402 1403 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1404 handle_simple_irq, IRQ_TYPE_NONE); 1405 if (ret) { 1406 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1407 goto fail; 1408 } 1409 1410 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1411 chv_gpio_irq_handler); 1412 return 0; 1413 1414 fail: 1415 gpiochip_remove(chip); 1416 1417 return ret; 1418 } 1419 1420 static int chv_pinctrl_probe(struct platform_device *pdev) 1421 { 1422 struct chv_pinctrl *pctrl; 1423 struct acpi_device *adev; 1424 struct resource *res; 1425 int ret, irq, i; 1426 1427 adev = ACPI_COMPANION(&pdev->dev); 1428 if (!adev) 1429 return -ENODEV; 1430 1431 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1432 if (!pctrl) 1433 return -ENOMEM; 1434 1435 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1436 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1437 pctrl->community = chv_communities[i]; 1438 break; 1439 } 1440 if (i == ARRAY_SIZE(chv_communities)) 1441 return -ENODEV; 1442 1443 spin_lock_init(&pctrl->lock); 1444 pctrl->dev = &pdev->dev; 1445 1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1447 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1448 if (IS_ERR(pctrl->regs)) 1449 return PTR_ERR(pctrl->regs); 1450 1451 irq = platform_get_irq(pdev, 0); 1452 if (irq < 0) { 1453 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1454 return irq; 1455 } 1456 1457 pctrl->pctldesc = chv_pinctrl_desc; 1458 pctrl->pctldesc.name = dev_name(&pdev->dev); 1459 pctrl->pctldesc.pins = pctrl->community->pins; 1460 pctrl->pctldesc.npins = pctrl->community->npins; 1461 1462 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); 1463 if (!pctrl->pctldev) { 1464 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1465 return -ENODEV; 1466 } 1467 1468 ret = chv_gpio_probe(pctrl, irq); 1469 if (ret) { 1470 pinctrl_unregister(pctrl->pctldev); 1471 return ret; 1472 } 1473 1474 platform_set_drvdata(pdev, pctrl); 1475 1476 return 0; 1477 } 1478 1479 static int chv_pinctrl_remove(struct platform_device *pdev) 1480 { 1481 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1482 1483 gpiochip_remove(&pctrl->chip); 1484 pinctrl_unregister(pctrl->pctldev); 1485 1486 return 0; 1487 } 1488 1489 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1490 { "INT33FF" }, 1491 { } 1492 }; 1493 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1494 1495 static struct platform_driver chv_pinctrl_driver = { 1496 .probe = chv_pinctrl_probe, 1497 .remove = chv_pinctrl_remove, 1498 .driver = { 1499 .name = "cherryview-pinctrl", 1500 .owner = THIS_MODULE, 1501 .acpi_match_table = chv_pinctrl_acpi_match, 1502 }, 1503 }; 1504 1505 static int __init chv_pinctrl_init(void) 1506 { 1507 return platform_driver_register(&chv_pinctrl_driver); 1508 } 1509 subsys_initcall(chv_pinctrl_init); 1510 1511 static void __exit chv_pinctrl_exit(void) 1512 { 1513 platform_driver_unregister(&chv_pinctrl_driver); 1514 } 1515 module_exit(chv_pinctrl_exit); 1516 1517 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1518 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1519 MODULE_LICENSE("GPL v2"); 1520